Secureboot memory layout support.

    * Start kernel in 1/4 cache mode per Secureboot.
    * Copy Secureboot header for base image for later use.
    * Blind-purge bottom half of cache.
    * Add bottom of cache into memory maps for 1/2 cache mode.

RTC: 64762
Change-Id: I1b45f30a2d45c9709d4fd486cfe0ca2ce86b051c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3773
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 10 insertions, 1 deletions

diff --git a/src/include/kernel/misc.H b/src/include/kernel/misc.H
index f0fe0ffd0..544df7c88 100644
--- a/src/include/kernel/misc.H
+++ b/src/include/kernel/misc.H
@@ -121,6 +121,15 @@ namespace KernelMisc
 
     };
 
+    /** @fn expand_half_cache
+     *
+     *  @brief Expands the image footprint from a quarter-cache (top 512k of
+     *         each cache column) to a half-cache (full 1mb of each column).
+     *
+     *  @return 0 or -errno
+     */
+    int expand_half_cache();
+
     /** @fn expand_full_cache
      *
      *  @brief Expands the image footprint from a half-cache to full-cache
@@ -155,7 +164,7 @@ namespace KernelMisc
      *     NOTE: This function is a wrapper function for writeScratchReg that
      *     takes care of modifying the scratch register address value depending
      *     on the getCPUType.   The writeScratchReg takes the scratch address
-     *     passed in and puts that date in that register using assembly code
+     *     passed in and puts that data in that register using assembly code
      *
      *  @param[in] uint64_t - scratch_addr
      *  @param[in] uint64_t - Data