PB Purge Scoms if PBIEQ clock domain is being stopped

Change-Id: I5b76dcf385809efff354120486acf8a0acc1502c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35629
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35631
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 64 insertions, 2 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
index e86fd69fb..2983f0e04 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
@@ -53,7 +53,10 @@
 enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS
 {
     CACHE_CLK_STOP_POLLING_HW_NS_DELAY     = 10000,
-    CACHE_CLK_STOP_POLLING_SIM_CYCLE_DELAY = 320000
+    CACHE_CLK_STOP_POLLING_SIM_CYCLE_DELAY = 320000,
+    PB_PURGE_CACHE_STOP_POLLING_DELAY_HW_MILLISEC = 1000000ULL, // 1msec
+    PB_PURGE_CACHE_STOP_POLLING_DELAY_SIM_CYCLES = 10000ULL,
+    PB_PURGE_CACHE_STOP_POLLING_TIMEOUT = 10,
 };
 
 //------------------------------------------------------------------------------
@@ -75,10 +78,59 @@ p9_hcd_cache_stopclocks(
     uint32_t                                       l_loops1ms;
     uint8_t                                        l_attr_chip_unit_pos = 0;
     uint8_t                                        l_attr_vdm_enable;
+    uint8_t                                        l_is_mpipl = 0x0;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
     auto l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_is_mpipl));
+
+    if(l_is_mpipl)
+    {
+        // PB_PURGE related SCOMs should be added to the beginning of
+        // p9_hcd_cache_stopclocks, these scoms should only be done if the clock
+        // region including PBIEQ clock domain is being stopped, which
+        // incidentally should always be the case for MPIPL
+        l_data64.flush<0>();
+        l_data64.setBit<30>();
+        // Set bit 30 in EQ_QPPM_QCCR_SCOM2(100F01BF) Reg, Pulse to the
+        // Powerbus logic in the Cache clock domain to request them to purge
+        // their async buffers in preparation to power off the Quad
+        FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM2, l_data64));
+
+        l_data64.flush<0>();
+        uint32_t l_timeout = PB_PURGE_CACHE_STOP_POLLING_TIMEOUT;
+
+        do
+        {
+            // Acknowledgement from Powerbus that the buffers are empty
+            // and can safely be fenced & clocked off.
+            FAPI_TRY(fapi2::getScom(i_target, EQ_QPPM_QCCR_SCOM, l_data64));
+            bool l_poll_data = l_data64.getBit<31>();
+
+            if(l_poll_data == 1)
+            {
+                break;
+            }
+
+            FAPI_TRY(fapi2::delay(PB_PURGE_CACHE_STOP_POLLING_DELAY_HW_MILLISEC,
+                                  PB_PURGE_CACHE_STOP_POLLING_DELAY_SIM_CYCLES),
+                     "Error from delay"); //1msec delay
+        }
+        while(--l_timeout != 0);
+
+        // Error if Timeout happens
+        FAPI_ASSERT((l_timeout != 0),
+                    fapi2::QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT()
+                    .set_TARGET(i_target)
+                    .set_EQPPMQCCR(l_data64),
+                    "QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit 31 not set.");
+
+        l_data64.flush<0>();
+        l_data64.setBit<30>();
+        FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM1, l_data64));
+    }
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,    l_sys,
                            l_attr_vdm_enable));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
@@ -99,7 +151,6 @@ p9_hcd_cache_stopclocks(
     // -----------------------------
     // Prepare to stop cache clocks
     // -----------------------------
-
     FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]");
     FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64));
 
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml
index 7dd58c2f7..ea3071552 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml
@@ -49,4 +49,15 @@
     <ffdc>EQCPLTSTAT</ffdc>
   </hwpError>
   <!-- ********************************************************************* -->
+  <hwpError>
+    <rc>RC_QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT</rc>
+    <description>
+    A timeout occured while waiting for Acknowledgement from 
+    Powerbus that the buffers are empty and can safely be
+    fenced and clocked off
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>EQPPMQCCR</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
 </hwpErrors>