Fixes FFDC for files moved to generic

Change-Id: Ibd639646548cfe0745127419c151a67635e8ae75
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77343
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77422
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 13 insertions, 10 deletions

diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
index 12821c76f..1ebd48115 100644
--- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
+++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H
@@ -493,7 +493,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                     right_aligned_insert(l_buffer, l_twrmin_msn, l_twrmin_lsb);
 
                     // Update output only after check passes
-                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWRMIN));
+                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, U, TWRMIN));
                     o_value = l_buffer;
 
                     FAPI_INF("%s. Minimum Write Recovery Time (tWRmin) in MTB units: %d",
@@ -526,7 +526,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                     right_aligned_insert(l_buffer, l_twtr_lmin_msn, l_twtr_lmin_lsb);
 
                     // Update output only after check passes
-                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWTR_L_MIN));
+                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, U, TWTR_L_MIN));
                     o_value = l_buffer;
 
                     FAPI_INF("%s. Minimum Write to Read Time - Different Bank Group (tWTR_Lmin) in MTB units: %d",
@@ -560,7 +560,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                     right_aligned_insert(l_buffer, l_twtr_smin_msn, l_twtr_smin_lsb);
 
                     // Update output only after check passes
-                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, TWTR_S_MIN));
+                    FAPI_TRY( check::max_timing_range<BITS12>(i_target, l_buffer, U, TWTR_S_MIN));
                     o_value = l_buffer;
 
                     FAPI_INF("%s. Minimum Write to Read Time - Different Bank Group (tWTR_Smin) in MTB units: %d",
@@ -1275,7 +1275,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_tRASmin_msn, l_tRASmin_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TRASMIN));
+                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, R, TRASMIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Active to Precharge Delay Time (tRASmin) in MTB units: %d",
@@ -1305,7 +1305,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_trcmin_msn, l_trcmin_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TRCMIN));
+                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, R, TRCMIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Active to Active/Refresh Delay Time (tRCmin) in MTB units: %d",
@@ -1336,7 +1336,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_trfc1min_msb, l_trfc1min_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC1MIN));
+                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, R, TRFC1MIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Refresh Recovery Delay Time 1 (tRFC1min) in MTB units: %d",
@@ -1366,7 +1366,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_trfc2min_msb, l_trfc2min_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC2MIN));
+                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, R, TRFC2MIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Refresh Recovery Delay Time 2 (tRFC2min) in MTB units: %d",
@@ -1396,7 +1396,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_trfc4min_msb, l_trfc4min_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, TRFC4MIN));
+                FAPI_TRY( check::max_timing_range<BITS16>(iv_target, l_buffer, R, TRFC4MIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Refresh Recovery Delay Time 4 (tRFC4min) in MTB units: %d",
@@ -1426,7 +1426,7 @@ class decoder<DDR4, BASE_CNFG, R> : public base_cnfg_decoder
                 right_aligned_insert(l_buffer, l_tfawmin_msn, l_tfawmin_lsb);
 
                 // Update output only after check passes
-                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, TFAWMIN));
+                FAPI_TRY( check::max_timing_range<BITS12>(iv_target, l_buffer, R, TFAWMIN));
                 o_value = l_buffer;
 
                 FAPI_INF("%s. Minimum Four Activate Window Delay Time (tFAWmin) in MTB units: %d",
diff --git a/src/import/generic/memory/lib/spd/spd_checker.H b/src/import/generic/memory/lib/spd/spd_checker.H
index 0b2a33076..50e6ef347 100644
--- a/src/import/generic/memory/lib/spd/spd_checker.H
+++ b/src/import/generic/memory/lib/spd/spd_checker.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* Contributors Listed Below - COPYRIGHT 2017,2019                        */
 /* [+] Evan Lojewski                                                      */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -103,17 +103,20 @@ namespace check
 /// @tparam TT defaulted to bitRangeTraits<TB>
 /// @param[in] i_target fapi2 target
 /// @param[in] i_timing the timing value
+/// @param[in] i_rev the SPD revision that needs to be checked
 /// @param[in] i_ffdc ffdc function code
 /// @return FAPI2_RC_SUCCESS iff okay
 ///
 template < bit_len BL, fapi2::TargetType T, typename TT = bitRangeTraits<BL> >
 fapi2::ReturnCode max_timing_range(const fapi2::Target<T>& i_target,
                                    const int64_t i_timing,
+                                   const rev i_rev,
                                    const generic_ffdc_codes i_ffdc)
 {
     FAPI_ASSERT( (i_timing <= TT::UPPER_BOUND) &&
                  (i_timing >= TT::LOWER_BOUND),
                  fapi2::MSS_SPD_TIMING_FAIL()
+                 .set_FAILED_REVISION(i_rev)
                  .set_FUNCTION_CODE(i_ffdc)
                  .set_TARGET(i_target),
                  "Failed timing parameter check for %s",