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| author | Claus Michael Olsen <cmolsen@us.ibm.com> | 2018-05-14 17:51:09 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-10-14 13:05:32 -0500 |
| commit | 52b76be222254e59959db984606c09dae854270b (patch) | |
| tree | a009b9fbeca0437d3552844bfd55f64147d4a0e1 /src/import/chips/p9/utils/imageProcs | |
| parent | 62feee748b72ef5f7cb1032964dab2b0686cd916 (diff) | |
| download | blackbird-hostboot-52b76be222254e59959db984606c09dae854270b.tar.gz blackbird-hostboot-52b76be222254e59959db984606c09dae854270b.zip | |
P10 prep: Infrastructure (IS) ring Id metadata and API changes
Gerrit intent:
- Applicable for P9 merge (co-req NOT required)
- Co-req not req'd for any tests
Includes the following changes:
- Accommodates initCompiler's needs for additional ring Id APIs to
retrieve IS's key ring identifiers, ringId and ringClass, and to
align with our enumerated chipId
- Elimination of redundancy in and reorg of IS's ring Id lists:
RingProperties, GenRingIdList (gone) and ChipletData.
- GenRingIdList has been removed.
- Expand RingProperties to also include scanScomAddr and ringClass.
- Member of ring and chiplet properties structs have been renamed in
consistent camel style (no longer using "iv_" anywhere).
- Note that with "infrastructure (IS)" we here mean the core infrastructure
codes that directly interact with and affect the image.
Key_Cronus_Test=XIP_REGRESS
Change-Id: I7e92af04edd10c0994718e476f6e7b77c5d124d6
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59087
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/utils/imageProcs')
| -rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H | 23 | ||||
| -rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_ringId.C | 594 | ||||
| -rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_ringId.H | 1286 | ||||
| -rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_tor.C | 445 | ||||
| -rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_tor.H | 5 |
5 files changed, 870 insertions, 1483 deletions
diff --git a/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H b/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H index 736f6025b..b644996e3 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H +++ b/src/import/chips/p9/utils/imageProcs/p9_infrastruct_help.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -52,30 +52,9 @@ const uint32_t MAX_HBBL_SIZE = 20 * 1024; // Max hbbl section siz const uint32_t MAX_NOOF_DD_LEVELS_IN_IMAGE = 20; -//@FIXME: CMO: Aren't these defined somewhere else? -#define NUM_OF_CORES (uint8_t)24 -#define NUM_OF_CMES (uint8_t)12 -#define NUM_OF_QUADS (uint8_t) 6 -#define CORES_PER_QUAD (NUM_OF_CORES/NUM_OF_QUADS) - #define INSTANCE_ID_MIN (uint8_t)0x01 #define INSTANCE_ID_MAX (uint8_t)0x37 -enum SYSPHASE -{ - SYSPHASE_HB_SBE = 0, - SYSPHASE_RT_CME = 1, - SYSPHASE_RT_SGPE = 2, - NOOF_SYSPHASES = 3, -}; - -enum MODEBUILD -{ - MODEBUILD_IPL = 0, - MODEBUILD_REBUILD = 1, - NOOF_MODEBUILDS = 2, -}; - #if defined(__FAPI) #include <fapi2.H> #define MY_INF(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_) diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C index 3d188e340..fb81d8c67 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C @@ -28,642 +28,84 @@ namespace P9_RID { - #include "p9_ringId.H" - - -namespace PERV -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"perv_fure" , 0x00, 0x01, 0x01, EKB_RING , 0x0103400F}, - {"perv_gptr" , 0x01, 0x01, 0x01, EKB_RING , 0x01034002}, - {"perv_time" , 0x02, 0x01, 0x01, VPD_RING , 0x01034007}, - {"occ_fure" , 0x03, 0x01, 0x01, EKB_RING , 0x0103080F}, - {"occ_gptr" , 0x04, 0x01, 0x01, EKB_RING , 0x01030802}, - {"occ_time" , 0x05, 0x01, 0x01, VPD_RING , 0x01030807}, - {"perv_ana_func" , 0x06, 0x01, 0x01, EKB_RING , 0x01030400}, - {"perv_ana_gptr" , 0x07, 0x01, 0x01, EKB_RING , 0x01030402}, - {"perv_pll_gptr" , 0x08, 0x01, 0x01, EKB_RING , 0x01030012}, - {"perv_pll_bndy_bucket_1", 0x09, 0x01, 0x01, EKB_RING , 0x01030018}, - {"perv_pll_bndy_bucket_2", 0x0a, 0x01, 0x01, EKB_RING , 0x01030018}, - {"perv_pll_bndy_bucket_3", 0x0b, 0x01, 0x01, EKB_RING , 0x01030018}, - {"perv_pll_bndy_bucket_4", 0x0c, 0x01, 0x01, EKB_RING , 0x01030018}, - {"perv_pll_bndy_bucket_5", 0x0d, 0x01, 0x01, EKB_RING , 0x01030018}, - {"perv_pll_func" , 0x0e, 0x01, 0x01, EKB_RING , 0x01030010}, - {"perv_pll_bndy_flt_1" , 0x0f, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, - {"perv_pll_bndy_flt_2" , 0x10, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, - {"perv_pll_bndy_flt_3" , 0x11, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, - {"perv_pll_bndy_flt_4" , 0x12, 0x01, 0x01, EKB_NONFLUSH_RING, 0x01030018}, - {"sbe_fure" , 0x13, 0x01, 0x01, EKB_RING , 0x0103020F}, - {"sbe_gptr" , 0x14, 0x01, 0x01, EKB_RING , 0x01030202}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"perv_repr" , 0x15, 0x01, 0x01, VPD_RING , 0x01034006}, - {"occ_repr" , 0x16, 0x01, 0x01, VPD_RING , 0x01030806}, - {"sbe_repr" , 0x17, 0x01, 0x01, VPD_RING , 0x01030206}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; }; -namespace N0 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"n0_fure" , 0x00, 0x02, 0x02, EKB_RING , 0x02034E0F}, - {"n0_gptr" , 0x01, 0x02, 0x02, EKB_RING , 0x02034E02}, - {"n0_time" , 0x02, 0x02, 0x02, VPD_RING , 0x02034E07}, - {"n0_nx_fure" , 0x03, 0x02, 0x02, EKB_RING , 0x0203200F}, - {"n0_nx_gptr" , 0x04, 0x02, 0x02, EKB_RING , 0x02032002}, - {"n0_nx_time" , 0x05, 0x02, 0x02, VPD_RING , 0x02032007}, - {"n0_cxa0_fure" , 0x06, 0x02, 0x02, EKB_RING , 0x0203100F}, - {"n0_cxa0_gptr" , 0x07, 0x02, 0x02, EKB_RING , 0x02031002}, - {"n0_cxa0_time" , 0x08, 0x02, 0x02, VPD_RING , 0x02031007}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"n0_repr" , 0x09, 0x02, 0x02, VPD_RING , 0x02034E06}, - {"n0_nx_repr" , 0x0a, 0x02, 0x02, VPD_RING , 0x02032006}, - {"n0_cxa0_repr" , 0x0b, 0x02, 0x02, VPD_RING , 0x02031006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace N1 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"n1_fure" , 0x00, 0x03, 0x03, EKB_RING , 0x0303700F}, - {"n1_gptr" , 0x01, 0x03, 0x03, EKB_RING , 0x03037002}, - {"n1_time" , 0x02, 0x03, 0x03, VPD_RING , 0x03037007}, - {"n1_ioo0_fure" , 0x03, 0x03, 0x03, EKB_RING , 0x0303080F}, - {"n1_ioo0_gptr" , 0x04, 0x03, 0x03, EKB_RING , 0x03030802}, - {"n1_ioo0_time" , 0x05, 0x03, 0x03, VPD_RING , 0x03030807}, - {"n1_ioo1_fure" , 0x06, 0x03, 0x03, EKB_RING , 0x0303040F}, - {"n1_ioo1_gptr" , 0x07, 0x03, 0x03, EKB_RING , 0x03030402}, - {"n1_ioo1_time" , 0x08, 0x03, 0x03, VPD_RING , 0x03030407}, - {"n1_mcs23_fure" , 0x09, 0x03, 0x03, EKB_RING , 0x0303020F}, - {"n1_mcs23_gptr" , 0x0a, 0x03, 0x03, EKB_RING , 0x03030202}, - {"n1_mcs23_time" , 0x0b, 0x03, 0x03, VPD_RING , 0x03030207}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"n1_repr" , 0x0c, 0x03, 0x03, VPD_RING , 0x03037006}, - {"n1_ioo0_repr" , 0x0d, 0x03, 0x03, VPD_RING , 0x03030806}, - {"n1_ioo1_repr" , 0x0e, 0x03, 0x03, VPD_RING , 0x03030406}, - {"n1_mcs23_repr" , 0x0f, 0x03, 0x03, VPD_RING , 0x03030206}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace N2 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"n2_fure" , 0x00, 0x04, 0x04, EKB_RING , 0x04035C0F}, - {"n2_gptr" , 0x01, 0x04, 0x04, EKB_RING , 0x04035C02}, - {"n2_time" , 0x02, 0x04, 0x04, VPD_RING , 0x04035C07}, - {"n2_cxa1_fure" , 0x03, 0x04, 0x04, EKB_RING , 0x0403200F}, - {"n2_cxa1_gptr" , 0x04, 0x04, 0x04, EKB_RING , 0x04032002}, - {"n2_cxa1_time" , 0x05, 0x04, 0x04, VPD_RING , 0x04032007}, - {"n2_psi_fure" , 0x06, 0x04, 0x04, EKB_RING , 0x0403020F}, - {"n2_psi_gptr" , 0x07, 0x04, 0x04, EKB_RING , 0x04030202}, - {"n2_psi_time" , 0x08, 0x04, 0x04, VPD_RING , 0x04030207}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"n2_repr" , 0x09, 0x04, 0x04, VPD_RING , 0x04035C06}, - {"n2_cxa1_repr" , 0x0a, 0x04, 0x04, VPD_RING , 0x04032006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace N3 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"n3_fure" , 0x00, 0x05, 0x05, EKB_RING , 0x0503660F}, - {"n3_gptr" , 0x01, 0x05, 0x05, EKB_RING , 0x05037602}, - {"n3_time" , 0x02, 0x05, 0x05, VPD_RING , 0x05037607}, - {"n3_mcs01_fure" , 0x03, 0x05, 0x05, EKB_RING , 0x0503010F}, - {"n3_mcs01_gptr" , 0x04, 0x05, 0x05, EKB_RING , 0x05030102}, - {"n3_mcs01_time" , 0x05, 0x05, 0x05, VPD_RING , 0x05030107}, - {"n3_np_fure" , 0x06, 0x05, 0x05, EKB_RING , 0x0503080F}, - {"n3_np_gptr" , 0x07, 0x05, 0x05, EKB_RING , 0x05030802}, - {"n3_np_time" , 0x08, 0x05, 0x05, VPD_RING , 0x05030807}, - {"n3_br_fure" , 0x09, 0x05, 0x05, EKB_RING , 0x0503100F}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"n3_repr" , 0x0a, 0x05, 0x05, VPD_RING , 0x05037606}, - {"n3_mcs01_repr" , 0x0b, 0x05, 0x05, VPD_RING , 0x05030106}, - {"n3_np_repr" , 0x0c, 0x05, 0x05, VPD_RING , 0x05030806}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace XB -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"xb_fure" , 0x00, 0x06, 0x06, EKB_RING , 0x0603440F}, - {"xb_gptr" , 0x01, 0x06, 0x06, EKB_RING , 0x06034402}, - {"xb_time" , 0x02, 0x06, 0x06, VPD_RING , 0x06034407}, - {"xb_io0_fure" , 0x03, 0x06, 0x06, EKB_RING , 0x0603220F}, - {"xb_io0_gptr" , 0x04, 0x06, 0x06, EKB_RING , 0x06032202}, - {"xb_io0_time" , 0x05, 0x06, 0x06, VPD_RING , 0x06032207}, - {"xb_io1_fure" , 0x06, 0x06, 0x06, EKB_RING , 0x0603110F}, - {"xb_io1_gptr" , 0x07, 0x06, 0x06, EKB_RING , 0x06031102}, - {"xb_io1_time" , 0x08, 0x06, 0x06, VPD_RING , 0x06031107}, - {"xb_io2_fure" , 0x09, 0x06, 0x06, EKB_RING , 0x0603088F}, - {"xb_io2_gptr" , 0x0a, 0x06, 0x06, EKB_RING , 0x06030882}, - {"xb_io2_time" , 0x0b, 0x06, 0x06, VPD_RING , 0x06030887}, - {"xb_pll_gptr" , 0x0c, 0x06, 0x06, EKB_RING , 0x06030012}, - {"xb_pll_bndy" , 0x0d, 0x06, 0x06, EKB_RING , 0x06030018}, - {"xb_pll_func" , 0x0e, 0x06, 0x06, EKB_RING , 0x06030010}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"xb_repr" , 0x13, 0x06, 0x06, VPD_RING , 0x06034406}, - {"xb_io0_repr" , 0x14, 0x06, 0x06, VPD_RING , 0x06032206}, - {"xb_io1_repr" , 0x15, 0x06, 0x06, VPD_RING , 0x06031106}, - {"xb_io2_repr" , 0x16, 0x06, 0x06, VPD_RING , 0x06030886}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace MC -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"mc_fure" , 0x00, 0x07, 0x07, EKB_RING , 0x0703600F}, - {"mc_gptr" , 0x01, 0x07, 0x07, EKB_RING , 0x07036002}, - {"mc_time" , 0x02, 0x07, 0x07, VPD_RING , 0x07036007}, - {"mc_iom01_fure" , 0x03, 0x07, 0x07, EKB_RING , 0x0703100F}, - {"mc_iom01_gptr" , 0x04, 0x07, 0x07, EKB_RING , 0x07031002}, - {"mc_iom01_time" , 0x05, 0x07, 0x07, VPD_RING , 0x07031007}, - {"mc_iom23_fure" , 0x06, 0x07, 0x07, EKB_RING , 0x0703080F}, - {"mc_iom23_gptr" , 0x07, 0x07, 0x07, EKB_RING , 0x07030802}, - {"mc_iom23_time" , 0x08, 0x07, 0x07, VPD_RING , 0x07030807}, - {"mc_pll_gptr" , 0x09, 0x07, 0x07, EKB_RING , 0x07030012}, - {"mc_pll_bndy_bucket_1", 0x0a, 0x07, 0x07, EKB_RING , 0x07030018}, - {"mc_pll_bndy_bucket_2", 0x0b, 0x07, 0x07, EKB_RING , 0x07030018}, - {"mc_pll_bndy_bucket_3", 0x0c, 0x07, 0x07, EKB_RING , 0x07030018}, - {"mc_pll_bndy_bucket_4", 0x0d, 0x07, 0x07, EKB_RING , 0x07030018}, - {"mc_pll_bndy_bucket_5", 0x0e, 0x07, 0x07, EKB_RING , 0x07030018}, - {"mc_pll_func" , 0x0f, 0x07, 0x07, EKB_RING , 0x07030010}, - {"mc_omi0_fure" , 0x10, 0x07, 0x08, EKB_RING , 0x0703100F}, - {"mc_omi0_gptr" , 0x11, 0x07, 0x07, EKB_RING , 0x07031002}, - {"mc_omi1_fure" , 0x12, 0x07, 0x07, EKB_RING , 0x0703080F}, - {"mc_omi1_gptr" , 0x13, 0x07, 0x07, EKB_RING , 0x07030802}, - {"mc_omi2_fure" , 0x14, 0x07, 0x07, EKB_RING , 0x0703040F}, - {"mc_omi2_gptr" , 0x15, 0x07, 0x07, EKB_RING , 0x07030402}, - {"mc_omippe_fure" , 0x16, 0x07, 0x07, EKB_RING , 0x0703020F}, - {"mc_omippe_gptr" , 0x17, 0x07, 0x07, EKB_RING , 0x07030202}, - {"mc_omippe_time" , 0x18, 0x07, 0x07, VPD_RING , 0x07030207}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"mc_repr" , 0x19, 0x07, 0x08, VPD_RING , 0x07036006}, - {"mc_iom23_repr" , 0x1a, 0x07, 0x08, VPD_RING , 0x07030806}, - {"mc_omippe_repr" , 0x1b, 0x07, 0x08, VPD_RING , 0x07030206}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace OB0 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"ob0_pll_bndy_bucket_1" , 0x00, 0x09, 0x09, EKB_RING , 0x09030018}, - {"ob0_pll_bndy_bucket_2" , 0x01, 0x09, 0x09, EKB_RING , 0x09030018}, - {"ob0_gptr" , 0x02, 0x09, 0x09, EKB_RING , 0x09037002}, - {"ob0_time" , 0x03, 0x09, 0x09, VPD_RING , 0x09037007}, - {"ob0_pll_gptr" , 0x04, 0x09, 0x09, EKB_RING , 0x09030012}, - {"ob0_fure" , 0x05, 0x09, 0x09, EKB_RING , 0x0903700F}, - {"ob0_pll_bndy_bucket_3" , 0x06, 0x09, 0x09, EKB_RING , 0x09030018}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"ob0_repr" , 0x07, 0x09, 0x09, VPD_RING , 0x09037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace OB1 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"ob1_pll_bndy_bucket_1" , 0x00, 0x0a, 0x0a, EKB_RING , 0x0A030018}, - {"ob1_pll_bndy_bucket_2" , 0x01, 0x0a, 0x0a, EKB_RING , 0x0A030018}, - {"ob1_gptr" , 0x02, 0x0a, 0x0a, EKB_RING , 0x0A037002}, - {"ob1_time" , 0x03, 0x0a, 0x0a, VPD_RING , 0x0A037007}, - {"ob1_pll_gptr" , 0x04, 0x0a, 0x0a, EKB_RING , 0x0A030012}, - {"ob1_fure" , 0x05, 0x0a, 0x0a, EKB_RING , 0x0A03700F}, - {"ob1_pll_bndy_bucket_3" , 0x06, 0x0a, 0x0a, EKB_RING , 0x0A030018}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"ob1_repr" , 0x07, 0x0a, 0x0a, VPD_RING , 0x0A037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace OB2 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"ob2_pll_bndy_bucket_1" , 0x00, 0x0b, 0x0b, EKB_RING , 0x0B030018}, - {"ob2_pll_bndy_bucket_2" , 0x01, 0x0b, 0x0b, EKB_RING , 0x0B030018}, - {"ob2_gptr" , 0x02, 0x0b, 0x0b, EKB_RING , 0x0B037002}, - {"ob2_time" , 0x03, 0x0b, 0x0b, VPD_RING , 0x0B037007}, - {"ob2_pll_gptr" , 0x04, 0x0b, 0x0b, EKB_RING , 0x0B030012}, - {"ob2_fure" , 0x05, 0x0b, 0x0b, EKB_RING , 0x0B03700F}, - {"ob2_pll_bndy_bucket_3" , 0x06, 0x0b, 0x0b, EKB_RING , 0x0B030018}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"ob2_repr" , 0x07, 0x0b, 0x0b, VPD_RING , 0x0B037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace OB3 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"ob3_pll_bndy_bucket_1" , 0x00, 0x0c, 0x0c, EKB_RING , 0x0C030018}, - {"ob3_pll_bndy_bucket_2" , 0x01, 0x0c, 0x0c, EKB_RING , 0x0C030018}, - {"ob3_gptr" , 0x02, 0x0c, 0x0c, EKB_RING , 0x0C037002}, - {"ob3_time" , 0x03, 0x0c, 0x0c, VPD_RING , 0x0C037007}, - {"ob3_pll_gptr" , 0x04, 0x0c, 0x0c, EKB_RING , 0x0C030012}, - {"ob3_fure" , 0x05, 0x0c, 0x0c, EKB_RING , 0x0C03700F}, - {"ob3_pll_bndy_bucket_3" , 0x06, 0x0c, 0x0c, EKB_RING , 0x0C030018}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"ob3_repr" , 0x07, 0x0c, 0x0c, VPD_RING , 0x0C037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace PCI0 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"pci0_fure" , 0x00, 0x0d, 0x0d, EKB_RING , 0x0D03700F}, - {"pci0_gptr" , 0x01, 0x0d, 0x0d, EKB_RING , 0x0D037002}, - {"pci0_time" , 0x02, 0x0d, 0x0d, VPD_RING , 0x0D037007}, - {"pci0_pll_bndy" , 0x03, 0x0d, 0x0d, EKB_RING , 0x0D030018}, - {"pci0_pll_gptr" , 0x04, 0x0d, 0x0d, EKB_RING , 0x0D030012}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"pci0_repr" , 0x05, 0x0d, 0x0d, VPD_RING , 0x0D037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace PCI1 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"pci1_fure" , 0x00, 0x0e, 0x0e, EKB_RING , 0x0E03780F}, - {"pci1_gptr" , 0x01, 0x0e, 0x0e, EKB_RING , 0x0E037802}, - {"pci1_time" , 0x02, 0x0e, 0x0e, VPD_RING , 0x0E037807}, - {"pci1_pll_bndy" , 0x03, 0x0e, 0x0e, EKB_RING , 0x0E030018}, - {"pci1_pll_gptr" , 0x04, 0x0e, 0x0e, EKB_RING , 0x0E030012}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"pci1_repr" , 0x05, 0x0e, 0x0e, VPD_RING , 0x0E037806}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace PCI2 -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"pci2_fure" , 0x00, 0x0f, 0x0f, EKB_RING , 0x0F037C0F}, - {"pci2_gptr" , 0x01, 0x0f, 0x0f, EKB_RING , 0x0F037C02}, - {"pci2_time" , 0x02, 0x0f, 0x0f, VPD_RING , 0x0F037C07}, - {"pci2_pll_bndy" , 0x03, 0x0f, 0x0f, EKB_RING , 0x0F030018}, - {"pci2_pll_gptr" , 0x04, 0x0f, 0x0f, EKB_RING , 0x0F030012}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"pci2_repr" , 0x05, 0x0F, 0x0F, VPD_RING , 0x0F037C06}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT }; -}; - - -namespace EQ -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - {"eq_fure" , 0x00, 0x10, 0x10, EKB_RING , 0x1003608F}, - {"eq_gptr" , 0x01, 0x10, 0x10, EKB_RING , 0x10036082}, - {"eq_time" , 0x02, 0x10, 0x10, VPD_RING , 0x10036087}, - {"eq_inex" , 0x03, 0x10, 0x10, EKB_RING , 0x1003608B}, - {"ex_l3_fure" , 0x04, 0x10, 0x10, EKB_RING , 0x1003100F}, - {"ex_l3_gptr" , 0x05, 0x10, 0x10, EKB_RING , 0x10031002}, - {"ex_l3_time" , 0x06, 0x10, 0x10, VPD_RING , 0x10031007}, - {"ex_l2_mode" , 0x07, 0x10, 0x10, EKB_RING , 0x10030401}, - {"ex_l2_fure" , 0x08, 0x10, 0x10, EKB_RING , 0x1003040F}, - {"ex_l2_gptr" , 0x09, 0x10, 0x10, EKB_RING , 0x10030402}, - {"ex_l2_time" , 0x0a, 0x10, 0x10, VPD_RING , 0x10030407}, - {"ex_l3_refr_fure" , 0x0b, 0x10, 0x10, EKB_RING , 0x1003004F}, - {"ex_l3_refr_gptr" , 0x0c, 0x10, 0x10, EKB_RING , 0x10030042}, - {"eq_ana_func" , 0x0d, 0x10, 0x10, EKB_RING , 0x10030100}, - {"eq_ana_gptr" , 0x0e, 0x10, 0x10, EKB_RING , 0x10030102}, - {"eq_dpll_func" , 0x0f, 0x10, 0x10, EKB_RING , 0x10030010}, - {"eq_dpll_gptr" , 0x10, 0x10, 0x10, EKB_RING , 0x10030012}, - {"eq_dpll_mode" , 0x11, 0x10, 0x10, EKB_RING , 0x10030011}, - {"eq_ana_bndy_bucket_0" , 0x12, 0x10, 0x10, EKB_RING , 0x10030108}, - {"eq_ana_bndy_bucket_1" , 0x13, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_2" , 0x14, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_3" , 0x15, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_4" , 0x16, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_5" , 0x17, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_6" , 0x18, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_7" , 0x19, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_8" , 0x1a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_9" , 0x1b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_10" , 0x1c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_11" , 0x1d, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_12" , 0x1e, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_13" , 0x1f, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_14" , 0x20, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_15" , 0x21, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_16" , 0x22, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_17" , 0x23, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_18" , 0x24, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_19" , 0x25, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_20" , 0x26, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_21" , 0x27, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_22" , 0x28, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_23" , 0x29, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_24" , 0x2a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_25" , 0x2b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_l3dcc" , 0x2c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_mode" , 0x2d, 0x10, 0x10, EKB_RING , 0x10030101}, - {"eq_ana_bndy_bucket_26" , 0x2e, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_27" , 0x2f, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_28" , 0x30, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_29" , 0x31, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_30" , 0x32, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_31" , 0x33, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_32" , 0x34, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_33" , 0x35, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_34" , 0x36, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_35" , 0x37, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_36" , 0x38, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_37" , 0x39, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_38" , 0x3a, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_39" , 0x3b, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_40" , 0x3c, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_ana_bndy_bucket_41" , 0x3d, 0x10, 0x10, EKB_FSM_RING, 0x10030108}, - {"eq_inex_bucket_1" , 0x3e, 0x10, 0x10, EKB_RING , 0x1003608B}, - {"eq_inex_bucket_2" , 0x3f, 0x10, 0x10, EKB_RING , 0x1003608B}, - {"eq_inex_bucket_3" , 0x40, 0x10, 0x10, EKB_RING , 0x1003608B}, - {"eq_inex_bucket_4" , 0x41, 0x10, 0x10, EKB_RING , 0x1003608B}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - {"eq_repr" , 0x42, 0x10, 0x1b, VPD_RING , 0x10036086}, - {"ex_l3_repr" , 0x43, 0x10, 0x1b, VPD_RING , 0x10031006}, - {"ex_l2_repr" , 0x44, 0x10, 0x1b, VPD_RING , 0x10030406}, - {"ex_l3_refr_repr" , 0x45, 0x10, 0x1b, VPD_RING , 0x10030046}, - {"ex_l3_refr_time" , 0x46, 0x10, 0x1b, VPD_RING , 0x10030047}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 }; -}; - - -namespace EC -{ -const GenRingIdList RING_ID_LIST_COMMON[] = -{ - { "ec_func" , 0x00, 0x20, 0x20, EKB_STUMPED_RING , 0x2003700F}, - { "ec_gptr" , 0x01, 0x20, 0x20, EKB_RING , 0x20037002}, - { "ec_time" , 0x02, 0x20, 0x20, VPD_RING , 0x20037007}, - { "ec_mode" , 0x03, 0x20, 0x20, EKB_RING , 0x20037001}, - { "ec_abst" , 0x04, 0x20, 0x20, EKB_RING , 0x20037005}, - { "ec_cmsk" , 0xFF, 0xFF, 0xFF, EKB_CMSK_RING , 0x2003700A}, -}; -const GenRingIdList RING_ID_LIST_INSTANCE[] = -{ - { "ec_repr" , 0x05, 0x20, 0x37, VPD_RING , 0x20037006}, -}; -const RingVariantOrder RING_VARIANT_ORDER[] = { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 }; -}; - - -}; // namespace P9_RID - - using namespace P9_RID; -ChipletType_t P9_RID::ringid_get_chiplet(RingId_t i_ringId) -{ - return RING_PROPERTIES[i_ringId].iv_type; -} - void P9_RID::ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_cpltData, - GenRingIdList** o_ringComm, - GenRingIdList** o_ringInst, - RingVariantOrder** o_varOrder, - uint8_t* o_numVariants) + ChipletData_t** o_chipletData) { switch (i_chipletType) { case PERV_TYPE : - *o_cpltData = (ChipletData_t*) &PERV::g_chipletData; - *o_ringComm = (GenRingIdList*) PERV::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) PERV::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) PERV::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&PERV::g_chipletData; break; case N0_TYPE : - *o_cpltData = (ChipletData_t*) &N0::g_chipletData; - *o_ringComm = (GenRingIdList*) N0::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) N0::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) N0::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&N0::g_chipletData; break; case N1_TYPE : - *o_cpltData = (ChipletData_t*) &N1::g_chipletData; - *o_ringComm = (GenRingIdList*) N1::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) N1::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) N1::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&N1::g_chipletData; break; case N2_TYPE : - *o_cpltData = (ChipletData_t*) &N2::g_chipletData; - *o_ringComm = (GenRingIdList*) N2::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) N2::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) N2::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&N2::g_chipletData; break; case N3_TYPE : - *o_cpltData = (ChipletData_t*) &N3::g_chipletData; - *o_ringComm = (GenRingIdList*) N3::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) N3::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) N3::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&N3::g_chipletData; break; case XB_TYPE : - *o_cpltData = (ChipletData_t*) &XB::g_chipletData; - *o_ringComm = (GenRingIdList*) XB::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) XB::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) XB::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&XB::g_chipletData; break; case MC_TYPE : - *o_cpltData = (ChipletData_t*) &MC::g_chipletData; - *o_ringComm = (GenRingIdList*) MC::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) MC::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) MC::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&MC::g_chipletData; break; case OB0_TYPE : - *o_cpltData = (ChipletData_t*) &OB0::g_chipletData; - *o_ringComm = (GenRingIdList*) OB0::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) OB0::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) OB0::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&OB0::g_chipletData; break; case OB1_TYPE : - *o_cpltData = (ChipletData_t*) &OB1::g_chipletData; - *o_ringComm = (GenRingIdList*) OB1::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) OB1::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) OB1::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&OB1::g_chipletData; break; case OB2_TYPE : - *o_cpltData = (ChipletData_t*) &OB2::g_chipletData; - *o_ringComm = (GenRingIdList*) OB2::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) OB2::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) OB2::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&OB2::g_chipletData; break; case OB3_TYPE : - *o_cpltData = (ChipletData_t*) &OB3::g_chipletData; - *o_ringComm = (GenRingIdList*) OB3::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) OB3::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) OB3::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&OB3::g_chipletData; break; case PCI0_TYPE : - *o_cpltData = (ChipletData_t*) &PCI0::g_chipletData; - *o_ringComm = (GenRingIdList*) PCI0::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) PCI0::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) PCI0::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&PCI0::g_chipletData; break; case PCI1_TYPE : - *o_cpltData = (ChipletData_t*) &PCI1::g_chipletData; - *o_ringComm = (GenRingIdList*) PCI1::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) PCI1::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) PCI1::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&PCI1::g_chipletData; break; case PCI2_TYPE : - *o_cpltData = (ChipletData_t*) &PCI2::g_chipletData; - *o_ringComm = (GenRingIdList*) PCI2::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) PCI2::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) PCI2::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&PCI2::g_chipletData; break; case EQ_TYPE : - *o_cpltData = (ChipletData_t*) &EQ::g_chipletData; - *o_ringComm = (GenRingIdList*) EQ::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) EQ::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) EQ::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&EQ::g_chipletData; break; case EC_TYPE : - *o_cpltData = (ChipletData_t*) &EC::g_chipletData; - *o_ringComm = (GenRingIdList*) EC::RING_ID_LIST_COMMON; - *o_ringInst = (GenRingIdList*) EC::RING_ID_LIST_INSTANCE; - *o_varOrder = (RingVariantOrder*) EC::RING_VARIANT_ORDER; - *o_numVariants = (*(*o_cpltData)).iv_num_common_ring_variants; + *o_chipletData = (ChipletData_t*)&EC::g_chipletData; break; default : - *o_cpltData = NULL; - *o_ringComm = NULL; - *o_ringInst = NULL; - *o_varOrder = NULL; - *o_numVariants = 0; + *o_chipletData = NULL; break; } } - -GenRingIdList* P9_RID::_ringid_get_ring_list(RingId_t i_ringId) -{ - ChipletData_t* l_cpltData; - GenRingIdList* l_ringList[2]; // 0: common, 1: instance - RingVariantOrder* l_varOrder; - uint8_t l_numVariants; - int i, j, n; - - P9_RID::ringid_get_chiplet_properties( - P9_RID::ringid_get_chiplet(i_ringId), - &l_cpltData, &l_ringList[0], &l_ringList[1], &l_varOrder, &l_numVariants); - - if (!l_ringList[0]) - { - return NULL; - } - - for (j = 0; j < 2; j++) // 0: common, 1: instance - { - n = (j ? l_cpltData->iv_num_instance_rings - : l_cpltData->iv_num_common_rings); - - for (i = 0; i < n; i++) - { - if (!strcmp(l_ringList[j][i].ringName, - RING_PROPERTIES[i_ringId].iv_name)) - { - return &(l_ringList[j][i]); - } - } - } - - return NULL; -} diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H index b6ec27a85..c0aff85a7 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -38,7 +38,7 @@ #endif -enum CHIPLET_TYPE +enum Chiplets { PERV_TYPE, N0_TYPE, @@ -56,123 +56,12 @@ enum CHIPLET_TYPE PCI2_TYPE, EQ_TYPE, EC_TYPE, - SBE_NOOF_CHIPLETS + SBE_NUM_CHIPLETS }; -const ChipletType_t CME_NOOF_CHIPLETS = 1; -const ChipletType_t SGPE_NOOF_CHIPLETS = 1; +const ChipletType_t CME_NUM_CHIPLETS = 1; +const ChipletType_t SGPE_NUM_CHIPLETS = 1; -namespace PERV -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace N0 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace N1 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace N2 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace N3 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace XB -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace MC -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace OB0 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace OB1 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace OB2 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace OB3 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace PCI0 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace PCI1 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace PCI2 -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace EQ -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} - -namespace EC -{ -extern const GenRingIdList RING_ID_LIST_COMMON[]; -extern const GenRingIdList RING_ID_LIST_INSTANCE[]; -extern const RingVariantOrder RING_VARIANT_ORDER[]; -} namespace PERV { @@ -213,12 +102,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 1, // Pervasive Chiplet ID is 1 + 0x01, // Base chiplet/instance ID + 1, // Number of chiplet instances 21, // 21 common rings for pervasive chiplet 3, // 3 instance specific rings for pervasive chiplet 3, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace PERV namespace N0 @@ -243,12 +135,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 2, // N0 Chiplet ID is 2. + 0x02, // Base chiplet/instance ID + 1, // Number of chiplet instances 9, // 9 common rings for N0 Chiplet 3, // 3 instance specific rings for N0 chiplet 3, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace N1 @@ -277,12 +172,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 3, // N1 Chiplet ID is 3. + 0x03, // Base chiplet/instance ID + 1, // Number of chiplet instances 12, // 12 common rings for N1 Chiplet 4, // 4 instance specific rings for N1 chiplet 4, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace N2 @@ -306,12 +204,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 4, // N2 Chiplet ID is 4. + 0x04, // Base chiplet/instance ID + 1, // Number of chiplet instances 9, // 9 common rings for N2 Chiplet 2, // 2 instance specific rings for N2 chiplet 2, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace N3 @@ -337,12 +238,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 5, // N3 Chiplet ID is 5 + 0x05, // Base chiplet/instance ID + 1, // Number of chiplet instances 10,// 10 common rings for N3 Chiplet 3, // 3 instance specific rings for N3 chiplet 3, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace XB @@ -374,12 +278,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 6, // X-Bus Chiplet ID is 6 + 0x06, // Base chiplet/instance ID + 1, // Number of chiplet instances 15, // 15 common rings for X-Bus Chiplet 4, // 4 instance specific rings for XB chiplet 4, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace XB namespace MC @@ -421,12 +328,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 7, // MC Chiplet ID range is 7 - 8. The base ID is 7. + 0x07, // Base chiplet/instance ID + 2, // Number of chiplet instances 25, // 25 common rings for MC Chiplet 3, // 3 instance specific rings for each MC instance 3, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace MC namespace OB0 @@ -448,12 +358,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 9, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. + 0x09, // Base chiplet/instance ID + 1, // Number of chiplet instances 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace OB0 namespace OB1 @@ -475,12 +388,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. + 0x0a, // Base chiplet/instance ID + 1, // Number of chiplet instances 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace OB1 @@ -503,12 +419,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. + 0x0b, // Base chiplet/instance ID + 1, // Number of chiplet instances 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace OB2 namespace OB3 @@ -530,12 +449,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. + 0x0c, // Base chiplet/instance ID + 1, // Number of chiplet instances 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; // end of namespace OB2 namespace PCI0 @@ -554,12 +476,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 13, // PCI0 Chiplet Chiplet ID is 13 + 0x0d, // Base chiplet/instance ID + 1, // Number of chiplet instances 5, // 5 common rings for PCI0 chiplet 1, // 1 instance specific rings for PCI0 chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace PCI1 @@ -578,12 +503,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 14, // PCI1 Chiplet Chiplet ID is 14 + 0x0e, // Base chiplet/instance ID + 1, // Number of chiplet instances 5, // 5 common rings for PCI1 chiplet 1, // 1 instance specific rings for PCI1 chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace PCI2 @@ -602,12 +530,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 15, // PCI2 Chiplet Chiplet ID is 15 + 0x0f, // Base chiplet/instance ID + 1, // Number of chiplet instances 5, // 5 common rings for PCI2 chiplet 1, // 1 instance specific rings for PCI2 chiplet 1, 2, // 2 common ring variants: BASE, RL + { RV_BASE, RV_RL, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT, UNDEFINED_RING_VARIANT } }; + }; namespace EQ @@ -693,12 +624,17 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 16, // Quad Chiplet ID range is 16 - 21. The base ID is 16. + 0x10, // Base chiplet/instance ID. + // Note that the Quad EQ chiplet/instance ID range is 16 - 21 but that in addition + // to this there are two EXs per EQ: even and odd, making a total of 12 instances + 12, // Max num of EX/EQ combined instance IDs = 2 (EX) x 6 (EQ) = 12 66, // 66 common rings for Quad chiplet. 5, // 5 instance specific rings for each EQ chiplet 9, // 9 different rings since 2 per EX ring and 1 per EQ 7, // 7 common ring variants: BASE, CC, RL, RL2/3/4/5 + { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 } }; + }; // end of namespace EQ namespace EC @@ -718,12 +654,15 @@ enum RingOffset static const ChipletData_t g_chipletData = { - 32, // Core Chiplet ID range is 32-55. The base ID is 32. + 0x20, // Core chiplet/instance ID range is 32-55. The base instance ID is 32. + 24, // Number of chiplet instances 6, // 6 common rings for Core chiplet 1, // 1 instance specific ring for each Core chiplet 1, 7, // 7 common ring variants: BASE, CC, RL, RL2/3/4/5 + { RV_BASE, RV_CC, RV_RL, RV_RL2, RV_RL3, RV_RL4, RV_RL5 } }; + }; // end of namespace EC @@ -731,568 +670,555 @@ static const ChipletData_t g_chipletData = static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - { PERV::perv_fure , "perv_fure" , PERV_TYPE }, // 0 - { PERV::perv_gptr , "perv_gptr" , PERV_TYPE }, // 1 - { PERV::perv_time , "perv_time" , PERV_TYPE }, // 2 - { PERV::occ_fure , "occ_fure" , PERV_TYPE }, // 3 - { PERV::occ_gptr , "occ_gptr" , PERV_TYPE }, // 4 - { PERV::occ_time , "occ_time" , PERV_TYPE }, // 5 - { PERV::perv_ana_func , "perv_ana_func" , PERV_TYPE }, // 6 - { PERV::perv_ana_gptr , "perv_ana_gptr" , PERV_TYPE }, // 7 - { PERV::perv_pll_gptr , "perv_pll_gptr" , PERV_TYPE }, // 8 - { PERV::perv_pll_bndy , "perv_pll_bndy" , PERV_TYPE }, // 9 - { PERV::perv_pll_bndy_bucket_1 , "perv_pll_bndy_bucket_1" , PERV_TYPE }, // 10 - { PERV::perv_pll_bndy_bucket_2 , "perv_pll_bndy_bucket_2" , PERV_TYPE }, // 11 - { PERV::perv_pll_bndy_bucket_3 , "perv_pll_bndy_bucket_3" , PERV_TYPE }, // 12 - { PERV::perv_pll_bndy_bucket_4 , "perv_pll_bndy_bucket_4" , PERV_TYPE }, // 13 - { PERV::perv_pll_bndy_bucket_5 , "perv_pll_bndy_bucket_5" , PERV_TYPE }, // 14 - { PERV::perv_pll_func , "perv_pll_func" , PERV_TYPE }, // 15 - { PERV::perv_repr , "perv_repr" , PERV_TYPE }, // 16 - { PERV::occ_repr , "occ_repr" , PERV_TYPE }, // 17 - { PERV::sbe_fure , "sbe_fure" , PERV_TYPE }, // 18 - { PERV::sbe_gptr , "sbe_gptr" , PERV_TYPE }, // 19 - { PERV::sbe_repr , "sbe_repr" , PERV_TYPE }, // 20 - { N0::n0_fure , "n0_fure" , N0_TYPE }, // 21 - { N0::n0_gptr , "n0_gptr" , N0_TYPE }, // 22 - { N0::n0_time , "n0_time" , N0_TYPE }, // 23 - { N0::n0_nx_fure , "n0_nx_fure" , N0_TYPE }, // 24 - { N0::n0_nx_gptr , "n0_nx_gptr" , N0_TYPE }, // 25 - { N0::n0_nx_time , "n0_nx_time" , N0_TYPE }, // 26 - { N0::n0_cxa0_fure , "n0_cxa0_fure" , N0_TYPE }, // 27 - { N0::n0_cxa0_gptr , "n0_cxa0_gptr" , N0_TYPE }, // 28 - { N0::n0_cxa0_time , "n0_cxa0_time" , N0_TYPE }, // 29 - { N0::n0_repr , "n0_repr" , N0_TYPE }, // 30 - { N0::n0_nx_repr , "n0_nx_repr" , N0_TYPE }, // 31 - { N0::n0_cxa0_repr , "n0_cxa0_repr" , N0_TYPE }, // 32 - { N1::n1_fure , "n1_fure" , N1_TYPE }, // 33 - { N1::n1_gptr , "n1_gptr" , N1_TYPE }, // 34 - { N1::n1_time , "n1_time" , N1_TYPE }, // 35 - { N1::n1_ioo0_fure , "n1_ioo0_fure" , N1_TYPE }, // 36 - { N1::n1_ioo0_gptr , "n1_ioo0_gptr" , N1_TYPE }, // 37 - { N1::n1_ioo0_time , "n1_ioo0_time" , N1_TYPE }, // 38 - { N1::n1_ioo1_fure , "n1_ioo1_fure" , N1_TYPE }, // 39 - { N1::n1_ioo1_gptr , "n1_ioo1_gptr" , N1_TYPE }, // 40 - { N1::n1_ioo1_time , "n1_ioo1_time" , N1_TYPE }, // 41 - { N1::n1_mcs23_fure , "n1_mcs23_fure" , N1_TYPE }, // 42 - { N1::n1_mcs23_gptr , "n1_mcs23_gptr" , N1_TYPE }, // 43 - { N1::n1_mcs23_time , "n1_mcs23_time" , N1_TYPE }, // 44 - { N1::n1_repr , "n1_repr" , N1_TYPE }, // 45 - { N1::n1_ioo0_repr , "n1_ioo0_repr" , N1_TYPE }, // 46 - { N1::n1_ioo1_repr , "n1_ioo1_repr" , N1_TYPE }, // 47 - { N1::n1_mcs23_repr , "n1_mcs23_repr" , N1_TYPE }, // 48 - { N2::n2_fure , "n2_fure" , N2_TYPE }, // 49 - { N2::n2_gptr , "n2_gptr" , N2_TYPE }, // 50 - { N2::n2_time , "n2_time" , N2_TYPE }, // 51 - { N2::n2_cxa1_fure , "n2_cxa1_fure" , N2_TYPE }, // 52 - { N2::n2_cxa1_gptr , "n2_cxa1_gptr" , N2_TYPE }, // 53 - { N2::n2_cxa1_time , "n2_cxa1_time" , N2_TYPE }, // 54 - { N2::n2_psi_fure , "n2_psi_fure" , N2_TYPE }, // 55 - { N2::n2_psi_gptr , "n2_psi_gptr" , N2_TYPE }, // 56 - { N2::n2_psi_time , "n2_psi_time" , N2_TYPE }, // 57 - { N2::n2_repr , "n2_repr" , N2_TYPE }, // 58 - { N2::n2_cxa1_repr , "n2_cxa1_repr" , N2_TYPE }, // 59 - { INVALID_RING_OFFSET , "invalid" , N2_TYPE }, // 60 - { INVALID_RING_OFFSET , "invalid" , N2_TYPE }, // 61 - { N3::n3_fure , "n3_fure" , N3_TYPE }, // 62 - { N3::n3_gptr , "n3_gptr" , N3_TYPE }, // 63 - { N3::n3_time , "n3_time" , N3_TYPE }, // 64 - { N3::n3_mcs01_fure , "n3_mcs01_fure" , N3_TYPE }, // 65 - { N3::n3_mcs01_gptr , "n3_mcs01_gptr" , N3_TYPE }, // 66 - { N3::n3_mcs01_time , "n3_mcs01_time" , N3_TYPE }, // 67 - { N3::n3_np_fure , "n3_np_fure" , N3_TYPE }, // 68 - { N3::n3_np_gptr , "n3_np_gptr" , N3_TYPE }, // 69 - { N3::n3_np_time , "n3_np_time" , N3_TYPE }, // 70 - { N3::n3_repr , "n3_repr" , N3_TYPE }, // 71 - { N3::n3_mcs01_repr , "n3_mcs01_repr" , N3_TYPE }, // 72 - { N3::n3_np_repr , "n3_np_repr" , N3_TYPE }, // 73 - { N3::n3_br_fure , "n3_br_fure" , N3_TYPE }, // 74 - { XB::xb_fure , "xb_fure" , XB_TYPE }, // 75 - { XB::xb_gptr , "xb_gptr" , XB_TYPE }, // 76 - { XB::xb_time , "xb_time" , XB_TYPE }, // 77 - { XB::xb_io0_fure , "xb_io0_fure" , XB_TYPE }, // 78 - { XB::xb_io0_gptr , "xb_io0_gptr" , XB_TYPE }, // 79 - { XB::xb_io0_time , "xb_io0_time" , XB_TYPE }, // 80 - { XB::xb_io1_fure , "xb_io1_fure" , XB_TYPE }, // 81 - { XB::xb_io1_gptr , "xb_io1_gptr" , XB_TYPE }, // 82 - { XB::xb_io1_time , "xb_io1_time" , XB_TYPE }, // 83 - { XB::xb_io2_fure , "xb_io2_fure" , XB_TYPE }, // 84 - { XB::xb_io2_gptr , "xb_io2_gptr" , XB_TYPE }, // 85 - { XB::xb_io2_time , "xb_io2_time" , XB_TYPE }, // 86 - { XB::xb_pll_gptr , "xb_pll_gptr" , XB_TYPE }, // 87 - { XB::xb_pll_bndy , "xb_pll_bndy" , XB_TYPE }, // 88 - { XB::xb_pll_func , "xb_pll_func" , XB_TYPE }, // 89 - { XB::xb_repr , "xb_repr" , XB_TYPE }, // 90 - { XB::xb_io0_repr , "xb_io0_repr" , XB_TYPE }, // 91 - { XB::xb_io1_repr , "xb_io1_repr" , XB_TYPE }, // 92 - { XB::xb_io2_repr , "xb_io2_repr" , XB_TYPE }, // 93 - { INVALID_RING_OFFSET , "invalid" , XB_TYPE }, // 94 - { INVALID_RING_OFFSET , "invalid" , XB_TYPE }, // 95 - { MC::mc_fure , "mc_fure" , MC_TYPE }, // 96 - { MC::mc_gptr , "mc_gptr" , MC_TYPE }, // 97 - { MC::mc_time , "mc_time" , MC_TYPE }, // 98 - { MC::mc_iom01_fure , "mc_iom01_fure" , MC_TYPE }, // 99 - { MC::mc_iom01_gptr , "mc_iom01_gptr" , MC_TYPE }, // 100 - { MC::mc_iom01_time , "mc_iom01_time" , MC_TYPE }, // 101 - { MC::mc_iom23_fure , "mc_iom23_fure" , MC_TYPE }, // 102 - { MC::mc_iom23_gptr , "mc_iom23_gptr" , MC_TYPE }, // 103 - { MC::mc_iom23_time , "mc_iom23_time" , MC_TYPE }, // 104 - { MC::mc_pll_gptr , "mc_pll_gptr" , MC_TYPE }, // 105 - { MC::mc_pll_bndy , "mc_pll_bndy" , MC_TYPE }, // 106 - { MC::mc_pll_bndy_bucket_1 , "mc_pll_bndy_bucket_1" , MC_TYPE }, // 107 - { MC::mc_pll_bndy_bucket_2 , "mc_pll_bndy_bucket_2" , MC_TYPE }, // 108 - { MC::mc_pll_bndy_bucket_3 , "mc_pll_bndy_bucket_3" , MC_TYPE }, // 109 - { MC::mc_pll_bndy_bucket_4 , "mc_pll_bndy_bucket_4" , MC_TYPE }, // 110 - { MC::mc_pll_bndy_bucket_5 , "mc_pll_bndy_bucket_5" , MC_TYPE }, // 111 - { MC::mc_pll_func , "mc_pll_func" , MC_TYPE }, // 112 - { MC::mc_repr , "mc_repr" , MC_TYPE }, // 113 - { INVALID_RING_OFFSET , "invalid" , MC_TYPE }, // 114 - { MC::mc_iom23_repr , "mc_iom23_repr" , MC_TYPE }, // 115 - { OB0::ob0_pll_bndy , "ob0_pll_bndy" , OB0_TYPE }, // 116 - { OB0::ob0_pll_bndy_bucket_1 , "ob0_pll_bndy_bucket_1" , OB0_TYPE }, // 117 - { OB0::ob0_pll_bndy_bucket_2 , "ob0_pll_bndy_bucket_2" , OB0_TYPE }, // 118 - { OB0::ob0_gptr , "ob0_gptr" , OB0_TYPE }, // 119 - { OB0::ob0_time , "ob0_time" , OB0_TYPE }, // 120 - { OB0::ob0_pll_gptr , "ob0_pll_gptr" , OB0_TYPE }, // 121 - { OB0::ob0_fure , "ob0_fure" , OB0_TYPE }, // 122 - { OB0::ob0_pll_bndy_bucket_3 , "ob0_pll_bndy_bucket_3" , OB0_TYPE }, // 123 - { OB0::ob0_repr , "ob0_repr" , OB0_TYPE }, // 124 - { OB1::ob1_pll_bndy , "ob1_pll_bndy" , OB1_TYPE }, // 125 - { OB1::ob1_pll_bndy_bucket_1 , "ob1_pll_bndy_bucket_1" , OB1_TYPE }, // 126 - { OB1::ob1_pll_bndy_bucket_2 , "ob1_pll_bndy_bucket_2" , OB1_TYPE }, // 127 - { OB1::ob1_gptr , "ob1_gptr" , OB1_TYPE }, // 128 - { OB1::ob1_time , "ob1_time" , OB1_TYPE }, // 129 - { OB1::ob1_pll_gptr , "ob1_pll_gptr" , OB1_TYPE }, // 130 - { OB1::ob1_fure , "ob1_fure" , OB1_TYPE }, // 131 - { OB1::ob1_pll_bndy_bucket_3 , "ob1_pll_bndy_bucket_3" , OB1_TYPE }, // 132 - { OB1::ob1_repr , "ob1_repr" , OB1_TYPE }, // 133 - { OB2::ob2_pll_bndy , "ob2_pll_bndy" , OB2_TYPE }, // 134 - { OB2::ob2_pll_bndy_bucket_1 , "ob2_pll_bndy_bucket_1" , OB2_TYPE }, // 135 - { OB2::ob2_pll_bndy_bucket_2 , "ob2_pll_bndy_bucket_2" , OB2_TYPE }, // 136 - { OB2::ob2_gptr , "ob2_gptr" , OB2_TYPE }, // 137 - { OB2::ob2_time , "ob2_time" , OB2_TYPE }, // 138 - { OB2::ob2_pll_gptr , "ob2_pll_gptr" , OB2_TYPE }, // 139 - { OB2::ob2_fure , "ob2_fure" , OB2_TYPE }, // 140 - { OB2::ob2_pll_bndy_bucket_3 , "ob2_pll_bndy_bucket_3" , OB2_TYPE }, // 141 - { OB2::ob2_repr , "ob2_repr" , OB2_TYPE }, // 142 - { OB3::ob3_pll_bndy , "ob3_pll_bndy" , OB3_TYPE }, // 143 - { OB3::ob3_pll_bndy_bucket_1 , "ob3_pll_bndy_bucket_1" , OB3_TYPE }, // 144 - { OB3::ob3_pll_bndy_bucket_2 , "ob3_pll_bndy_bucket_2" , OB3_TYPE }, // 145 - { OB3::ob3_gptr , "ob3_gptr" , OB3_TYPE }, // 146 - { OB3::ob3_time , "ob3_time" , OB3_TYPE }, // 147 - { OB3::ob3_pll_gptr , "ob3_pll_gptr" , OB3_TYPE }, // 148 - { OB3::ob3_fure , "ob3_fure" , OB3_TYPE }, // 149 - { OB3::ob3_pll_bndy_bucket_3 , "ob3_pll_bndy_bucket_3" , OB3_TYPE }, // 150 - { OB3::ob3_repr , "ob3_repr" , OB3_TYPE }, // 151 - { INVALID_RING_OFFSET , "invalid" , OB3_TYPE }, // 152 - { INVALID_RING_OFFSET , "invalid" , OB3_TYPE }, // 153 - { PCI0::pci0_fure , "pci0_fure" , PCI0_TYPE }, // 154 - { PCI0::pci0_gptr , "pci0_gptr" , PCI0_TYPE }, // 155 - { PCI0::pci0_time , "pci0_time" , PCI0_TYPE }, // 156 - { PCI0::pci0_pll_bndy , "pci0_pll_bndy" , PCI0_TYPE }, // 157 - { PCI0::pci0_pll_gptr , "pci0_pll_gptr" , PCI0_TYPE }, // 158 - { PCI0::pci0_repr , "pci0_repr" , PCI0_TYPE }, // 159 - { PCI1::pci1_fure , "pci1_fure" , PCI1_TYPE }, // 160 - { PCI1::pci1_gptr , "pci1_gptr" , PCI1_TYPE }, // 161 - { PCI1::pci1_time , "pci1_time" , PCI1_TYPE }, // 162 - { PCI1::pci1_pll_bndy , "pci1_pll_bndy" , PCI1_TYPE }, // 163 - { PCI1::pci1_pll_gptr , "pci1_pll_gptr" , PCI1_TYPE }, // 164 - { PCI1::pci1_repr , "pci1_repr" , PCI1_TYPE }, // 165 - { PCI2::pci2_fure , "pci2_fure" , PCI2_TYPE }, // 166 - { PCI2::pci2_gptr , "pci2_gptr" , PCI2_TYPE }, // 167 - { PCI2::pci2_time , "pci2_time" , PCI2_TYPE }, // 168 - { PCI2::pci2_pll_bndy , "pci2_pll_bndy" , PCI2_TYPE }, // 169 - { PCI2::pci2_pll_gptr , "pci2_pll_gptr" , PCI2_TYPE }, // 170 - { PCI2::pci2_repr , "pci2_repr" , PCI2_TYPE }, // 171 - { EQ::eq_fure , "eq_fure" , EQ_TYPE }, // 172 - { EQ::eq_gptr , "eq_gptr" , EQ_TYPE }, // 173 - { EQ::eq_time , "eq_time" , EQ_TYPE }, // 174 - { EQ::eq_inex , "eq_inex" , EQ_TYPE }, // 175 - { EQ::ex_l3_fure , "ex_l3_fure" , EQ_TYPE }, // 176 - { EQ::ex_l3_gptr , "ex_l3_gptr" , EQ_TYPE }, // 177 - { EQ::ex_l3_time , "ex_l3_time" , EQ_TYPE }, // 178 - { EQ::ex_l2_mode , "ex_l2_mode" , EQ_TYPE }, // 179 - { EQ::ex_l2_fure , "ex_l2_fure" , EQ_TYPE }, // 180 - { EQ::ex_l2_gptr , "ex_l2_gptr" , EQ_TYPE }, // 181 - { EQ::ex_l2_time , "ex_l2_time" , EQ_TYPE }, // 182 - { EQ::ex_l3_refr_fure , "ex_l3_refr_fure" , EQ_TYPE }, // 183 - { EQ::ex_l3_refr_gptr , "ex_l3_refr_gptr" , EQ_TYPE }, // 184 - { EQ::ex_l3_refr_time , "ex_l3_refr_time" , EQ_TYPE }, // 185 - { EQ::eq_ana_func , "eq_ana_func" , EQ_TYPE }, // 186 - { EQ::eq_ana_gptr , "eq_ana_gptr" , EQ_TYPE }, // 187 - { EQ::eq_dpll_func , "eq_dpll_func" , EQ_TYPE }, // 188 - { EQ::eq_dpll_gptr , "eq_dpll_gptr" , EQ_TYPE }, // 189 - { EQ::eq_dpll_mode , "eq_dpll_mode" , EQ_TYPE }, // 190 - { EQ::eq_ana_bndy , "eq_ana_bndy" , EQ_TYPE }, // 191 - { EQ::eq_ana_bndy_bucket_0 , "eq_ana_bndy_bucket_0" , EQ_TYPE }, // 192 - { EQ::eq_ana_bndy_bucket_1 , "eq_ana_bndy_bucket_1" , EQ_TYPE }, // 193 - { EQ::eq_ana_bndy_bucket_2 , "eq_ana_bndy_bucket_2" , EQ_TYPE }, // 194 - { EQ::eq_ana_bndy_bucket_3 , "eq_ana_bndy_bucket_3" , EQ_TYPE }, // 195 - { EQ::eq_ana_bndy_bucket_4 , "eq_ana_bndy_bucket_4" , EQ_TYPE }, // 196 - { EQ::eq_ana_bndy_bucket_5 , "eq_ana_bndy_bucket_5" , EQ_TYPE }, // 197 - { EQ::eq_ana_bndy_bucket_6 , "eq_ana_bndy_bucket_6" , EQ_TYPE }, // 198 - { EQ::eq_ana_bndy_bucket_7 , "eq_ana_bndy_bucket_7" , EQ_TYPE }, // 199 - { EQ::eq_ana_bndy_bucket_8 , "eq_ana_bndy_bucket_8" , EQ_TYPE }, // 200 - { EQ::eq_ana_bndy_bucket_9 , "eq_ana_bndy_bucket_9" , EQ_TYPE }, // 201 - { EQ::eq_ana_bndy_bucket_10 , "eq_ana_bndy_bucket_10" , EQ_TYPE }, // 202 - { EQ::eq_ana_bndy_bucket_11 , "eq_ana_bndy_bucket_11" , EQ_TYPE }, // 203 - { EQ::eq_ana_bndy_bucket_12 , "eq_ana_bndy_bucket_12" , EQ_TYPE }, // 204 - { EQ::eq_ana_bndy_bucket_13 , "eq_ana_bndy_bucket_13" , EQ_TYPE }, // 205 - { EQ::eq_ana_bndy_bucket_14 , "eq_ana_bndy_bucket_14" , EQ_TYPE }, // 206 - { EQ::eq_ana_bndy_bucket_15 , "eq_ana_bndy_bucket_15" , EQ_TYPE }, // 207 - { EQ::eq_ana_bndy_bucket_16 , "eq_ana_bndy_bucket_16" , EQ_TYPE }, // 208 - { EQ::eq_ana_bndy_bucket_17 , "eq_ana_bndy_bucket_17" , EQ_TYPE }, // 209 - { EQ::eq_ana_bndy_bucket_18 , "eq_ana_bndy_bucket_18" , EQ_TYPE }, // 210 - { EQ::eq_ana_bndy_bucket_19 , "eq_ana_bndy_bucket_19" , EQ_TYPE }, // 211 - { EQ::eq_ana_bndy_bucket_20 , "eq_ana_bndy_bucket_20" , EQ_TYPE }, // 212 - { EQ::eq_ana_bndy_bucket_21 , "eq_ana_bndy_bucket_21" , EQ_TYPE }, // 213 - { EQ::eq_ana_bndy_bucket_22 , "eq_ana_bndy_bucket_22" , EQ_TYPE }, // 214 - { EQ::eq_ana_bndy_bucket_23 , "eq_ana_bndy_bucket_23" , EQ_TYPE }, // 215 - { EQ::eq_ana_bndy_bucket_24 , "eq_ana_bndy_bucket_24" , EQ_TYPE }, // 216 - { EQ::eq_ana_bndy_bucket_25 , "eq_ana_bndy_bucket_25" , EQ_TYPE }, // 217 - { EQ::eq_ana_bndy_bucket_l3dcc , "eq_ana_bndy_bucket_l3dcc" , EQ_TYPE }, // 218 - { EQ::eq_ana_mode , "eq_ana_mode" , EQ_TYPE }, // 219 - { EQ::eq_repr , "eq_repr" , EQ_TYPE }, // 220 - { EQ::ex_l3_repr , "ex_l3_repr" , EQ_TYPE }, // 221 - { EQ::ex_l2_repr , "ex_l2_repr" , EQ_TYPE }, // 222 - { EQ::ex_l3_refr_repr , "ex_l3_refr_repr" , EQ_TYPE }, // 223 - { EC::ec_func , "ec_func" , EC_TYPE }, // 224 - { EC::ec_gptr , "ec_gptr" , EC_TYPE }, // 225 - { EC::ec_time , "ec_time" , EC_TYPE }, // 226 - { EC::ec_mode , "ec_mode" , EC_TYPE }, // 227 - { EC::ec_repr , "ec_repr" , EC_TYPE }, // 228 - { INVALID_RING_OFFSET , "invalid" , EQ_TYPE }, // 229 - { INVALID_RING_OFFSET , "invalid" , EQ_TYPE }, // 230 - { EC::ec_abst , "ec_abst" , EC_TYPE }, // 231 - { EQ::eq_ana_bndy_bucket_26 , "eq_ana_bndy_bucket_26" , EQ_TYPE }, // 232 - { EQ::eq_ana_bndy_bucket_27 , "eq_ana_bndy_bucket_27" , EQ_TYPE }, // 233 - { EQ::eq_ana_bndy_bucket_28 , "eq_ana_bndy_bucket_28" , EQ_TYPE }, // 234 - { EQ::eq_ana_bndy_bucket_29 , "eq_ana_bndy_bucket_29" , EQ_TYPE }, // 235 - { EQ::eq_ana_bndy_bucket_30 , "eq_ana_bndy_bucket_30" , EQ_TYPE }, // 236 - { EQ::eq_ana_bndy_bucket_31 , "eq_ana_bndy_bucket_31" , EQ_TYPE }, // 237 - { EQ::eq_ana_bndy_bucket_32 , "eq_ana_bndy_bucket_32" , EQ_TYPE }, // 238 - { EQ::eq_ana_bndy_bucket_33 , "eq_ana_bndy_bucket_33" , EQ_TYPE }, // 239 - { EQ::eq_ana_bndy_bucket_34 , "eq_ana_bndy_bucket_34" , EQ_TYPE }, // 240 - { EQ::eq_ana_bndy_bucket_35 , "eq_ana_bndy_bucket_35" , EQ_TYPE }, // 241 - { EQ::eq_ana_bndy_bucket_36 , "eq_ana_bndy_bucket_36" , EQ_TYPE }, // 242 - { EQ::eq_ana_bndy_bucket_37 , "eq_ana_bndy_bucket_37" , EQ_TYPE }, // 243 - { EQ::eq_ana_bndy_bucket_38 , "eq_ana_bndy_bucket_38" , EQ_TYPE }, // 244 - { EQ::eq_ana_bndy_bucket_39 , "eq_ana_bndy_bucket_39" , EQ_TYPE }, // 245 - { EQ::eq_ana_bndy_bucket_40 , "eq_ana_bndy_bucket_40" , EQ_TYPE }, // 246 - { EQ::eq_ana_bndy_bucket_41 , "eq_ana_bndy_bucket_41" , EQ_TYPE }, // 247 - { EQ::eq_inex_bucket_1 , "eq_inex_bucket_1" , EQ_TYPE }, // 248 - { EQ::eq_inex_bucket_2 , "eq_inex_bucket_2" , EQ_TYPE }, // 249 - { EQ::eq_inex_bucket_3 , "eq_inex_bucket_3" , EQ_TYPE }, // 250 - { EQ::eq_inex_bucket_4 , "eq_inex_bucket_4" , EQ_TYPE }, // 251 - { EC::ec_cmsk , "ec_cmsk" , EC_TYPE }, // 252 - { PERV::perv_pll_bndy_flt_1 , "perv_pll_bndy_flt_1" , PERV_TYPE }, // 253 - { PERV::perv_pll_bndy_flt_2 , "perv_pll_bndy_flt_2" , PERV_TYPE }, // 254 - { PERV::perv_pll_bndy_flt_3 , "perv_pll_bndy_flt_3" , PERV_TYPE }, // 255 - { PERV::perv_pll_bndy_flt_4 , "perv_pll_bndy_flt_4" , PERV_TYPE }, // 256 - { MC::mc_omi0_fure , "mc_omi0_fure" , MC_TYPE }, // 257 - { MC::mc_omi0_gptr , "mc_omi0_gptr" , MC_TYPE }, // 258 - { MC::mc_omi1_fure , "mc_omi1_fure" , MC_TYPE }, // 259 - { MC::mc_omi1_gptr , "mc_omi1_gptr" , MC_TYPE }, // 260 - { MC::mc_omi2_fure , "mc_omi2_fure" , MC_TYPE }, // 261 - { MC::mc_omi2_gptr , "mc_omi2_gptr" , MC_TYPE }, // 262 - { MC::mc_omippe_fure , "mc_omippe_fure" , MC_TYPE }, // 263 - { MC::mc_omippe_gptr , "mc_omippe_gptr" , MC_TYPE }, // 264 - { MC::mc_omippe_time , "mc_omippe_time" , MC_TYPE }, // 265 - { MC::mc_omippe_repr , "mc_omippe_repr" , MC_TYPE }, // 266 + { "perv_fure" , 0x0103400F, PERV::perv_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 0 + { "perv_gptr" , 0x01034002, PERV::perv_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 1 + { "perv_time" , 0x01034007, PERV::perv_time , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 2 + { "occ_fure" , 0x0103080F, PERV::occ_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 3 + { "occ_gptr" , 0x01030802, PERV::occ_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 4 + { "occ_time" , 0x01030807, PERV::occ_time , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 5 + { "perv_ana_func" , 0x01030400, PERV::perv_ana_func , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 6 + { "perv_ana_gptr" , 0x01030402, PERV::perv_ana_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 7 + { "perv_pll_gptr" , 0x01030012, PERV::perv_pll_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 8 + { "perv_pll_bndy" , 0x01030018, PERV::perv_pll_bndy , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 9 + { "perv_pll_bndy_bucket_1" , 0x01030018, PERV::perv_pll_bndy_bucket_1, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 10 + { "perv_pll_bndy_bucket_2" , 0x01030018, PERV::perv_pll_bndy_bucket_2, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 11 + { "perv_pll_bndy_bucket_3" , 0x01030018, PERV::perv_pll_bndy_bucket_3, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 12 + { "perv_pll_bndy_bucket_4" , 0x01030018, PERV::perv_pll_bndy_bucket_4, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 13 + { "perv_pll_bndy_bucket_5" , 0x01030018, PERV::perv_pll_bndy_bucket_5, PERV_TYPE, RCLS_EKB_FLUSH_RING }, // 14 + { "perv_pll_func" , 0x01030010, PERV::perv_pll_func , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 15 + { "perv_repr" , 0x01034006, PERV::perv_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 16 + { "occ_repr" , 0x01030806, PERV::occ_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 17 + { "sbe_fure" , 0x0103020F, PERV::sbe_fure , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 18 + { "sbe_gptr" , 0x01030202, PERV::sbe_gptr , PERV_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 19 + { "sbe_repr" , 0x01030206, PERV::sbe_repr , PERV_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 20 + { "n0_fure" , 0x02034E0F, N0::n0_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 21 + { "n0_gptr" , 0x02034E02, N0::n0_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 22 + { "n0_time" , 0x02034E07, N0::n0_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 23 + { "n0_nx_fure" , 0x0203200F, N0::n0_nx_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 24 + { "n0_nx_gptr" , 0x02032002, N0::n0_nx_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 25 + { "n0_nx_time" , 0x02032007, N0::n0_nx_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 26 + { "n0_cxa0_fure" , 0x0203100F, N0::n0_cxa0_fure , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 27 + { "n0_cxa0_gptr" , 0x02031002, N0::n0_cxa0_gptr , N0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 28 + { "n0_cxa0_time" , 0x02031007, N0::n0_cxa0_time , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 29 + { "n0_repr" , 0x02034E06, N0::n0_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 30 + { "n0_nx_repr" , 0x02032006, N0::n0_nx_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 31 + { "n0_cxa0_repr" , 0x02031006, N0::n0_cxa0_repr , N0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 32 + { "n1_fure" , 0x0303700F, N1::n1_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 33 + { "n1_gptr" , 0x03037002, N1::n1_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 34 + { "n1_time" , 0x03037007, N1::n1_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 35 + { "n1_ioo0_fure" , 0x0303080F, N1::n1_ioo0_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 36 + { "n1_ioo0_gptr" , 0x03030802, N1::n1_ioo0_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 37 + { "n1_ioo0_time" , 0x03030807, N1::n1_ioo0_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 38 + { "n1_ioo1_fure" , 0x0303040F, N1::n1_ioo1_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 39 + { "n1_ioo1_gptr" , 0x03030402, N1::n1_ioo1_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 40 + { "n1_ioo1_time" , 0x03030407, N1::n1_ioo1_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 41 + { "n1_mcs23_fure" , 0x0303020F, N1::n1_mcs23_fure , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 42 + { "n1_mcs23_gptr" , 0x03030202, N1::n1_mcs23_gptr , N1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 43 + { "n1_mcs23_time" , 0x03030207, N1::n1_mcs23_time , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 44 + { "n1_repr" , 0x03037006, N1::n1_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 45 + { "n1_ioo0_repr" , 0x03030806, N1::n1_ioo0_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 46 + { "n1_ioo1_repr" , 0x03030406, N1::n1_ioo1_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 47 + { "n1_mcs23_repr" , 0x03030206, N1::n1_mcs23_repr , N1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 48 + { "n2_fure" , 0x04035C0F, N2::n2_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 49 + { "n2_gptr" , 0x04035C02, N2::n2_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 50 + { "n2_time" , 0x04035C07, N2::n2_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 51 + { "n2_cxa1_fure" , 0x0403200F, N2::n2_cxa1_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 52 + { "n2_cxa1_gptr" , 0x04032002, N2::n2_cxa1_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 53 + { "n2_cxa1_time" , 0x04032007, N2::n2_cxa1_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 54 + { "n2_psi_fure" , 0x0403020F, N2::n2_psi_fure , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 55 + { "n2_psi_gptr" , 0x04030202, N2::n2_psi_gptr , N2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 56 + { "n2_psi_time" , 0x04030207, N2::n2_psi_time , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 57 + { "n2_repr" , 0x04035C06, N2::n2_repr , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 58 + { "n2_cxa1_repr" , 0x04032006, N2::n2_cxa1_repr , N2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 59 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, N2_TYPE , UNDEFINED_RING_CLASS }, // 60 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, N2_TYPE , UNDEFINED_RING_CLASS }, // 61 + { "n3_fure" , 0x0503660F, N3::n3_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 62 + { "n3_gptr" , 0x05037602, N3::n3_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 63 + { "n3_time" , 0x05037607, N3::n3_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 64 + { "n3_mcs01_fure" , 0x0503010F, N3::n3_mcs01_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 65 + { "n3_mcs01_gptr" , 0x05030102, N3::n3_mcs01_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 66 + { "n3_mcs01_time" , 0x05030107, N3::n3_mcs01_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 67 + { "n3_np_fure" , 0x0503080F, N3::n3_np_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 68 + { "n3_np_gptr" , 0x05030802, N3::n3_np_gptr , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 69 + { "n3_np_time" , 0x05030807, N3::n3_np_time , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 70 + { "n3_repr" , 0x05037606, N3::n3_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 71 + { "n3_mcs01_repr" , 0x05030106, N3::n3_mcs01_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 72 + { "n3_np_repr" , 0x05030806, N3::n3_np_repr , N3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 73 + { "n3_br_fure" , 0x0503100F, N3::n3_br_fure , N3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 74 + { "xb_fure" , 0x0603440F, XB::xb_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 75 + { "xb_gptr" , 0x06034402, XB::xb_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 76 + { "xb_time" , 0x06034407, XB::xb_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 77 + { "xb_io0_fure" , 0x0603220F, XB::xb_io0_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 78 + { "xb_io0_gptr" , 0x06032202, XB::xb_io0_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 79 + { "xb_io0_time" , 0x06032207, XB::xb_io0_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 80 + { "xb_io1_fure" , 0x0603110F, XB::xb_io1_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 81 + { "xb_io1_gptr" , 0x06031102, XB::xb_io1_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 82 + { "xb_io1_time" , 0x06031107, XB::xb_io1_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 83 + { "xb_io2_fure" , 0x0603088F, XB::xb_io2_fure , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 84 + { "xb_io2_gptr" , 0x06030882, XB::xb_io2_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 85 + { "xb_io2_time" , 0x06030887, XB::xb_io2_time , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 86 + { "xb_pll_gptr" , 0x06030012, XB::xb_pll_gptr , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 87 + { "xb_pll_bndy" , 0x06030018, XB::xb_pll_bndy , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 88 + { "xb_pll_func" , 0x06030010, XB::xb_pll_func , XB_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 89 + { "xb_repr" , 0x06034406, XB::xb_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 90 + { "xb_io0_repr" , 0x06032206, XB::xb_io0_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 91 + { "xb_io1_repr" , 0x06031106, XB::xb_io1_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 92 + { "xb_io2_repr" , 0x06030886, XB::xb_io2_repr , XB_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 93 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, XB_TYPE , UNDEFINED_RING_CLASS }, // 94 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, XB_TYPE , UNDEFINED_RING_CLASS }, // 95 + { "mc_fure" , 0x0703600F, MC::mc_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 96 + { "mc_gptr" , 0x07036002, MC::mc_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 97 + { "mc_time" , 0x07036007, MC::mc_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 98 + { "mc_iom01_fure" , 0x0703100F, MC::mc_iom01_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 99 + { "mc_iom01_gptr" , 0x07031002, MC::mc_iom01_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 100 + { "mc_iom01_time" , 0x07031007, MC::mc_iom01_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 101 + { "mc_iom23_fure" , 0x0703080F, MC::mc_iom23_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 102 + { "mc_iom23_gptr" , 0x07030802, MC::mc_iom23_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 103 + { "mc_iom23_time" , 0x07030807, MC::mc_iom23_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 104 + { "mc_pll_gptr" , 0x07030012, MC::mc_pll_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 105 + { "mc_pll_bndy" , 0x07030018, MC::mc_pll_bndy , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 106 + { "mc_pll_bndy_bucket_1" , 0x07030018, MC::mc_pll_bndy_bucket_1 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 107 + { "mc_pll_bndy_bucket_2" , 0x07030018, MC::mc_pll_bndy_bucket_2 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 108 + { "mc_pll_bndy_bucket_3" , 0x07030018, MC::mc_pll_bndy_bucket_3 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 109 + { "mc_pll_bndy_bucket_4" , 0x07030018, MC::mc_pll_bndy_bucket_4 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 110 + { "mc_pll_bndy_bucket_5" , 0x07030018, MC::mc_pll_bndy_bucket_5 , MC_TYPE , RCLS_EKB_FLUSH_RING }, // 111 + { "mc_pll_func" , 0x07030010, MC::mc_pll_func , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 112 + { "mc_repr" , 0x07036006, MC::mc_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 113 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, MC_TYPE , UNDEFINED_RING_CLASS }, // 114 + { "mc_iom23_repr" , 0x07030806, MC::mc_iom23_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 115 + { "ob0_pll_bndy" , 0x09030018, OB0::ob0_pll_bndy , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 116 + { "ob0_pll_bndy_bucket_1" , 0x09030018, OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 117 + { "ob0_pll_bndy_bucket_2" , 0x09030018, OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 118 + { "ob0_gptr" , 0x09037002, OB0::ob0_gptr , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 119 + { "ob0_time" , 0x09037007, OB0::ob0_time , OB0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 120 + { "ob0_pll_gptr" , 0x09030012, OB0::ob0_pll_gptr , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 121 + { "ob0_fure" , 0x0903700F, OB0::ob0_fure , OB0_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 122 + { "ob0_pll_bndy_bucket_3" , 0x09030018, OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE , RCLS_EKB_FLUSH_RING }, // 123 + { "ob0_repr" , 0x09037006, OB0::ob0_repr , OB0_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 124 + { "ob1_pll_bndy" , 0x0A030018, OB1::ob1_pll_bndy , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 125 + { "ob1_pll_bndy_bucket_1" , 0x0A030018, OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 126 + { "ob1_pll_bndy_bucket_2" , 0x0A030018, OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 127 + { "ob1_gptr" , 0x0A037002, OB1::ob1_gptr , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 128 + { "ob1_time" , 0x0A037007, OB1::ob1_time , OB1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 129 + { "ob1_pll_gptr" , 0x0A030012, OB1::ob1_pll_gptr , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 130 + { "ob1_fure" , 0x0A03700F, OB1::ob1_fure , OB1_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 131 + { "ob1_pll_bndy_bucket_3" , 0x0A030018, OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE , RCLS_EKB_FLUSH_RING }, // 132 + { "ob1_repr" , 0x0A037006, OB1::ob1_repr , OB1_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 133 + { "ob2_pll_bndy" , 0x0B030018, OB2::ob2_pll_bndy , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 134 + { "ob2_pll_bndy_bucket_1" , 0x0B030018, OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 135 + { "ob2_pll_bndy_bucket_2" , 0x0B030018, OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 136 + { "ob2_gptr" , 0x0B037002, OB2::ob2_gptr , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 137 + { "ob2_time" , 0x0B037007, OB2::ob2_time , OB2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 138 + { "ob2_pll_gptr" , 0x0B030012, OB2::ob2_pll_gptr , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 139 + { "ob2_fure" , 0x0B03700F, OB2::ob2_fure , OB2_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 140 + { "ob2_pll_bndy_bucket_3" , 0x0B030018, OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE , RCLS_EKB_FLUSH_RING }, // 141 + { "ob2_repr" , 0x0B037006, OB2::ob2_repr , OB2_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 142 + { "ob3_pll_bndy" , 0x0C030018, OB3::ob3_pll_bndy , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 143 + { "ob3_pll_bndy_bucket_1" , 0x0C030018, OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 144 + { "ob3_pll_bndy_bucket_2" , 0x0C030018, OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 145 + { "ob3_gptr" , 0x0C037002, OB3::ob3_gptr , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 146 + { "ob3_time" , 0x0C037007, OB3::ob3_time , OB3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 147 + { "ob3_pll_gptr" , 0x0C030012, OB3::ob3_pll_gptr , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 148 + { "ob3_fure" , 0x0C03700F, OB3::ob3_fure , OB3_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 149 + { "ob3_pll_bndy_bucket_3" , 0x0C030018, OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE , RCLS_EKB_FLUSH_RING }, // 150 + { "ob3_repr" , 0x0C037006, OB3::ob3_repr , OB3_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 151 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, OB3_TYPE , UNDEFINED_RING_CLASS }, // 152 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, OB3_TYPE , UNDEFINED_RING_CLASS }, // 153 + { "pci0_fure" , 0x0D03700F, PCI0::pci0_fure , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 154 + { "pci0_gptr" , 0x0D037002, PCI0::pci0_gptr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 155 + { "pci0_time" , 0x0D037007, PCI0::pci0_time , PCI0_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 156 + { "pci0_pll_bndy" , 0x0D030018, PCI0::pci0_pll_bndy , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 157 + { "pci0_pll_gptr" , 0x0D030012, PCI0::pci0_pll_gptr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 158 + { "pci0_repr" , 0x0D037006, PCI0::pci0_repr , PCI0_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 159 + { "pci1_fure" , 0x0E03780F, PCI1::pci1_fure , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 160 + { "pci1_gptr" , 0x0E037802, PCI1::pci1_gptr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 161 + { "pci1_time" , 0x0E037807, PCI1::pci1_time , PCI1_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 162 + { "pci1_pll_bndy" , 0x0E030018, PCI1::pci1_pll_bndy , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 163 + { "pci1_pll_gptr" , 0x0E030012, PCI1::pci1_pll_gptr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 164 + { "pci1_repr" , 0x0E037806, PCI1::pci1_repr , PCI1_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 165 + { "pci2_fure" , 0x0F037C0F, PCI2::pci2_fure , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 166 + { "pci2_gptr" , 0x0F037C02, PCI2::pci2_gptr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 167 + { "pci2_time" , 0x0F037C07, PCI2::pci2_time , PCI2_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 168 + { "pci2_pll_bndy" , 0x0F030018, PCI2::pci2_pll_bndy , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 169 + { "pci2_pll_gptr" , 0x0F030012, PCI2::pci2_pll_gptr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 170 + { "pci2_repr" , 0x0F037C06, PCI2::pci2_repr , PCI2_TYPE, RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 171 + { "eq_fure" , 0x1003608F, EQ::eq_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 172 + { "eq_gptr" , 0x10036082, EQ::eq_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 173 + { "eq_time" , 0x10036087, EQ::eq_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 174 + { "eq_inex" , 0x1003608B, EQ::eq_inex , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 175 + { "ex_l3_fure" , 0x1003100F, EQ::ex_l3_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 176 + { "ex_l3_gptr" , 0x10031002, EQ::ex_l3_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 177 + { "ex_l3_time" , 0x10031007, EQ::ex_l3_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 178 + { "ex_l2_mode" , 0x10030401, EQ::ex_l2_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 179 + { "ex_l2_fure" , 0x1003040F, EQ::ex_l2_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 180 + { "ex_l2_gptr" , 0x10030402, EQ::ex_l2_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 181 + { "ex_l2_time" , 0x10030407, EQ::ex_l2_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 182 + { "ex_l3_refr_fure" , 0x1003004F, EQ::ex_l3_refr_fure , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 183 + { "ex_l3_refr_gptr" , 0x10030042, EQ::ex_l3_refr_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 184 + { "ex_l3_refr_time" , 0x10030047, EQ::ex_l3_refr_time , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 185 + { "eq_ana_func" , 0x10030100, EQ::eq_ana_func , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 186 + { "eq_ana_gptr" , 0x10030102, EQ::eq_ana_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 187 + { "eq_dpll_func" , 0x10030010, EQ::eq_dpll_func , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 188 + { "eq_dpll_gptr" , 0x10030012, EQ::eq_dpll_gptr , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 189 + { "eq_dpll_mode" , 0x10030011, EQ::eq_dpll_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 190 + { "eq_ana_bndy" , 0x10030108, EQ::eq_ana_bndy , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FSM_RING }, // 191 + { "eq_ana_bndy_bucket_0" , 0x10030108, EQ::eq_ana_bndy_bucket_0 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 192 + { "eq_ana_bndy_bucket_1" , 0x10030108, EQ::eq_ana_bndy_bucket_1 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 193 + { "eq_ana_bndy_bucket_2" , 0x10030108, EQ::eq_ana_bndy_bucket_2 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 194 + { "eq_ana_bndy_bucket_3" , 0x10030108, EQ::eq_ana_bndy_bucket_3 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 195 + { "eq_ana_bndy_bucket_4" , 0x10030108, EQ::eq_ana_bndy_bucket_4 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 196 + { "eq_ana_bndy_bucket_5" , 0x10030108, EQ::eq_ana_bndy_bucket_5 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 197 + { "eq_ana_bndy_bucket_6" , 0x10030108, EQ::eq_ana_bndy_bucket_6 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 198 + { "eq_ana_bndy_bucket_7" , 0x10030108, EQ::eq_ana_bndy_bucket_7 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 199 + { "eq_ana_bndy_bucket_8" , 0x10030108, EQ::eq_ana_bndy_bucket_8 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 200 + { "eq_ana_bndy_bucket_9" , 0x10030108, EQ::eq_ana_bndy_bucket_9 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 201 + { "eq_ana_bndy_bucket_10" , 0x10030108, EQ::eq_ana_bndy_bucket_10 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 202 + { "eq_ana_bndy_bucket_11" , 0x10030108, EQ::eq_ana_bndy_bucket_11 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 203 + { "eq_ana_bndy_bucket_12" , 0x10030108, EQ::eq_ana_bndy_bucket_12 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 204 + { "eq_ana_bndy_bucket_13" , 0x10030108, EQ::eq_ana_bndy_bucket_13 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 205 + { "eq_ana_bndy_bucket_14" , 0x10030108, EQ::eq_ana_bndy_bucket_14 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 206 + { "eq_ana_bndy_bucket_15" , 0x10030108, EQ::eq_ana_bndy_bucket_15 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 207 + { "eq_ana_bndy_bucket_16" , 0x10030108, EQ::eq_ana_bndy_bucket_16 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 208 + { "eq_ana_bndy_bucket_17" , 0x10030108, EQ::eq_ana_bndy_bucket_17 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 209 + { "eq_ana_bndy_bucket_18" , 0x10030108, EQ::eq_ana_bndy_bucket_18 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 210 + { "eq_ana_bndy_bucket_19" , 0x10030108, EQ::eq_ana_bndy_bucket_19 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 211 + { "eq_ana_bndy_bucket_20" , 0x10030108, EQ::eq_ana_bndy_bucket_20 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 212 + { "eq_ana_bndy_bucket_21" , 0x10030108, EQ::eq_ana_bndy_bucket_21 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 213 + { "eq_ana_bndy_bucket_22" , 0x10030108, EQ::eq_ana_bndy_bucket_22 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 214 + { "eq_ana_bndy_bucket_23" , 0x10030108, EQ::eq_ana_bndy_bucket_23 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 215 + { "eq_ana_bndy_bucket_24" , 0x10030108, EQ::eq_ana_bndy_bucket_24 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 216 + { "eq_ana_bndy_bucket_25" , 0x10030108, EQ::eq_ana_bndy_bucket_25 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 217 + { "eq_ana_bndy_bucket_l3dcc", 0x10030108, EQ::eq_ana_bndy_bucket_l3dcc, EQ_TYPE , RCLS_EKB_FSM_RING }, // 218 + { "eq_ana_mode" , 0x10030101, EQ::eq_ana_mode , EQ_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 219 + { "eq_repr" , 0x10036086, EQ::eq_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 220 + { "ex_l3_repr" , 0x10031006, EQ::ex_l3_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 221 + { "ex_l2_repr" , 0x10030406, EQ::ex_l2_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 222 + { "ex_l3_refr_repr" , 0x10030046, EQ::ex_l3_refr_repr , EQ_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 223 + { "ec_func" , 0x2003700F, EC::ec_func , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_STUMPED_RING }, // 224 + { "ec_gptr" , 0x20037002, EC::ec_gptr , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 225 + { "ec_time" , 0x20037007, EC::ec_time , EC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 226 + { "ec_mode" , 0x20037001, EC::ec_mode , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 227 + { "ec_repr" , 0x20037006, EC::ec_repr , EC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 228 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, EQ_TYPE , UNDEFINED_RING_CLASS }, // 229 + { "invalid" , UNDEFINED_SCOM_ADDR, INVALID_RING_OFFSET, EQ_TYPE , UNDEFINED_RING_CLASS }, // 230 + { "ec_abst" , 0x20037005, EC::ec_abst , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 231 + { "eq_ana_bndy_bucket_26" , 0x10030108, EQ::eq_ana_bndy_bucket_26 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 232 + { "eq_ana_bndy_bucket_27" , 0x10030108, EQ::eq_ana_bndy_bucket_27 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 233 + { "eq_ana_bndy_bucket_28" , 0x10030108, EQ::eq_ana_bndy_bucket_28 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 234 + { "eq_ana_bndy_bucket_29" , 0x10030108, EQ::eq_ana_bndy_bucket_29 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 235 + { "eq_ana_bndy_bucket_30" , 0x10030108, EQ::eq_ana_bndy_bucket_30 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 236 + { "eq_ana_bndy_bucket_31" , 0x10030108, EQ::eq_ana_bndy_bucket_31 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 237 + { "eq_ana_bndy_bucket_32" , 0x10030108, EQ::eq_ana_bndy_bucket_32 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 238 + { "eq_ana_bndy_bucket_33" , 0x10030108, EQ::eq_ana_bndy_bucket_33 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 239 + { "eq_ana_bndy_bucket_34" , 0x10030108, EQ::eq_ana_bndy_bucket_34 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 240 + { "eq_ana_bndy_bucket_35" , 0x10030108, EQ::eq_ana_bndy_bucket_35 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 241 + { "eq_ana_bndy_bucket_36" , 0x10030108, EQ::eq_ana_bndy_bucket_36 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 242 + { "eq_ana_bndy_bucket_37" , 0x10030108, EQ::eq_ana_bndy_bucket_37 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 243 + { "eq_ana_bndy_bucket_38" , 0x10030108, EQ::eq_ana_bndy_bucket_38 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 244 + { "eq_ana_bndy_bucket_39" , 0x10030108, EQ::eq_ana_bndy_bucket_39 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 245 + { "eq_ana_bndy_bucket_40" , 0x10030108, EQ::eq_ana_bndy_bucket_40 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 246 + { "eq_ana_bndy_bucket_41" , 0x10030108, EQ::eq_ana_bndy_bucket_41 , EQ_TYPE , RCLS_EKB_FSM_RING }, // 247 + { "eq_inex_bucket_1" , 0x1003608B, EQ::eq_inex_bucket_1 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 248 + { "eq_inex_bucket_2" , 0x1003608B, EQ::eq_inex_bucket_2 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 249 + { "eq_inex_bucket_3" , 0x1003608B, EQ::eq_inex_bucket_3 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 250 + { "eq_inex_bucket_4" , 0x1003608B, EQ::eq_inex_bucket_4 , EQ_TYPE , RCLS_EKB_FLUSH_RING }, // 251 + { "ec_cmsk" , 0x2003700A, EC::ec_cmsk , EC_TYPE , RCLS_ROOT_RING | RCLS_EKB_CMSK_RING }, // 252 + { "perv_pll_bndy_flt_1" , 0x01030018, PERV::perv_pll_bndy_flt_1 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 253 + { "perv_pll_bndy_flt_2" , 0x01030018, PERV::perv_pll_bndy_flt_2 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 254 + { "perv_pll_bndy_flt_3" , 0x01030018, PERV::perv_pll_bndy_flt_3 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 255 + { "perv_pll_bndy_flt_4" , 0x01030018, PERV::perv_pll_bndy_flt_4 , PERV_TYPE, RCLS_EKB_NONFLUSH_RING }, // 256 + { "mc_omi0_fure" , 0x0703100F, MC::mc_omi0_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 257 + { "mc_omi0_gptr" , 0x07031002, MC::mc_omi0_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 258 + { "mc_omi1_fure" , 0x0703080F, MC::mc_omi1_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 259 + { "mc_omi1_gptr" , 0x07030802, MC::mc_omi1_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 260 + { "mc_omi2_fure" , 0x0703040F, MC::mc_omi2_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 261 + { "mc_omi2_gptr" , 0x07030402, MC::mc_omi2_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 262 + { "mc_omippe_fure" , 0x0703020F, MC::mc_omippe_fure , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_FLUSH_RING }, // 263 + { "mc_omippe_gptr" , 0x07030202, MC::mc_omippe_gptr , MC_TYPE , RCLS_ROOT_RING | RCLS_EKB_OVLY_RING }, // 264 + { "mc_omippe_time" , 0x07030207, MC::mc_omippe_time , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDG_RING }, // 265 + { "mc_omippe_repr" , 0x07030206, MC::mc_omippe_repr , MC_TYPE , RCLS_ROOT_RING | RCLS_MVPD_PDR_RING }, // 266 }; #endif #ifdef __PPE__ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] = { - { PERV::perv_fure , PERV_TYPE }, // 0 - { PERV::perv_gptr , PERV_TYPE }, // 1 - { PERV::perv_time , PERV_TYPE }, // 2 - { PERV::occ_fure , PERV_TYPE }, // 3 - { PERV::occ_gptr , PERV_TYPE }, // 4 - { PERV::occ_time , PERV_TYPE }, // 5 - { PERV::perv_ana_func , PERV_TYPE }, // 6 - { PERV::perv_ana_gptr , PERV_TYPE }, // 7 - { PERV::perv_pll_gptr , PERV_TYPE }, // 8 - { PERV::perv_pll_bndy , PERV_TYPE }, // 9 - { PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 10 - { PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 11 - { PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 12 - { PERV::perv_pll_bndy_bucket_4 , PERV_TYPE }, // 13 - { PERV::perv_pll_bndy_bucket_5 , PERV_TYPE }, // 14 - { PERV::perv_pll_func , PERV_TYPE }, // 15 - { PERV::perv_repr , PERV_TYPE }, // 16 - { PERV::occ_repr , PERV_TYPE }, // 17 - { PERV::sbe_fure , PERV_TYPE }, // 18 - { PERV::sbe_gptr , PERV_TYPE }, // 19 - { PERV::sbe_repr , PERV_TYPE }, // 20 - { N0::n0_fure , N0_TYPE }, // 21 - { N0::n0_gptr , N0_TYPE }, // 22 - { N0::n0_time , N0_TYPE }, // 23 - { N0::n0_nx_fure , N0_TYPE }, // 24 - { N0::n0_nx_gptr , N0_TYPE }, // 25 - { N0::n0_nx_time , N0_TYPE }, // 26 - { N0::n0_cxa0_fure , N0_TYPE }, // 27 - { N0::n0_cxa0_gptr , N0_TYPE }, // 28 - { N0::n0_cxa0_time , N0_TYPE }, // 29 - { N0::n0_repr , N0_TYPE }, // 30 - { N0::n0_nx_repr , N0_TYPE }, // 31 - { N0::n0_cxa0_repr , N0_TYPE }, // 32 - { N1::n1_fure , N1_TYPE }, // 33 - { N1::n1_gptr , N1_TYPE }, // 34 - { N1::n1_time , N1_TYPE }, // 35 - { N1::n1_ioo0_fure , N1_TYPE }, // 36 - { N1::n1_ioo0_gptr , N1_TYPE }, // 37 - { N1::n1_ioo0_time , N1_TYPE }, // 38 - { N1::n1_ioo1_fure , N1_TYPE }, // 39 - { N1::n1_ioo1_gptr , N1_TYPE }, // 40 - { N1::n1_ioo1_time , N1_TYPE }, // 41 - { N1::n1_mcs23_fure , N1_TYPE }, // 42 - { N1::n1_mcs23_gptr , N1_TYPE }, // 43 - { N1::n1_mcs23_time , N1_TYPE }, // 44 - { N1::n1_repr , N1_TYPE }, // 45 - { N1::n1_ioo0_repr , N1_TYPE }, // 46 - { N1::n1_ioo1_repr , N1_TYPE }, // 47 - { N1::n1_mcs23_repr , N1_TYPE }, // 48 - { N2::n2_fure , N2_TYPE }, // 49 - { N2::n2_gptr , N2_TYPE }, // 50 - { N2::n2_time , N2_TYPE }, // 51 - { N2::n2_cxa1_fure , N2_TYPE }, // 52 - { N2::n2_cxa1_gptr , N2_TYPE }, // 53 - { N2::n2_cxa1_time , N2_TYPE }, // 54 - { N2::n2_psi_fure , N2_TYPE }, // 55 - { N2::n2_psi_gptr , N2_TYPE }, // 56 - { N2::n2_psi_time , N2_TYPE }, // 57 - { N2::n2_repr , N2_TYPE }, // 58 - { N2::n2_cxa1_repr , N2_TYPE }, // 59 - { INVALID_RING_OFFSET , N2_TYPE }, // 60 - { INVALID_RING_OFFSET , N2_TYPE }, // 61 - { N3::n3_fure , N3_TYPE }, // 62 - { N3::n3_gptr , N3_TYPE }, // 63 - { N3::n3_time , N3_TYPE }, // 64 - { N3::n3_mcs01_fure , N3_TYPE }, // 65 - { N3::n3_mcs01_gptr , N3_TYPE }, // 66 - { N3::n3_mcs01_time , N3_TYPE }, // 67 - { N3::n3_np_fure , N3_TYPE }, // 68 - { N3::n3_np_gptr , N3_TYPE }, // 69 - { N3::n3_np_time , N3_TYPE }, // 70 - { N3::n3_repr , N3_TYPE }, // 71 - { N3::n3_mcs01_repr , N3_TYPE }, // 72 - { N3::n3_np_repr , N3_TYPE }, // 73 - { N3::n3_br_fure , N3_TYPE }, // 74 - { XB::xb_fure , XB_TYPE }, // 75 - { XB::xb_gptr , XB_TYPE }, // 76 - { XB::xb_time , XB_TYPE }, // 77 - { XB::xb_io0_fure , XB_TYPE }, // 78 - { XB::xb_io0_gptr , XB_TYPE }, // 79 - { XB::xb_io0_time , XB_TYPE }, // 80 - { XB::xb_io1_fure , XB_TYPE }, // 81 - { XB::xb_io1_gptr , XB_TYPE }, // 82 - { XB::xb_io1_time , XB_TYPE }, // 83 - { XB::xb_io2_fure , XB_TYPE }, // 84 - { XB::xb_io2_gptr , XB_TYPE }, // 85 - { XB::xb_io2_time , XB_TYPE }, // 86 - { XB::xb_pll_gptr , XB_TYPE }, // 87 - { XB::xb_pll_bndy , XB_TYPE }, // 88 - { XB::xb_pll_func , XB_TYPE }, // 89 - { XB::xb_repr , XB_TYPE }, // 90 - { XB::xb_io0_repr , XB_TYPE }, // 91 - { XB::xb_io1_repr , XB_TYPE }, // 92 - { XB::xb_io2_repr , XB_TYPE }, // 93 - { INVALID_RING_OFFSET , XB_TYPE }, // 94 - { INVALID_RING_OFFSET , XB_TYPE }, // 95 - { MC::mc_fure , MC_TYPE }, // 96 - { MC::mc_gptr , MC_TYPE }, // 97 - { MC::mc_time , MC_TYPE }, // 98 - { MC::mc_iom01_fure , MC_TYPE }, // 99 - { MC::mc_iom01_gptr , MC_TYPE }, // 100 - { MC::mc_iom01_time , MC_TYPE }, // 101 - { MC::mc_iom23_fure , MC_TYPE }, // 102 - { MC::mc_iom23_gptr , MC_TYPE }, // 103 - { MC::mc_iom23_time , MC_TYPE }, // 104 - { MC::mc_pll_gptr , MC_TYPE }, // 105 - { MC::mc_pll_bndy , MC_TYPE }, // 106 - { MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 107 - { MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 108 - { MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 109 - { MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 110 - { MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 111 - { MC::mc_pll_func , MC_TYPE }, // 112 - { MC::mc_repr , MC_TYPE }, // 113 - { INVALID_RING_OFFSET , MC_TYPE }, // 114 - { MC::mc_iom23_repr , MC_TYPE }, // 115 - { OB0::ob0_pll_bndy , OB0_TYPE }, // 116 - { OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE }, // 117 - { OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE }, // 118 - { OB0::ob0_gptr , OB0_TYPE }, // 119 - { OB0::ob0_time , OB0_TYPE }, // 120 - { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 - { OB0::ob0_fure , OB0_TYPE }, // 122 - { OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE }, // 123 - { OB0::ob0_repr , OB0_TYPE }, // 124 - { OB1::ob1_pll_bndy , OB1_TYPE }, // 125 - { OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE }, // 126 - { OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE }, // 127 - { OB1::ob1_gptr , OB1_TYPE }, // 128 - { OB1::ob1_time , OB1_TYPE }, // 129 - { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 - { OB1::ob1_fure , OB1_TYPE }, // 131 - { OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE }, // 132 - { OB1::ob1_repr , OB1_TYPE }, // 133 - { OB2::ob2_pll_bndy , OB2_TYPE }, // 134 - { OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE }, // 135 - { OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE }, // 136 - { OB2::ob2_gptr , OB2_TYPE }, // 137 - { OB2::ob2_time , OB2_TYPE }, // 138 - { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 - { OB2::ob2_fure , OB2_TYPE }, // 140 - { OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE }, // 141 - { OB2::ob2_repr , OB2_TYPE }, // 142 - { OB3::ob3_pll_bndy , OB3_TYPE }, // 143 - { OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE }, // 144 - { OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE }, // 145 - { OB3::ob3_gptr , OB3_TYPE }, // 146 - { OB3::ob3_time , OB3_TYPE }, // 147 - { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 - { OB3::ob3_fure , OB3_TYPE }, // 149 - { OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE }, // 150 - { OB3::ob3_repr , OB3_TYPE }, // 151 - { INVALID_RING_OFFSET , OB3_TYPE }, // 152 - { INVALID_RING_OFFSET , OB3_TYPE }, // 153 - { PCI0::pci0_fure , PCI0_TYPE }, // 154 - { PCI0::pci0_gptr , PCI0_TYPE }, // 155 - { PCI0::pci0_time , PCI0_TYPE }, // 156 - { PCI0::pci0_pll_bndy , PCI0_TYPE }, // 157 - { PCI0::pci0_pll_gptr , PCI0_TYPE }, // 158 - { PCI0::pci0_repr , PCI0_TYPE }, // 159 - { PCI1::pci1_fure , PCI1_TYPE }, // 160 - { PCI1::pci1_gptr , PCI1_TYPE }, // 161 - { PCI1::pci1_time , PCI1_TYPE }, // 162 - { PCI1::pci1_pll_bndy , PCI1_TYPE }, // 163 - { PCI1::pci1_pll_gptr , PCI1_TYPE }, // 164 - { PCI1::pci1_repr , PCI1_TYPE }, // 165 - { PCI2::pci2_fure , PCI2_TYPE }, // 166 - { PCI2::pci2_gptr , PCI2_TYPE }, // 167 - { PCI2::pci2_time , PCI2_TYPE }, // 168 - { PCI2::pci2_pll_bndy , PCI2_TYPE }, // 169 - { PCI2::pci2_pll_gptr , PCI2_TYPE }, // 170 - { PCI2::pci2_repr , PCI2_TYPE }, // 171 - { EQ::eq_fure , EQ_TYPE }, // 172 - { EQ::eq_gptr , EQ_TYPE }, // 173 - { EQ::eq_time , EQ_TYPE }, // 174 - { EQ::eq_inex , EQ_TYPE }, // 175 - { EQ::ex_l3_fure , EQ_TYPE }, // 176 - { EQ::ex_l3_gptr , EQ_TYPE }, // 177 - { EQ::ex_l3_time , EQ_TYPE }, // 178 - { EQ::ex_l2_mode , EQ_TYPE }, // 179 - { EQ::ex_l2_fure , EQ_TYPE }, // 180 - { EQ::ex_l2_gptr , EQ_TYPE }, // 181 - { EQ::ex_l2_time , EQ_TYPE }, // 182 - { EQ::ex_l3_refr_fure , EQ_TYPE }, // 183 - { EQ::ex_l3_refr_gptr , EQ_TYPE }, // 184 - { EQ::ex_l3_refr_time , EQ_TYPE }, // 185 - { EQ::eq_ana_func , EQ_TYPE }, // 186 - { EQ::eq_ana_gptr , EQ_TYPE }, // 187 - { EQ::eq_dpll_func , EQ_TYPE }, // 188 - { EQ::eq_dpll_gptr , EQ_TYPE }, // 189 - { EQ::eq_dpll_mode , EQ_TYPE }, // 190 - { EQ::eq_ana_bndy , EQ_TYPE }, // 191 - { EQ::eq_ana_bndy_bucket_0 , EQ_TYPE }, // 192 - { EQ::eq_ana_bndy_bucket_1 , EQ_TYPE }, // 193 - { EQ::eq_ana_bndy_bucket_2 , EQ_TYPE }, // 194 - { EQ::eq_ana_bndy_bucket_3 , EQ_TYPE }, // 195 - { EQ::eq_ana_bndy_bucket_4 , EQ_TYPE }, // 196 - { EQ::eq_ana_bndy_bucket_5 , EQ_TYPE }, // 197 - { EQ::eq_ana_bndy_bucket_6 , EQ_TYPE }, // 198 - { EQ::eq_ana_bndy_bucket_7 , EQ_TYPE }, // 199 - { EQ::eq_ana_bndy_bucket_8 , EQ_TYPE }, // 200 - { EQ::eq_ana_bndy_bucket_9 , EQ_TYPE }, // 201 - { EQ::eq_ana_bndy_bucket_10 , EQ_TYPE }, // 202 - { EQ::eq_ana_bndy_bucket_11 , EQ_TYPE }, // 203 - { EQ::eq_ana_bndy_bucket_12 , EQ_TYPE }, // 204 - { EQ::eq_ana_bndy_bucket_13 , EQ_TYPE }, // 205 - { EQ::eq_ana_bndy_bucket_14 , EQ_TYPE }, // 206 - { EQ::eq_ana_bndy_bucket_15 , EQ_TYPE }, // 207 - { EQ::eq_ana_bndy_bucket_16 , EQ_TYPE }, // 208 - { EQ::eq_ana_bndy_bucket_17 , EQ_TYPE }, // 209 - { EQ::eq_ana_bndy_bucket_18 , EQ_TYPE }, // 210 - { EQ::eq_ana_bndy_bucket_19 , EQ_TYPE }, // 211 - { EQ::eq_ana_bndy_bucket_20 , EQ_TYPE }, // 212 - { EQ::eq_ana_bndy_bucket_21 , EQ_TYPE }, // 213 - { EQ::eq_ana_bndy_bucket_22 , EQ_TYPE }, // 214 - { EQ::eq_ana_bndy_bucket_23 , EQ_TYPE }, // 215 - { EQ::eq_ana_bndy_bucket_24 , EQ_TYPE }, // 216 - { EQ::eq_ana_bndy_bucket_25 , EQ_TYPE }, // 217 - { EQ::eq_ana_bndy_bucket_l3dcc , EQ_TYPE }, // 218 - { EQ::eq_ana_mode , EQ_TYPE }, // 219 - { EQ::eq_repr , EQ_TYPE }, // 220 - { EQ::ex_l3_repr , EQ_TYPE }, // 221 - { EQ::ex_l2_repr , EQ_TYPE }, // 222 - { EQ::ex_l3_refr_repr , EQ_TYPE }, // 223 - { EC::ec_func , EC_TYPE }, // 224 - { EC::ec_gptr , EC_TYPE }, // 225 - { EC::ec_time , EC_TYPE }, // 226 - { EC::ec_mode , EC_TYPE }, // 227 - { EC::ec_repr , EC_TYPE }, // 228 - { INVALID_RING_OFFSET , EQ_TYPE }, // 229 - { INVALID_RING_OFFSET , EQ_TYPE }, // 230 - { EC::ec_abst , EC_TYPE }, // 231 - { EQ::eq_ana_bndy_bucket_26 , EQ_TYPE }, // 232 - { EQ::eq_ana_bndy_bucket_27 , EQ_TYPE }, // 233 - { EQ::eq_ana_bndy_bucket_28 , EQ_TYPE }, // 234 - { EQ::eq_ana_bndy_bucket_29 , EQ_TYPE }, // 235 - { EQ::eq_ana_bndy_bucket_30 , EQ_TYPE }, // 236 - { EQ::eq_ana_bndy_bucket_31 , EQ_TYPE }, // 237 - { EQ::eq_ana_bndy_bucket_32 , EQ_TYPE }, // 238 - { EQ::eq_ana_bndy_bucket_33 , EQ_TYPE }, // 239 - { EQ::eq_ana_bndy_bucket_34 , EQ_TYPE }, // 240 - { EQ::eq_ana_bndy_bucket_35 , EQ_TYPE }, // 241 - { EQ::eq_ana_bndy_bucket_36 , EQ_TYPE }, // 242 - { EQ::eq_ana_bndy_bucket_37 , EQ_TYPE }, // 243 - { EQ::eq_ana_bndy_bucket_38 , EQ_TYPE }, // 244 - { EQ::eq_ana_bndy_bucket_39 , EQ_TYPE }, // 245 - { EQ::eq_ana_bndy_bucket_40 , EQ_TYPE }, // 246 - { EQ::eq_ana_bndy_bucket_41 , EQ_TYPE }, // 247 - { EQ::eq_inex_bucket_1 , EQ_TYPE }, // 248 - { EQ::eq_inex_bucket_2 , EQ_TYPE }, // 249 - { EQ::eq_inex_bucket_3 , EQ_TYPE }, // 250 - { EQ::eq_inex_bucket_4 , EQ_TYPE }, // 251 - { EC::ec_cmsk , EC_TYPE }, // 252 - { PERV::perv_pll_bndy_flt_1 , PERV_TYPE }, // 253 - { PERV::perv_pll_bndy_flt_2 , PERV_TYPE }, // 254 - { PERV::perv_pll_bndy_flt_3 , PERV_TYPE }, // 255 - { PERV::perv_pll_bndy_flt_4 , PERV_TYPE }, // 256 - { MC::mc_omi0_fure , MC_TYPE }, // 257 - { MC::mc_omi0_gptr , MC_TYPE }, // 258 - { MC::mc_omi1_fure , MC_TYPE }, // 259 - { MC::mc_omi1_gptr , MC_TYPE }, // 260 - { MC::mc_omi2_fure , MC_TYPE }, // 261 - { MC::mc_omi2_gptr , MC_TYPE }, // 262 - { MC::mc_omippe_fure , MC_TYPE }, // 263 - { MC::mc_omippe_gptr , MC_TYPE }, // 264 - { MC::mc_omippe_time , MC_TYPE }, // 265 - { MC::mc_omippe_repr , MC_TYPE }, // 266 + { PERV::perv_fure , PERV_TYPE }, // 0 + { PERV::perv_gptr , PERV_TYPE }, // 1 + { PERV::perv_time , PERV_TYPE }, // 2 + { PERV::occ_fure , PERV_TYPE }, // 3 + { PERV::occ_gptr , PERV_TYPE }, // 4 + { PERV::occ_time , PERV_TYPE }, // 5 + { PERV::perv_ana_func , PERV_TYPE }, // 6 + { PERV::perv_ana_gptr , PERV_TYPE }, // 7 + { PERV::perv_pll_gptr , PERV_TYPE }, // 8 + { PERV::perv_pll_bndy , PERV_TYPE }, // 9 + { PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 10 + { PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 11 + { PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 12 + { PERV::perv_pll_bndy_bucket_4 , PERV_TYPE }, // 13 + { PERV::perv_pll_bndy_bucket_5 , PERV_TYPE }, // 14 + { PERV::perv_pll_func , PERV_TYPE }, // 15 + { PERV::perv_repr , PERV_TYPE }, // 16 + { PERV::occ_repr , PERV_TYPE }, // 17 + { PERV::sbe_fure , PERV_TYPE }, // 18 + { PERV::sbe_gptr , PERV_TYPE }, // 19 + { PERV::sbe_repr , PERV_TYPE }, // 20 + { N0::n0_fure , N0_TYPE }, // 21 + { N0::n0_gptr , N0_TYPE }, // 22 + { N0::n0_time , N0_TYPE }, // 23 + { N0::n0_nx_fure , N0_TYPE }, // 24 + { N0::n0_nx_gptr , N0_TYPE }, // 25 + { N0::n0_nx_time , N0_TYPE }, // 26 + { N0::n0_cxa0_fure , N0_TYPE }, // 27 + { N0::n0_cxa0_gptr , N0_TYPE }, // 28 + { N0::n0_cxa0_time , N0_TYPE }, // 29 + { N0::n0_repr , N0_TYPE }, // 30 + { N0::n0_nx_repr , N0_TYPE }, // 31 + { N0::n0_cxa0_repr , N0_TYPE }, // 32 + { N1::n1_fure , N1_TYPE }, // 33 + { N1::n1_gptr , N1_TYPE }, // 34 + { N1::n1_time , N1_TYPE }, // 35 + { N1::n1_ioo0_fure , N1_TYPE }, // 36 + { N1::n1_ioo0_gptr , N1_TYPE }, // 37 + { N1::n1_ioo0_time , N1_TYPE }, // 38 + { N1::n1_ioo1_fure , N1_TYPE }, // 39 + { N1::n1_ioo1_gptr , N1_TYPE }, // 40 + { N1::n1_ioo1_time , N1_TYPE }, // 41 + { N1::n1_mcs23_fure , N1_TYPE }, // 42 + { N1::n1_mcs23_gptr , N1_TYPE }, // 43 + { N1::n1_mcs23_time , N1_TYPE }, // 44 + { N1::n1_repr , N1_TYPE }, // 45 + { N1::n1_ioo0_repr , N1_TYPE }, // 46 + { N1::n1_ioo1_repr , N1_TYPE }, // 47 + { N1::n1_mcs23_repr , N1_TYPE }, // 48 + { N2::n2_fure , N2_TYPE }, // 49 + { N2::n2_gptr , N2_TYPE }, // 50 + { N2::n2_time , N2_TYPE }, // 51 + { N2::n2_cxa1_fure , N2_TYPE }, // 52 + { N2::n2_cxa1_gptr , N2_TYPE }, // 53 + { N2::n2_cxa1_time , N2_TYPE }, // 54 + { N2::n2_psi_fure , N2_TYPE }, // 55 + { N2::n2_psi_gptr , N2_TYPE }, // 56 + { N2::n2_psi_time , N2_TYPE }, // 57 + { N2::n2_repr , N2_TYPE }, // 58 + { N2::n2_cxa1_repr , N2_TYPE }, // 59 + { INVALID_RING_OFFSET , N2_TYPE }, // 60 + { INVALID_RING_OFFSET , N2_TYPE }, // 61 + { N3::n3_fure , N3_TYPE }, // 62 + { N3::n3_gptr , N3_TYPE }, // 63 + { N3::n3_time , N3_TYPE }, // 64 + { N3::n3_mcs01_fure , N3_TYPE }, // 65 + { N3::n3_mcs01_gptr , N3_TYPE }, // 66 + { N3::n3_mcs01_time , N3_TYPE }, // 67 + { N3::n3_np_fure , N3_TYPE }, // 68 + { N3::n3_np_gptr , N3_TYPE }, // 69 + { N3::n3_np_time , N3_TYPE }, // 70 + { N3::n3_repr , N3_TYPE }, // 71 + { N3::n3_mcs01_repr , N3_TYPE }, // 72 + { N3::n3_np_repr , N3_TYPE }, // 73 + { N3::n3_br_fure , N3_TYPE }, // 74 + { XB::xb_fure , XB_TYPE }, // 75 + { XB::xb_gptr , XB_TYPE }, // 76 + { XB::xb_time , XB_TYPE }, // 77 + { XB::xb_io0_fure , XB_TYPE }, // 78 + { XB::xb_io0_gptr , XB_TYPE }, // 79 + { XB::xb_io0_time , XB_TYPE }, // 80 + { XB::xb_io1_fure , XB_TYPE }, // 81 + { XB::xb_io1_gptr , XB_TYPE }, // 82 + { XB::xb_io1_time , XB_TYPE }, // 83 + { XB::xb_io2_fure , XB_TYPE }, // 84 + { XB::xb_io2_gptr , XB_TYPE }, // 85 + { XB::xb_io2_time , XB_TYPE }, // 86 + { XB::xb_pll_gptr , XB_TYPE }, // 87 + { XB::xb_pll_bndy , XB_TYPE }, // 88 + { XB::xb_pll_func , XB_TYPE }, // 89 + { XB::xb_repr , XB_TYPE }, // 90 + { XB::xb_io0_repr , XB_TYPE }, // 91 + { XB::xb_io1_repr , XB_TYPE }, // 92 + { XB::xb_io2_repr , XB_TYPE }, // 93 + { INVALID_RING_OFFSET , XB_TYPE }, // 94 + { INVALID_RING_OFFSET , XB_TYPE }, // 95 + { MC::mc_fure , MC_TYPE }, // 96 + { MC::mc_gptr , MC_TYPE }, // 97 + { MC::mc_time , MC_TYPE }, // 98 + { MC::mc_iom01_fure , MC_TYPE }, // 99 + { MC::mc_iom01_gptr , MC_TYPE }, // 100 + { MC::mc_iom01_time , MC_TYPE }, // 101 + { MC::mc_iom23_fure , MC_TYPE }, // 102 + { MC::mc_iom23_gptr , MC_TYPE }, // 103 + { MC::mc_iom23_time , MC_TYPE }, // 104 + { MC::mc_pll_gptr , MC_TYPE }, // 105 + { MC::mc_pll_bndy , MC_TYPE }, // 106 + { MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 107 + { MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 108 + { MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 109 + { MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 110 + { MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 111 + { MC::mc_pll_func , MC_TYPE }, // 112 + { MC::mc_repr , MC_TYPE }, // 113 + { INVALID_RING_OFFSET , MC_TYPE }, // 114 + { MC::mc_iom23_repr , MC_TYPE }, // 115 + { OB0::ob0_pll_bndy , OB0_TYPE }, // 116 + { OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE }, // 117 + { OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE }, // 118 + { OB0::ob0_gptr , OB0_TYPE }, // 119 + { OB0::ob0_time , OB0_TYPE }, // 120 + { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 + { OB0::ob0_fure , OB0_TYPE }, // 122 + { OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE }, // 123 + { OB0::ob0_repr , OB0_TYPE }, // 124 + { OB1::ob1_pll_bndy , OB1_TYPE }, // 125 + { OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE }, // 126 + { OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE }, // 127 + { OB1::ob1_gptr , OB1_TYPE }, // 128 + { OB1::ob1_time , OB1_TYPE }, // 129 + { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 + { OB1::ob1_fure , OB1_TYPE }, // 131 + { OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE }, // 132 + { OB1::ob1_repr , OB1_TYPE }, // 133 + { OB2::ob2_pll_bndy , OB2_TYPE }, // 134 + { OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE }, // 135 + { OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE }, // 136 + { OB2::ob2_gptr , OB2_TYPE }, // 137 + { OB2::ob2_time , OB2_TYPE }, // 138 + { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 + { OB2::ob2_fure , OB2_TYPE }, // 140 + { OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE }, // 141 + { OB2::ob2_repr , OB2_TYPE }, // 142 + { OB3::ob3_pll_bndy , OB3_TYPE }, // 143 + { OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE }, // 144 + { OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE }, // 145 + { OB3::ob3_gptr , OB3_TYPE }, // 146 + { OB3::ob3_time , OB3_TYPE }, // 147 + { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 + { OB3::ob3_fure , OB3_TYPE }, // 149 + { OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE }, // 150 + { OB3::ob3_repr , OB3_TYPE }, // 151 + { INVALID_RING_OFFSET , OB3_TYPE }, // 152 + { INVALID_RING_OFFSET , OB3_TYPE }, // 153 + { PCI0::pci0_fure , PCI0_TYPE }, // 154 + { PCI0::pci0_gptr , PCI0_TYPE }, // 155 + { PCI0::pci0_time , PCI0_TYPE }, // 156 + { PCI0::pci0_pll_bndy , PCI0_TYPE }, // 157 + { PCI0::pci0_pll_gptr , PCI0_TYPE }, // 158 + { PCI0::pci0_repr , PCI0_TYPE }, // 159 + { PCI1::pci1_fure , PCI1_TYPE }, // 160 + { PCI1::pci1_gptr , PCI1_TYPE }, // 161 + { PCI1::pci1_time , PCI1_TYPE }, // 162 + { PCI1::pci1_pll_bndy , PCI1_TYPE }, // 163 + { PCI1::pci1_pll_gptr , PCI1_TYPE }, // 164 + { PCI1::pci1_repr , PCI1_TYPE }, // 165 + { PCI2::pci2_fure , PCI2_TYPE }, // 166 + { PCI2::pci2_gptr , PCI2_TYPE }, // 167 + { PCI2::pci2_time , PCI2_TYPE }, // 168 + { PCI2::pci2_pll_bndy , PCI2_TYPE }, // 169 + { PCI2::pci2_pll_gptr , PCI2_TYPE }, // 170 + { PCI2::pci2_repr , PCI2_TYPE }, // 171 + { EQ::eq_fure , EQ_TYPE }, // 172 + { EQ::eq_gptr , EQ_TYPE }, // 173 + { EQ::eq_time , EQ_TYPE }, // 174 + { EQ::eq_inex , EQ_TYPE }, // 175 + { EQ::ex_l3_fure , EQ_TYPE }, // 176 + { EQ::ex_l3_gptr , EQ_TYPE }, // 177 + { EQ::ex_l3_time , EQ_TYPE }, // 178 + { EQ::ex_l2_mode , EQ_TYPE }, // 179 + { EQ::ex_l2_fure , EQ_TYPE }, // 180 + { EQ::ex_l2_gptr , EQ_TYPE }, // 181 + { EQ::ex_l2_time , EQ_TYPE }, // 182 + { EQ::ex_l3_refr_fure , EQ_TYPE }, // 183 + { EQ::ex_l3_refr_gptr , EQ_TYPE }, // 184 + { EQ::ex_l3_refr_time , EQ_TYPE }, // 185 + { EQ::eq_ana_func , EQ_TYPE }, // 186 + { EQ::eq_ana_gptr , EQ_TYPE }, // 187 + { EQ::eq_dpll_func , EQ_TYPE }, // 188 + { EQ::eq_dpll_gptr , EQ_TYPE }, // 189 + { EQ::eq_dpll_mode , EQ_TYPE }, // 190 + { EQ::eq_ana_bndy , EQ_TYPE }, // 191 + { EQ::eq_ana_bndy_bucket_0 , EQ_TYPE }, // 192 + { EQ::eq_ana_bndy_bucket_1 , EQ_TYPE }, // 193 + { EQ::eq_ana_bndy_bucket_2 , EQ_TYPE }, // 194 + { EQ::eq_ana_bndy_bucket_3 , EQ_TYPE }, // 195 + { EQ::eq_ana_bndy_bucket_4 , EQ_TYPE }, // 196 + { EQ::eq_ana_bndy_bucket_5 , EQ_TYPE }, // 197 + { EQ::eq_ana_bndy_bucket_6 , EQ_TYPE }, // 198 + { EQ::eq_ana_bndy_bucket_7 , EQ_TYPE }, // 199 + { EQ::eq_ana_bndy_bucket_8 , EQ_TYPE }, // 200 + { EQ::eq_ana_bndy_bucket_9 , EQ_TYPE }, // 201 + { EQ::eq_ana_bndy_bucket_10 , EQ_TYPE }, // 202 + { EQ::eq_ana_bndy_bucket_11 , EQ_TYPE }, // 203 + { EQ::eq_ana_bndy_bucket_12 , EQ_TYPE }, // 204 + { EQ::eq_ana_bndy_bucket_13 , EQ_TYPE }, // 205 + { EQ::eq_ana_bndy_bucket_14 , EQ_TYPE }, // 206 + { EQ::eq_ana_bndy_bucket_15 , EQ_TYPE }, // 207 + { EQ::eq_ana_bndy_bucket_16 , EQ_TYPE }, // 208 + { EQ::eq_ana_bndy_bucket_17 , EQ_TYPE }, // 209 + { EQ::eq_ana_bndy_bucket_18 , EQ_TYPE }, // 210 + { EQ::eq_ana_bndy_bucket_19 , EQ_TYPE }, // 211 + { EQ::eq_ana_bndy_bucket_20 , EQ_TYPE }, // 212 + { EQ::eq_ana_bndy_bucket_21 , EQ_TYPE }, // 213 + { EQ::eq_ana_bndy_bucket_22 , EQ_TYPE }, // 214 + { EQ::eq_ana_bndy_bucket_23 , EQ_TYPE }, // 215 + { EQ::eq_ana_bndy_bucket_24 , EQ_TYPE }, // 216 + { EQ::eq_ana_bndy_bucket_25 , EQ_TYPE }, // 217 + { EQ::eq_ana_bndy_bucket_l3dcc , EQ_TYPE }, // 218 + { EQ::eq_ana_mode , EQ_TYPE }, // 219 + { EQ::eq_repr , EQ_TYPE }, // 220 + { EQ::ex_l3_repr , EQ_TYPE }, // 221 + { EQ::ex_l2_repr , EQ_TYPE }, // 222 + { EQ::ex_l3_refr_repr , EQ_TYPE }, // 223 + { EC::ec_func , EC_TYPE }, // 224 + { EC::ec_gptr , EC_TYPE }, // 225 + { EC::ec_time , EC_TYPE }, // 226 + { EC::ec_mode , EC_TYPE }, // 227 + { EC::ec_repr , EC_TYPE }, // 228 + { INVALID_RING_OFFSET , EQ_TYPE }, // 229 + { INVALID_RING_OFFSET , EQ_TYPE }, // 230 + { EC::ec_abst , EC_TYPE }, // 231 + { EQ::eq_ana_bndy_bucket_26 , EQ_TYPE }, // 232 + { EQ::eq_ana_bndy_bucket_27 , EQ_TYPE }, // 233 + { EQ::eq_ana_bndy_bucket_28 , EQ_TYPE }, // 234 + { EQ::eq_ana_bndy_bucket_29 , EQ_TYPE }, // 235 + { EQ::eq_ana_bndy_bucket_30 , EQ_TYPE }, // 236 + { EQ::eq_ana_bndy_bucket_31 , EQ_TYPE }, // 237 + { EQ::eq_ana_bndy_bucket_32 , EQ_TYPE }, // 238 + { EQ::eq_ana_bndy_bucket_33 , EQ_TYPE }, // 239 + { EQ::eq_ana_bndy_bucket_34 , EQ_TYPE }, // 240 + { EQ::eq_ana_bndy_bucket_35 , EQ_TYPE }, // 241 + { EQ::eq_ana_bndy_bucket_36 , EQ_TYPE }, // 242 + { EQ::eq_ana_bndy_bucket_37 , EQ_TYPE }, // 243 + { EQ::eq_ana_bndy_bucket_38 , EQ_TYPE }, // 244 + { EQ::eq_ana_bndy_bucket_39 , EQ_TYPE }, // 245 + { EQ::eq_ana_bndy_bucket_40 , EQ_TYPE }, // 246 + { EQ::eq_ana_bndy_bucket_41 , EQ_TYPE }, // 247 + { EQ::eq_inex_bucket_1 , EQ_TYPE }, // 248 + { EQ::eq_inex_bucket_2 , EQ_TYPE }, // 249 + { EQ::eq_inex_bucket_3 , EQ_TYPE }, // 250 + { EQ::eq_inex_bucket_4 , EQ_TYPE }, // 251 + { EC::ec_cmsk , EC_TYPE }, // 252 + { PERV::perv_pll_bndy_flt_1 , PERV_TYPE }, // 253 + { PERV::perv_pll_bndy_flt_2 , PERV_TYPE }, // 254 + { PERV::perv_pll_bndy_flt_3 , PERV_TYPE }, // 255 + { PERV::perv_pll_bndy_flt_4 , PERV_TYPE }, // 256 + { MC::mc_omi0_fure , MC_TYPE }, // 257 + { MC::mc_omi0_gptr , MC_TYPE }, // 258 + { MC::mc_omi1_fure , MC_TYPE }, // 259 + { MC::mc_omi1_gptr , MC_TYPE }, // 260 + { MC::mc_omi2_fure , MC_TYPE }, // 261 + { MC::mc_omi2_gptr , MC_TYPE }, // 262 + { MC::mc_omippe_fure , MC_TYPE }, // 263 + { MC::mc_omippe_gptr , MC_TYPE }, // 264 + { MC::mc_omippe_time , MC_TYPE }, // 265 + { MC::mc_omippe_repr , MC_TYPE }, // 266 }; #endif -// Returns our own chiplet enum value for this ringId -ChipletType_t -ringid_get_chiplet(RingId_t i_ringId); - -// Returns data structures defined for chiplet type -// as determined by ringId +// Returns data structure assocated with chipletType void ringid_get_chiplet_properties( ChipletType_t i_chipletType, - ChipletData_t** o_cpltData, - GenRingIdList** o_ringComm, - GenRingIdList** o_ringInst, - RingVariantOrder** o_varOrder, - uint8_t* o_numVariants); - -// Returns properties of a ring as determined by ringId -GenRingIdList* -_ringid_get_ring_list(RingId_t i_ringId); + ChipletData_t** o_chipletData); #endif diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.C b/src/import/chips/p9/utils/imageProcs/p9_tor.C index 143c5c7ba..44bf731e0 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.C +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.C @@ -51,245 +51,287 @@ int get_ring_from_ring_section( void* i_ringSection, // Ring secti uint32_t i_dbgl ) // Debug option { int rc = TOR_SUCCESS; - uint8_t iInst, iRing, iVariant; TorHeader_t* torHeader; uint32_t torMagic; uint8_t torVersion; - uint8_t chipType; + ChipId_t chipId; TorCpltBlock_t* cpltBlock; TorCpltOffset_t cpltOffset; // Offset from ringSection to chiplet section TorRingOffset_t ringOffset; // Offset to actual ring container uint32_t torSlotNum; // TOR slot number (within a chiplet section) uint32_t ringSize; // Size of whole ring container/block. - RingVariantOrder* ringVariantOrder; + RingVariant_t* ringVariantOrder; RingId_t numRings; - GenRingIdList* ringIdListCommon; - GenRingIdList* ringIdListInstance; - GenRingIdList* ringIdList; - uint8_t bInstCase = 0; - ChipletData_t* cpltData; + ChipletType_t chipletType = UNDEFINED_CHIPLET_TYPE; + ChipletType_t chipletIndex = UNDEFINED_CHIPLET_TYPE; // Effective chiplet index + MyBool_t bInstCase = UNDEFINED_BOOLEAN; + ChipletData_t* chipletData; + uint8_t numInstances; uint8_t numVariants; - ChipletType_t numChiplets; - RingProperties_t* ringProps; + RingProperties_t* ringProps = NULL; + uint8_t idxRingEff; // Effective chiplet ring index + uint8_t iInst, iRing, iVariant; // Index counters for instance, chiplet rings, variant torHeader = (TorHeader_t*)i_ringSection; torMagic = be32toh(torHeader->magic); torVersion = torHeader->version; - chipType = torHeader->chipType; + chipId = torHeader->chipId; - rc = ringid_get_noof_chiplets( chipType, - torMagic, - &numChiplets); + // + // Get main ring properties list for the chip ID + // + rc = ringid_get_ringProps( chipId, + &ringProps ); + + if (rc) + { + MY_ERR("ringid_get_ringProps() failed w/rc=0x%08x\n", rc); + return rc; + } + + chipletType = ringProps[i_ringId].chipletType; + + // + // Get all other metadata for the chipletType + // + rc = ringid_get_chipletProps( chipId, + torMagic, + torHeader->version, + chipletType, + &chipletData, + &numVariants ); if (rc) { - MY_ERR("ringid_get_noof_chiplets() failed w/rc=0x%08x\n", rc); + MY_ERR("ringid_get_chipletProps() failed w/rc=0x%08x\n", rc); return rc; } + ringVariantOrder = chipletData->ringVariantOrder; + // - // Looper for each SBE chipleti + // Check the scope of chipletType and Get the effective chipletType's index // - for (ChipletType_t iCplt = 0; iCplt < numChiplets; iCplt++) + rc = ringid_get_chipletIndex( chipId, + torMagic, + chipletType, + &chipletIndex ); + + if (rc) { - rc = ringid_get_properties( chipType, - torMagic, - torHeader->version, - iCplt, - &cpltData, - &ringIdListCommon, - &ringIdListInstance, - &ringVariantOrder, - &ringProps, - &numVariants ); - - if (rc) + if ( rc == TOR_INVALID_CHIPLET_TYPE ) { - MY_ERR("ringid_get_properties() failed w/rc=0x%08x\n", rc); + // Many things could have lead to this error. It's not necessarily fatal or even + // unacceptable. For example, xip_tool will hit this one a lot, so we can't trace + // out here. Instead, for now, we're just returning TOR_INVALID_CHIPLET_TYPE. + // But maybe this needs to change in future. return rc; } - - // - // Sequentially traverse ring offset slots within a chiplet's CMN or INST section - // - for ( bInstCase = 0; bInstCase <= 1; bInstCase++ ) + else { - numRings = bInstCase ? cpltData->iv_num_instance_rings : cpltData->iv_num_common_rings; - ringIdList = bInstCase ? ringIdListInstance : ringIdListCommon; + MY_ERR("ringid_get_chipletIndex() failed w/rc=0x%08x\n", rc); + return rc; + } + } - // Adjust number of variants according to TOR version of image - if (torVersion < 7) - { - // Nothing to do. Number of variants is the same for Common and Instance rings. - } - else - { - numVariants = bInstCase ? 1 : numVariants; // Only BASE variant for Instance rings - } + // + // Determine whether Common or Instance section based on the INSTANCE_RING_MARK + // + if ( ringProps[i_ringId].idxRing & INSTANCE_RING_MARK ) + { + bInstCase = 1; + } + else + { + bInstCase = 0; + } + + // + // Calculate various loop upper limits + // + numInstances = bInstCase ? + chipletData->numChipletInstances : + 1; + + numRings = bInstCase ? + chipletData->numInstanceRings : + chipletData->numCommonRings; - if (ringIdList) // Only proceed if chiplet has [Common/Instance] rings. + idxRingEff = ringProps[i_ringId].idxRing & INSTANCE_RING_MASK; // Always safe + + // Adjust number of variants according to TOR version of image + if (torVersion < 7) + { + // Nothing to do. Number of variants is the same for Common and Instance rings. + } + else + { + numVariants = bInstCase ? + 1 : // Only BASE variant for Instance rings + numVariants; + } + + // Unless we find a ring, then the following rc will be returned + rc = TOR_RING_HAS_NO_TOR_SLOT; + + // + // Now traverse the chiplet's Common or Instance ring section + // + if (numRings) // Only proceed if chiplet has [Common/Instance] rings. + { + // Calc offset to chiplet's CMN or INST section, cpltOffset (steps 1-3) + // + // 1. Calc offset to TOR slot pointing to chiplet's COM or INST section + cpltOffset = sizeof(TorHeader_t) + + chipletIndex * sizeof(TorCpltBlock_t) + + bInstCase * sizeof(cpltBlock->cmnOffset); + // 2. Retrive offset, endian convert and make it relative to ring section origin + cpltOffset = *(uint32_t*)( (uint8_t*)i_ringSection + cpltOffset ); + cpltOffset = be32toh(cpltOffset); + // 3. Make offset relative to ring section origin + cpltOffset = sizeof(TorHeader_t) + cpltOffset; + + torSlotNum = 0; + + for ( iInst = 0; iInst < numInstances; iInst++ ) + { + for ( iRing = 0; iRing < numRings; iRing++ ) { - // Calc offset to chiplet's CMN or INST section, cpltOffset (steps 1-3) - // - // 1. Calc offset to TOR slot pointing to chiplet's COM or INST section - cpltOffset = sizeof(TorHeader_t) + - iCplt * sizeof(TorCpltBlock_t) + - bInstCase * sizeof(cpltBlock->cmnOffset); - // 2. Retrive offset, endian convert and make it relative to ring section origin - cpltOffset = *(uint32_t*)( (uint8_t*)i_ringSection + cpltOffset ); - cpltOffset = be32toh(cpltOffset); - // 3. Make offset relative to ring section origin - cpltOffset = sizeof(TorHeader_t) + cpltOffset; - - torSlotNum = 0; - - for ( iInst = ringIdList->instanceIdMin; - iInst <= ringIdList->instanceIdMax; - iInst++ ) + for ( iVariant = 0; iVariant < numVariants; iVariant++ ) { - for ( iRing = 0; iRing < numRings; iRing++ ) + if ( idxRingEff == iRing && // We're already in the right chiplet here! + ( i_ringVariant == ringVariantOrder[iVariant] || + // Support overrides etc where ringVariant doesn't necessarily apply + ( numVariants == 1 && i_ringVariant == UNDEFINED_RING_VARIANT ) ) && + ( !bInstCase || ( bInstCase && iInst == (io_instanceId - chipletData->chipletBaseId) ) ) ) { - for ( iVariant = 0; iVariant < numVariants; iVariant++ ) - { - if ( strcmp( (ringIdList + iRing)->ringName, - ringProps[i_ringId].iv_name ) == 0 && - ( i_ringVariant == ringVariantOrder->variant[iVariant] || - numVariants == 1 ) && // If no variants, ignore i_ringVariant and assume "BASE" ring - ( !bInstCase || ( bInstCase && iInst == io_instanceId ) ) ) - { - strcpy(o_ringName, (ringIdList + iRing)->ringName); + strcpy(o_ringName, ringProps[i_ringId].ringName); - // Calc offset to actual ring, ringOffset (steps 1-3) - // - // 1. Calc offset to TOR slot pointing to actual ring - ringOffset = cpltOffset + torSlotNum * sizeof(ringOffset); - // 2. Retrieve offset and endian convert - ringOffset = *(TorRingOffset_t*)( (uint8_t*)i_ringSection + ringOffset ); - ringOffset = be16toh(ringOffset); + // Calc offset to actual ring, ringOffset (steps 1-3) + // + // 1. Calc offset to TOR slot pointing to actual ring + ringOffset = cpltOffset + torSlotNum * sizeof(ringOffset); + // 2. Retrieve offset and endian convert + ringOffset = *(TorRingOffset_t*)( (uint8_t*)i_ringSection + ringOffset ); + ringOffset = be16toh(ringOffset); - if (i_ringBlockType == GET_SINGLE_RING) - { - ringSize = 0; + if (i_ringBlockType == GET_SINGLE_RING) + { + ringSize = 0; - if (ringOffset) - { - // 3. Make offset relative to ring section origin - ringOffset = cpltOffset + ringOffset; - - ringSize = be16toh( ((CompressedScanData*) - ((uint8_t*)i_ringSection + ringOffset))->iv_size ); - - if (io_ringBlockSize == 0) - { - if (i_dbgl > 0) - { - MY_DBG("io_ringBlockSize is zero. Returning required size.\n"); - } - - io_ringBlockSize = ringSize; - return TOR_SUCCESS; - } - - if (io_ringBlockSize < ringSize) - { - MY_ERR("io_ringBlockSize is less than required size.\n"); - return TOR_BUFFER_TOO_SMALL; - } - - // Produce return parms - memcpy( *io_ringBlockPtr, (uint8_t*)i_ringSection + ringOffset, ringSize); - io_ringBlockSize = ringSize; - io_instanceId = (bInstCase) ? io_instanceId : (ringIdList + iRing)->instanceIdMin; - - if (i_dbgl > 0) - { - MY_DBG("Found a ring:\n" \ - " Name: %s\n" \ - " Blocksize: %d\n", - o_ringName, io_ringBlockSize); - } - - rc = TOR_SUCCESS; - } - else - { - if (i_dbgl > 0) - { - MY_DBG("Ring %s was not found.\n", o_ringName); - } + if (ringOffset) + { + // 3. Make offset relative to ring section origin + ringOffset = cpltOffset + ringOffset; - rc = TOR_RING_NOT_FOUND; - } + ringSize = be16toh( ((CompressedScanData*) + ((uint8_t*)i_ringSection + ringOffset))->iv_size ); + if (io_ringBlockSize == 0) + { if (i_dbgl > 0) { - MY_DBG("Details for chiplet ring index=%d: \n" - " Full offset to chiplet section = 0x%08x \n" - " Full offset to RS4 header = 0x%08x \n" - " Ring size = 0x%08x \n", - iRing, cpltOffset, ringOffset, ringSize); + MY_DBG("io_ringBlockSize is zero. Returning required size.\n"); } - return rc; - + io_ringBlockSize = ringSize; + return TOR_SUCCESS; } - else if (i_ringBlockType == PUT_SINGLE_RING) + + if (io_ringBlockSize < ringSize) { - if (ringOffset) - { - MY_ERR("Ring container is already present in image\n"); - MY_ERR(" Ring section addr: 0x%016lx (First 8B: 0x%016lx)\n", - (uintptr_t)i_ringSection, - be64toh(*((uint64_t*)i_ringSection))); - MY_ERR(" cpltOffset=0x%08x, torSlotNum=0x%x, TOR offset=0x%04x\n", - cpltOffset, torSlotNum, ringOffset); - return TOR_RING_AVAILABLE_IN_RINGSECTION; - } + MY_ERR("io_ringBlockSize is less than required size.\n"); + return TOR_BUFFER_TOO_SMALL; + } - // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: - // Put location of chiplet's CMN or INST section into ringBlockPtr - memcpy( *io_ringBlockPtr, &cpltOffset, sizeof(cpltOffset)); - // Put location of ringOffset slot into ringBlockSize - io_ringBlockSize = cpltOffset + (torSlotNum * sizeof(ringOffset)); + // Produce return parms + memcpy( *io_ringBlockPtr, (uint8_t*)i_ringSection + ringOffset, ringSize); + io_ringBlockSize = ringSize; + io_instanceId = bInstCase ? + io_instanceId : + chipletData->chipletBaseId; - return TOR_SUCCESS; + if (i_dbgl > 0) + { + MY_DBG("Found a ring:\n" \ + " Name: %s\n" \ + " Blocksize: %d\n", + o_ringName, io_ringBlockSize); } - else + + rc = TOR_SUCCESS; + } + else + { + if (i_dbgl > 0) { - MY_ERR("Ring block type (i_ringBlockType=%d) is not supported\n", i_ringBlockType); - return TOR_INVALID_RING_BLOCK_TYPE; + MY_DBG("ringName=%s was found but is empty\n", + o_ringName); } + + rc = TOR_RING_IS_EMPTY; } - torSlotNum++; // Next TOR ring slot + if (i_dbgl > 0) + { + MY_DBG("Details for chiplet ring index=%d: \n" + " Full offset to chiplet section = 0x%08x \n" + " Full offset to RS4 header = 0x%08x \n" + " Ring size = 0x%08x \n", + iRing, cpltOffset, ringOffset, ringSize); + } + + return rc; + } - } - } - } - else // Since there's no Common/Instance rings, set RING_NOT_FOUND - { - // Note that if we get here, it's because the chiplet doesn't have either - // a Common or Instance rings. This happens e.g. for Centaur which has - // no Instance rings. And theoretically, it's possible to only have - // Instance rings and no Common rings, so accommodating that as well here. - if (i_dbgl > 0) - { - MY_DBG("Chiplet=%d has no CMN(%d) or INST(%d) section\n", - iCplt, (1 - bInstCase), bInstCase); - } + else if (i_ringBlockType == PUT_SINGLE_RING) + { + if (ringOffset) + { + MY_ERR("Ring container is already present in image\n"); + MY_ERR(" Ring section addr: 0x%016lx (First 8B: 0x%016lx)\n", + (uintptr_t)i_ringSection, + be64toh(*((uint64_t*)i_ringSection))); + MY_ERR(" cpltOffset=0x%08x, torSlotNum=0x%x, TOR offset=0x%04x\n", + cpltOffset, torSlotNum, ringOffset); + return TOR_RING_IS_POPULATED; + } - rc = TOR_RING_NOT_FOUND; + // Special [mis]use of io_ringBlockPtr and io_ringBlockSize: + // Put location of chiplet's CMN or INST section into ringBlockPtr + memcpy( *io_ringBlockPtr, &cpltOffset, sizeof(cpltOffset)); + // Put location of ringOffset slot into ringBlockSize + io_ringBlockSize = cpltOffset + (torSlotNum * sizeof(ringOffset)); - } // if (ringIdList) - } // for (bInstCase) - } // for (iCplt) + return TOR_SUCCESS; + } + else + { + MY_ERR("Ring block type (i_ringBlockType=%d) is not supported\n", i_ringBlockType); + return TOR_INVALID_RING_BLOCK_TYPE; + } + } - if (i_dbgl > 0) - { - MY_DBG("i_ringId=0x%x is an invalid ring ID\n", i_ringId); + torSlotNum++; // Next TOR ring slot + } + } + } } + else // Code bug if we get here + { + MY_ERR("CODE BUG: We can't have a ring section with no rings (i.e., no ring slots)." + " Check RING_PROPERTIES and ChipletData lists for :\n" + "chipId: %d\n" + "torMagic: %d\n" + "ringId: 0x%x\n" + "chipletType: %d\n" + "bInstCase: %d\n", + chipId, torMagic, i_ringId, chipletType, bInstCase); + + return INFRASTRUCT_RC_CODE_BUG; + } // if (numRings) - return TOR_INVALID_RING_ID; + return rc; } // End of get_ring_from_ring_section() @@ -330,14 +372,14 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr MY_DBG("TOR header fields\n" " magic: 0x%08x\n" " version: %d\n" - " chipType: %d\n" + " chipId: %d\n" " ddLevel: 0x%x\n" " size: %d\n" "API parms\n" " i_ddLevel: 0x%x\n" " i_ppeType: %d\n" " i_ringVariant: %d\n", - torMagic, torHeader->version, torHeader->chipType, + torMagic, torHeader->version, torHeader->chipId, torHeader->ddLevel, be32toh(torHeader->size), i_ddLevel, i_ppeType, i_ringVariant); @@ -360,19 +402,23 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr } if ( torMagic >> 8 != TOR_MAGIC || - torHeader->version > TOR_VERSION || // Code cannot be forward compatible to a newer image + // Check that we're not trying to be "forward" compatible to a newer image + torHeader->version > TOR_VERSION || + // Make sure version is set torHeader->version == 0 || - torHeader->chipType >= NUM_CHIP_TYPES ) + // Check for valid chip ID and for valid ring ID + ringid_check_ringId(torHeader->chipId, i_ringId) != INFRASTRUCT_RC_SUCCESS ) { - MY_ERR("Invalid TOR header:\n" - " magic: 0x%08x\n" - " version: %d\n" - " chipType: %d\n" + MY_ERR("Invalid TOR header or ringId:\n" + " magic: 0x%08x (TOR_MAGIC: 0x%08x)\n" + " version: %d (TOR_VERSION: %d)\n" + " chipId: %d\n" + " ringId: 0x%x\n" " ddLevel: 0x%x (requested ddLevel=0x%x)\n" " size: %d\n", - torMagic, torHeader->version, torHeader->chipType, - torHeader->ddLevel, i_ddLevel, - be32toh(torHeader->size)); + torMagic, TOR_MAGIC, torHeader->version, TOR_VERSION, + torHeader->chipId, i_ringId, torHeader->ddLevel, + i_ddLevel, be32toh(torHeader->size)); return TOR_INVALID_MAGIC_NUMBER; } @@ -525,7 +571,6 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr int tor_get_block_of_rings ( void* i_ringSection, // Ring section ptr uint8_t i_ddLevel, // DD level PpeType_t i_ppeType, // SBE,CME,SGPE - RingVariant_t i_ringVariant, // Base,CC,RL void** io_ringBlockPtr, // Output ring buffer uint32_t& io_ringBlockSize, // Size of ring data uint32_t i_dbgl ) // Debug option @@ -534,7 +579,7 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section uint8_t l_instanceId; char i_ringName[MAX_RING_NAME_LENGTH]; uint32_t torMagic; - ChipType_t chipType = UNDEFINED_CHIP_TYPE; + ChipId_t chipId = UNDEFINED_CHIP_ID; TorHeader_t* torHeader; if (i_dbgl > 1) @@ -544,9 +589,9 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section torHeader = (TorHeader_t*)i_ringSection; torMagic = be32toh(torHeader->magic); - chipType = torHeader->chipType; + chipId = torHeader->chipId; - if ( torMagic == TOR_MAGIC_HW && chipType != CT_CEN ) + if ( torMagic == TOR_MAGIC_HW && chipId != CID_CEN ) { if (i_ppeType == PT_SBE || i_ppeType == PT_CME || i_ppeType == PT_SGPE) { @@ -555,7 +600,7 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section UNDEFINED_RING_ID, i_ddLevel, i_ppeType, - i_ringVariant, + UNDEFINED_RING_VARIANT, l_instanceId, GET_PPE_LEVEL_RINGS, io_ringBlockPtr, @@ -571,8 +616,8 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section } else { - MY_ERR("tor_get_block_of_rings(): Only the P9 HW ring section is supported. However, torMagic=0x%08x and chipType=%d\n", - torMagic, chipType); + MY_ERR("tor_get_block_of_rings(): Only the P9 HW ring section is supported. However, torMagic=0x%08x and chipId=%d\n", + torMagic, chipId); return TOR_UNSUPPORTED_RING_SECTION; } diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H index 65e863167..52e281a17 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H @@ -184,10 +184,6 @@ int tor_get_single_ring ( void* i_ringSection, /// TOR API uses Ppe type to extract single ring or block of rings /// on either hw_image or SBE image /// -/// \param[in] i_RingVariant A enum to indicate which variant type of -/// requested for single ring extract. There are three major types. -/// They are base, Cache contained and Risk level ring -/// /// \param[in/out] io_ringBlockPtr A void point to pointer. Returns data /// which copied block of rings. Note: Caller's responsibility for free() /// to avoid memory leak @@ -206,7 +202,6 @@ int tor_get_single_ring ( void* i_ringSection, int tor_get_block_of_rings ( void* i_ringSection, uint8_t i_ddLevel, PpeType_t i_PpeType, - RingVariant_t i_RingVariant, void** io_ringBlockPtr, uint32_t& io_ringBlockSize, uint32_t i_dbgl = 0 ); |
