P10 prep: Infrastructure (IS) ring Id metadata and API changes

Gerrit intent:
- Applicable for P9 merge (co-req NOT required)
- Co-req not req'd for any tests

Includes the following changes:
- Accommodates initCompiler's needs for additional ring Id APIs to
  retrieve IS's key ring identifiers, ringId and ringClass, and to
  align with our enumerated chipId
- Elimination of redundancy in and reorg of IS's ring Id lists:
  RingProperties, GenRingIdList (gone) and ChipletData.
  - GenRingIdList has been removed.
- Expand RingProperties to also include scanScomAddr and ringClass.
- Member of ring and chiplet properties structs have been renamed in
  consistent camel style (no longer using "iv_" anywhere).
- Note that with "infrastructure (IS)" we here mean the core infrastructure
  codes that directly interact with and affect the image.

Key_Cronus_Test=XIP_REGRESS

Change-Id: I7e92af04edd10c0994718e476f6e7b77c5d124d6
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59087
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 22 insertions, 14 deletions

diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
index 18a10c5b5..4bd11906e 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
@@ -308,7 +308,7 @@ fapi2::ReturnCode get_overlays_ring(
                io_ringBuf2,  //Has RS4 Gptr overlay ring on return
                l_ringBlockSize);
 
-    if (l_rc == INFRASTRUCT_RC_SUCCESS)
+    if (l_rc == TOR_SUCCESS)
     {
         FAPI_DBG("Successfully found Gptr ringId=0x%x of iv_size=%d bytes", i_ringId,
                  be16toh(((CompressedScanData*)(*io_ringBuf2))->iv_size));
@@ -342,7 +342,7 @@ fapi2::ReturnCode get_overlays_ring(
     }
     else
     {
-        FAPI_ASSERT( l_rc == TOR_RING_NOT_FOUND,
+        FAPI_ASSERT( l_rc == TOR_RING_IS_EMPTY,
                      fapi2::XIPC_GPTR_GET_SINGLE_RING_ERROR().
                      set_CHIP_TARGET(i_procTarget).
                      set_RING_ID(i_ringId).
@@ -560,8 +560,7 @@ fapi2::ReturnCode process_gptr_rings(
     RingId_t l_vpdRingId   = (RingId_t)be16toh(((CompressedScanData*)io_vpdRing)->iv_ringId);
     uint32_t l_vpdScanAddr = be32toh(((CompressedScanData*)io_vpdRing)->iv_scanAddr);
 
-    FAPI_DBG("Entering process_gptr_rings");
-    FAPI_DBG("Processing GPTR ringId=0x%x", l_vpdRingId);
+    FAPI_DBG("process_gptr_rings(): Processing ringId=0x%x", l_vpdRingId);
 
     // Used for getting Gptr ring from overlays section
     void* l_ovlyRs4Ring = io_ringBuf2; //This content will be destroyed later in this function!
@@ -693,8 +692,6 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
     fapi2::current_err  = fapi2::FAPI2_RC_SUCCESS;
     int        l_rc = 0;
 
-    FAPI_DBG("Entering _fetch_and_insert_vpd_ring");
-
     FAPI_INF("_fetch_and_insert_vpd_ring: (ringId,chipletId) = (0x%02X,0x%02x)",
              i_ring.ringId, i_chipletId);
 
@@ -921,8 +918,8 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
                      set_TOR_RC(l_rc).
                      set_RING_ID(i_ring.ringId).
                      set_OCCURRENCE(1),
-                     "tor_append_ring() failed in phase %d w/l_rc=%d for ringId=0x%x",
-                     l_ppeType, l_rc, i_ring.ringId );
+                     "tor_append_ring() failed in sysPhase=%d w/rc=%d for ringId=0x%x",
+                     i_sysPhase, l_rc, i_ring.ringId );
 
         FAPI_INF("Successfully added VPD ring: (ringId,evenOdd,chipletId)=(0x%02X,0x%X,0x%02X)",
                  i_ring.ringId, i_evenOdd, i_chipletId);
@@ -1879,8 +1876,7 @@ ReturnCode p9_xip_customize (
     MyBool_t     l_bDdSupport = UNDEFINED_BOOLEAN;
 
 
-
-    FAPI_DBG ("Entering p9_xip_customize w/sysPhase=%d...", i_sysPhase);
+    FAPI_IMP ("Entering p9_xip_customize w/sysPhase=%d...", i_sysPhase);
 
 
     // Make copy of the requested bootCoreMask
@@ -1889,7 +1885,7 @@ ReturnCode p9_xip_customize (
 
     //-------------------------------------------
     // Check some input buffer parameters:
-    // - sysPhase, modeBuild are checked later
+    // - sysPhase is checked later
     // - log the initial image size
     // - more buffer size checks in big switch()
     //-------------------------------------------
@@ -2600,7 +2596,6 @@ ReturnCode p9_xip_customize (
             l_rc = tor_get_block_of_rings( l_hwRingsSection,
                                            attrDdLevel,
                                            l_ppeType,
-                                           UNDEFINED_RING_VARIANT,
                                            &io_ringSectionBuf,
                                            io_ringSectionBufSize );
 
diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
index 06490cb17..3771af093 100644
--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -28,6 +28,19 @@
 #ifndef WIN32
 #include <fapi2.H>
 
+#define NUM_OF_CORES     (uint8_t)24
+#define NUM_OF_CMES      (uint8_t)12
+#define NUM_OF_QUADS     (uint8_t) 6
+#define CORES_PER_QUAD   (NUM_OF_CORES/NUM_OF_QUADS)
+
+enum SYSPHASE
+{
+    SYSPHASE_HB_SBE = 0,
+    SYSPHASE_RT_CME = 1,
+    SYSPHASE_RT_SGPE = 2,
+    NOOF_SYSPHASES = 3,
+};
+
 typedef fapi2::ReturnCode (*p9_xip_customize_FP_t) (
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_proc_target,
     void*     i_hwImage,
@@ -83,7 +96,7 @@ extern "C"
 ///                                             In:  >=MAX_SBE_SEEPROM_SIZE
 ///                                             Out: Final size
 /// @param[in] i_sysPhase                => ={HB_SBE, RT_CME, RT_SGPE}
-/// @param[in] i_modeBuild               => ={IPL, REBUILD}
+/// @param[in] i_modeBuild               => ={IPL, REBUILD} - Not used in P9
 /// @param[in] i_ringBuf1                => Caller supplied in-memory buffer
 ///                                         for VPD rings
 /// @param[in] i_ringBufSize1            => Max size of VPD ring buffer