diff options
| author | Louis Stermole <stermole@us.ibm.com> | 2018-04-13 15:09:30 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-05-16 15:39:31 -0400 |
| commit | 29bde9b906c9c7bc1ba45b7bfef6d9c7ef1ecfca (patch) | |
| tree | 932d5e6ba8cebd3ff290610e908f571132c50f9b /src/import/chips/centaur/procedures/xml | |
| parent | b7a44c2259760465b375795baeea883b9f08b44d (diff) | |
| download | blackbird-hostboot-29bde9b906c9c7bc1ba45b7bfef6d9c7ef1ecfca.tar.gz blackbird-hostboot-29bde9b906c9c7bc1ba45b7bfef6d9c7ef1ecfca.zip | |
WR_LVL Termination Fix (Qoff) for p9c, DDR4 only
Change-Id: Iabc29772b0618231bee469b65bcbe30e76935486
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57201
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57208
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/xml')
| -rw-r--r-- | src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml | 4 | ||||
| -rw-r--r-- | src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml | 33 |
2 files changed, 35 insertions, 2 deletions
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index 5c1ad1fb9..281b03a77 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -2714,7 +2714,8 @@ Firmware notes: none</description> <attribute> <id>ATTR_CEN_MSS_CAL_STEP_ENABLE</id> <targetType>TARGET_TYPE_MBA</targetType> - <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL + <description>A bit vector denoting valid cal steps to run during dram_init_train. +[0] EXT_ZQCAL [1] WR_LEVEL [2] DQS_ALIGN [3] RDCLK_ALIGN @@ -2724,6 +2725,7 @@ Firmware notes: none</description> [7] COARSE_RD bits6:7 will be consumed together to form COARSE_LVL. </description> <valueType>uint8</valueType> + <enum>EXT_ZQCAL = 0, WR_LVL = 1, DQS_ALIGN = 2, RDCLK_ALIGN = 3, RD_CTR = 4, WR_CTR = 5, COARSE_WR = 6, COARSE_RD = 7</enum> <writeable/> <odmVisable/> <odmChangeable/> diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml index 06648afb4..cbed4cf8c 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_draminit_training_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -151,6 +151,37 @@ </hwpError> <hwpError> + <rc>RC_CEN_INVALID_INPUT_DATA</rc> + <description>Function received invalid input args.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <ffdc>RANKGROUP_POSITION</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> + <rc>RC_CEN_INVALID_PORT</rc> + <description>Function received invalid port arg.</description> + <ffdc>MBA_POSITION</ffdc> + <ffdc>PORT_POSITION</ffdc> + <callout> + <target>TARGET_MBA_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + +<hwpError> <rc>RC_CEN_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR</rc> <description>Write Leveling has returned a fail for a given position within this calibration.</description> <ffdc>MBA_POSITION</ffdc> |
