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| author | Stephen Cprek <smcprek@us.ibm.com> | 2017-06-20 16:48:07 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-07-20 15:54:48 -0400 |
| commit | 781d316517240e869cc76ceff5cde3eb1fe6bc48 (patch) | |
| tree | 22009f9a9b34b9fe4456e72ce8bd5ce783aa0074 /src/build/debug/Hostboot | |
| parent | 22d6e4636c815eecdcf778c417ef217e32878fba (diff) | |
| download | blackbird-hostboot-781d316517240e869cc76ceff5cde3eb1fe6bc48.tar.gz blackbird-hostboot-781d316517240e869cc76ceff5cde3eb1fe6bc48.zip | |
Increase HBB PNOR section max size to 1MB with ECC
Change-Id: Icfd9411deac792d9772e89e35e7da5df272a7ecc
RTC: 175114
CMVC-prereq: 1027576
CMVC-prereq: 1027947
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42170
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/debug/Hostboot')
| -rwxr-xr-x | src/build/debug/Hostboot/Dump.pm | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/build/debug/Hostboot/Dump.pm b/src/build/debug/Hostboot/Dump.pm index 9ce3dd679..0966e2187 100755 --- a/src/build/debug/Hostboot/Dump.pm +++ b/src/build/debug/Hostboot/Dump.pm @@ -41,20 +41,23 @@ use constant MEMSTATE_MS_32MEG => 0x20; use constant _KB => 1024; use constant _MB => 1024 * 1024; +# Size of HBB PNOR partition without ECC, page algined down, minus 4K header +use constant MAX_HBB_SIZE => (904 * _KB); + # Map the available memory at each state. +# *** NOTE: Keep in sync with fsp-memdump.sh and bootloaderif.H (MAX_HBB_SIZE) our %memory_maps = ( MEMSTATE_NO_MEM() => # No memory has been initialized so we can only dump our static - # code load up to 512 - 4k. The 4k is a reserved space for the - # Secureboot Header. - [ 0, (512 - 4) * _KB + # code load up to HBB size + [ 0, MAX_HBB_SIZE ], MEMSTATE_HALF_CACHE() => - # All of the first 4MB can now be read (except reserved MBOX). - [ 512 * _KB, 512 * _KB, - 1 * _MB + 512 * _KB, 512 * _KB, - 2 * _MB + 512 * _KB, 512 * _KB, - 3 * _MB + 512 * _KB, 512 * _KB + # All of the first 4MB can now be read. + [ MAX_HBB_SIZE, ((1 * _MB) - MAX_HBB_SIZE), + 1 * _MB, 1 * _MB, + 2 * _MB, 1 * _MB, + 3 * _MB, 1 * _MB ], MEMSTATE_REDUCED_CACHE() => # Initial chips may have 2MB bad cache |
