Changes for Brazos 2z/3z Support

This commit has the hostboot changes for Brazos 2z/3z support along with
some attributes that Hostboot and HWSV share.  It also contains memory
XML and HWP changes from SW305517 and SW305518.

Change-Id: I71896dfac6946624bed3e216fe7823bd73e8e6bc
RTC: 125037
CQ:SW305518
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19306
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19375
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

20 files changed, 1119 insertions, 160 deletions

diff --git a/src/include/usr/hwpf/hwpf_reasoncodes.H b/src/include/usr/hwpf/hwpf_reasoncodes.H
index f3d66de6c..e1a00da4a 100644
--- a/src/include/usr/hwpf/hwpf_reasoncodes.H
+++ b/src/include/usr/hwpf/hwpf_reasoncodes.H
@@ -79,6 +79,7 @@ namespace fapi
         MOD_GET_VER_ONE_VOLTAGE_BUCKET_DATA        = 0x25,
         MOD_PLAT_MVPD_GET_VLTG_BUCKET_ATTR         = 0x26,
         MOD_PLAT_ATTR_SVC_CEN_DQ_TO_DIMM_CONN_DQ   = 0x27,
+        MOD_PLAT_ATTR_SVC_GET_MEM_ATTR_DATA        = 0x28,
 
     };
 
@@ -137,6 +138,7 @@ namespace fapi
         RC_INVALID_PARAM              = HWPF_COMP_ID | 0x37,
         RC_DATA_MISMATCH              = HWPF_COMP_ID | 0x38,
         RC_DATA_NOT_SUPPORTED         = HWPF_COMP_ID | 0x39,
+        RC_NO_SINGLE_NODE             = HWPF_COMP_ID | 0x3A,
     };
 
     /**
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index 58efade6f..38ea06355 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -795,6 +795,20 @@ fapi::ReturnCode fapiPlatGetTpVitlSpyLengthAttr(
 fapi::ReturnCode fapiPlatGetTpVitlSpyOffsetAttr(
                                const fapi::Target * i_pProcTarget,
                                uint32_t (&o_data)[SPY_OFFSET_SIZE]);
+/*
+ * @brief This function is called by the FAPI_ATTR_GET macro when getting
+ * certain memory attributes
+ * It should not be called directly.
+ *
+ *  @param[in]  i_pTarget   Target Centaur pointer
+ *  @param[in]  i_attr      Attribute Id
+ *  @param[out] o_val       Attribute Value
+ *  @return     ReturnCode. Zero on success, else platform specified error
+ */
+fapi::ReturnCode fapiPlatGetMemAttrData (
+                                const fapi::Target * i_pTarget,
+                                const TARGETING::ATTRIBUTE_ID i_attr,
+                                uint32_t & o_val);
 
 } // namespace platAttrSvc
 
@@ -2748,4 +2762,78 @@ fapi::ReturnCode fapiPlatGetTpVitlSpyOffsetAttr(
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetTpVitlSpyOffsetAttr(PTARGET, VAL)
 
+//------------------------------------------------------------------------------
+//  MACROS to support Memory Attributes at node level
+//------------------------------------------------------------------------------
+#define ATTR_MSS_VDD_SLOPE_ACTIVE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+              PTARGET, TARGETING::ATTR_MSS_CENT_VDD_SLOPE_ACTIVE, VAL)
+#define ATTR_MSS_VDD_SLOPE_INACTIVE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_CENT_VDD_SLOPE_INACTIVE, VAL)
+#define ATTR_MSS_VDD_SLOPE_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_CENT_VDD_INTERCEPT, VAL)
+#define ATTR_MSS_VCS_SLOPE_ACTIVE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_CENT_VCS_SLOPE_ACTIVE, VAL)
+#define ATTR_MSS_VCS_SLOPE_INACTIVE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_CENT_VCS_SLOPE_INACTIVE, VAL)
+#define ATTR_MSS_VCS_SLOPE_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_CENT_VCS_INTERCEPT, VAL)
+#define ATTR_MSS_VPP_SLOPE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_EFF_CONFIG, VAL)
+#define ATTR_MSS_VPP_SLOPE_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG, VAL)
+#define ATTR_MSS_DDR3_VDDR_SLOPE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG, VAL)
+#define ATTR_MSS_DDR3_VDDR_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(PTARGET,\
+            TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG, VAL)
+#define ATTR_MRW_DDR3_VDDR_MAX_LIMIT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG, VAL)
+#define ATTR_MSS_DDR4_VDDR_SLOPE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG, VAL)
+#define ATTR_MSS_DDR4_VDDR_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(PTARGET,\
+            TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG, VAL)
+#define ATTR_MRW_DDR4_VDDR_MAX_LIMIT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+        fapi::FAPI_RC_SUCCESS : \
+        fapi::platAttrSvc::fapiPlatGetMemAttrData(\
+            PTARGET, TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG, VAL)
+
 #endif // FAPIPLATATTRIBUTESERVICE_H_
diff --git a/src/include/usr/isteps/istep13list.H b/src/include/usr/isteps/istep13list.H
index e717a4a66..4c5c57983 100644
--- a/src/include/usr/isteps/istep13list.H
+++ b/src/include/usr/isteps/istep13list.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -152,6 +152,7 @@ const DepModInfo g_istep13Dependancies = {
 #ifndef CONFIG_VPO_COMPILE
         DEP_LIB(libdram_training.so),
         DEP_LIB(libdram_initialization.so),
+        DEP_LIB(libmc_config.so),
 #endif
         NULL
     }
diff --git a/src/include/usr/targeting/common/target.H b/src/include/usr/targeting/common/target.H
index 04599859f..25e7be6b6 100644
--- a/src/include/usr/targeting/common/target.H
+++ b/src/include/usr/targeting/common/target.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index a6d996033..0f811cfc0 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -79,6 +79,8 @@ const uint8_t VPO_NUM_OF_MEMBUF_TO_RUN = UNLIMITED_RUN;
 #include    "mss_draminit_trainadv/mss_draminit_training_advanced.H"
 #include    "mss_draminit_mc/mss_draminit_mc.H"
 #include    "proc_throttle_sync.H"
+#include    "../mc_config/mc_config.H"
+
 
 namespace   DRAM_TRAINING
 {
@@ -530,6 +532,75 @@ void*  call_mss_ddr_phy_reset( void *io_pArgs )
     return l_stepError.getErrorHandle();
 }
 
+//
+//  Wrapper function to call mss_post_draminit
+//
+void   mss_post_draminit( IStepError & l_stepError )
+{
+    errlHndl_t l_err = NULL;
+    bool rerun_vddr = false;
+
+    do {
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit entry" );
+
+    set_eff_config_attrs_helper(MC_CONFIG::POST_DRAM_INIT, rerun_vddr);
+
+    if ( rerun_vddr == false )
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "mss_post_draminit: nothing to do" );
+        break;
+    }
+
+    // Call mss_volt_vddr_offset to recalculate VDDR voltage
+
+    l_err = MC_CONFIG::setMemoryVoltageDomainOffsetVoltage<
+        TARGETING::ATTR_MSS_VOLT_VDDR_OFFSET_DISABLE,
+        TARGETING::ATTR_MEM_VDDR_OFFSET_MILLIVOLTS,
+        TARGETING::ATTR_VMEM_ID>();
+    if(l_err)
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit: "
+            "ERROR 0x%08X: setMemoryVoltageDomainOffsetVoltage for VDDR domain",
+            l_err->reasonCode());
+        l_stepError.addErrorDetails(l_err);
+        errlCommit(l_err,HWPF_COMP_ID);
+        break;
+    }
+    else
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "mss_post_draminit: mss_volt_vddr_offset(): SUCCESS");
+    }
+
+    // Call HWSV to call POWR code
+    // This fuction has compile-time binding for different platforms
+    l_err = platform_adjust_vddr_post_dram_init();
+
+    if( l_err )
+    {
+        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                  "ERROR 0x%.8X: mss_post_draminit: "
+                  "platform_adjust_vddr_post_dram_init() returns error",
+                  l_err->reasonCode());
+
+        // Create IStep error log and cross reference to error that occurred
+        l_stepError.addErrorDetails( l_err );
+
+        // Commit Error
+        errlCommit( l_err, HWPF_COMP_ID );
+    }
+
+    } while(0);
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+            "mss_post_draminit exit" );
+
+    return;
+}
+
+
 
 //
 //  Wrapper function to call mss_draminit
@@ -593,6 +664,12 @@ void*    call_mss_draminit( void *io_pArgs )
 
     }   // endfor   mba's
 
+    // call POST_DRAM_INIT function
+    if(INITSERVICE::spBaseServicesEnabled())
+    {
+        mss_post_draminit(l_stepError);
+    }
+
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" );
 
     return l_stepError.getErrorHandle();
diff --git a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
index 2119ed222..7198988ee 100644
--- a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
+++ b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
@@ -223,7 +223,7 @@ void HBVddrMsg::addMemoryVoltageDomains(
 ///////////////////////////////////////////////////////////////////////////////
 
 void HBVddrMsg::createVddrData(
-    const VDDR_MSG_TYPE     i_requestType,
+          VDDR_MSG_TYPE     i_requestType,
           RequestContainer& io_request) const
 {
     TRACFCOMP( g_trac_volt, ENTER_MRK "HBVddrMsg::createVddrData" );
@@ -302,7 +302,8 @@ void HBVddrMsg::createVddrData(
             io_request.erase(pInvalidEntries,io_request.end());
         }
 
-        if(   (i_requestType == HB_VDDR_ENABLE)
+        if( ( (i_requestType == HB_VDDR_ENABLE) ||
+              (i_requestType == HB_VDDR_POST_DRAM_INIT_ENABLE) )
            && (!membufTargetList.empty())      )
         {
             // Inhibit sending any request to turn on a domain with no voltage.
@@ -322,7 +323,7 @@ void HBVddrMsg::createVddrData(
 ///////////////////////////////////////////////////////////////////////////////
 // HBVddrMsg::sendMsg
 ///////////////////////////////////////////////////////////////////////////////
-errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
+errlHndl_t HBVddrMsg::sendMsg(VDDR_MSG_TYPE i_msgType) const
 {
     errlHndl_t l_err = NULL;
 
@@ -333,13 +334,9 @@ errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
     {
         RequestContainer l_request;
 
-        if ( (i_msgType == HB_VDDR_ENABLE) || (i_msgType == HB_VDDR_DISABLE) )
-        {
-            VDDR_MSG_TYPE msgType = (i_msgType == HB_VDDR_ENABLE)
-                ? HB_VDDR_ENABLE : HB_VDDR_DISABLE;
-            createVddrData(msgType, l_request);
-        }
-        else
+        if ( ! ( (i_msgType == HB_VDDR_ENABLE) ||
+                 (i_msgType == HB_VDDR_DISABLE) ||
+                 (i_msgType == HB_VDDR_POST_DRAM_INIT_ENABLE) ) )
         {
             TRACFCOMP(g_trac_volt, ERR_MRK "hbVddrMsg::send msg with non-"
                       "valid msg type%08X",i_msgType);
@@ -358,6 +355,8 @@ errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
                          fapi::RC_INCORRECT_MSG_TYPE, i_msgType);
             break;
         }
+        createVddrData(i_msgType, l_request);
+
 
         size_t l_dataCount = l_request.size();
 
@@ -544,7 +543,8 @@ errlHndl_t HBVddrMsg::processMsg(msg_t* i_Msg) const
             TRACFCOMP( g_trac_volt, INFO_MRK
                        "HBVddrMsg::processMsg l_msgType=x%08X",l_msgType );
             if ( (l_msgType == HB_VDDR_ENABLE) ||
-                 (l_msgType == HB_VDDR_DISABLE) )
+                 (l_msgType == HB_VDDR_DISABLE)||
+                 (l_msgType == HB_VDDR_POST_DRAM_INIT_ENABLE) )
             {
                 //process a VDDR message    
                 l_errLog=processVDDRmsg(i_Msg);
@@ -653,7 +653,7 @@ errlHndl_t platform_enable_vddr()
                        "SUCCESS :  host_enable_vddr()" );
         }
     }
-    else // simics stand-alone TULETTA
+    else // no FSP/mbox services available
     {
         TRACFCOMP(g_trac_volt,"call_host_enable_vddr"
                 "no-op because mbox not available");
@@ -683,7 +683,7 @@ errlHndl_t platform_disable_vddr()
                        "SUCCESS :  host_disable_vddr()" );
         }
     }
-    else  // simics stand-along TULETTA
+    else  // no FSP/mbox services available
     {
         TRACFCOMP(g_trac_volt,"call_host_disable_vddr"
                 "no-op because mbox not available");
@@ -692,3 +692,33 @@ errlHndl_t platform_disable_vddr()
     return l_err;
 }
 
+errlHndl_t platform_adjust_vddr_post_dram_init()
+{
+    errlHndl_t l_err = NULL;
+    if(INITSERVICE::spBaseServicesEnabled())
+    {
+        HBVddrMsg l_hbVddr;
+
+        l_err = l_hbVddr.sendMsg(HBVddrMsg::HB_VDDR_POST_DRAM_INIT_ENABLE);
+        if (l_err)
+        {
+            TRACFCOMP(g_trac_volt,
+                      "ERROR 0x%.8X: call_host_adjust_vddr_post_dram_init to "
+                      "sendMsg returns error",
+                      l_err->reasonCode());
+        }
+        else
+        {
+            TRACFCOMP( g_trac_volt,
+                       "SUCCESS :  host_adjust_vddr_post_dram_init()" );
+        }
+    }
+    else  // no FSP/mbox services available
+    {
+        TRACFCOMP(g_trac_volt,"call_host_adjust_vddr_post_dram_init()"
+                "no-op because mbox not available");
+    }
+
+    return l_err;
+}
+
diff --git a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
index f04019919..23f79fc14 100644
--- a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
+++ b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -136,6 +138,7 @@ public:
     {
         HB_VDDR_ENABLE = 0x40000041,
         HB_VDDR_DISABLE = 0x40000042,
+        HB_VDDR_POST_DRAM_INIT_ENABLE = 0x40000043,
     };
 
     /**
@@ -180,7 +183,7 @@ public:
      *  @return N/A
      */
     void createVddrData(
-        const VDDR_MSG_TYPE     i_requestType,
+              VDDR_MSG_TYPE     i_requestType,
               RequestContainer& io_request) const;
 
     /**
@@ -199,7 +202,7 @@ public:
       *              return errl ==  NULL  -> success
       *              return errl !=  NULL  -> failure
      */
-    errlHndl_t sendMsg(uint32_t i_msgType) const;
+    errlHndl_t sendMsg(VDDR_MSG_TYPE i_msgType) const;
 
 private:
 
diff --git a/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C b/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
index b456324a4..b0b7e47d7 100644
--- a/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
+++ b/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
@@ -356,3 +356,10 @@ errlHndl_t platform_disable_vddr()
     return for_each_vddr_domain_with_functional_memory(
         disableVddrViaGpioPinStrategy);
 }
+
+errlHndl_t platform_adjust_vddr_post_dram_init()
+{
+    // Not supported on palmetto
+    return NULL;
+}
+
diff --git a/src/usr/hwpf/hwp/dram_training/platform_vddr.H b/src/usr/hwpf/hwp/dram_training/platform_vddr.H
index 98c013535..b726aee0c 100644
--- a/src/usr/hwpf/hwp/dram_training/platform_vddr.H
+++ b/src/usr/hwpf/hwp/dram_training/platform_vddr.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -43,6 +43,12 @@ errlHndl_t platform_enable_vspd();
 errlHndl_t platform_enable_vddr();
 
 /**
+ * @brief Adjust vddr on DIMMS with POST DRAM INITs
+ * @return NULL | error handle on error
+ */
+errlHndl_t platform_adjust_vddr_post_dram_init();
+
+/**
  * @brief Disable vddr on DIMMS
  * @return NULL | error handle on error
  */
diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C
index 1d1ea9780..b2bc2f165 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.C
@@ -89,6 +89,230 @@ using   namespace   ERRORLOG;
 using   namespace   TARGETING;
 using   namespace   fapi;
 
+
+//
+//  Helper function to set _EFF_CONFIG attributes for HWPs
+//
+void set_eff_config_attrs_helper( const EFF_CONFIG_ATTRIBUTES_BASE i_base,
+                                  bool & o_post_dram_inits_found)
+{
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "set_eff_config_attrs_helper: setting _EFF_CONFIG attributes "
+               "enter: i_base=%d", i_base);
+
+    o_post_dram_inits_found = false;
+
+    // Local Variables ('pdi_' means 'post dram init')
+    uint32_t pdi_ddr3_vddr_slope=0;
+    uint32_t pdi_ddr3_vddr_intercept=0;
+    uint32_t pdi_ddr3_vddr_max_limit=0;
+    uint32_t pdi_ddr4_vddr_slope=0;
+    uint32_t pdi_ddr4_vddr_intercept=0;
+    uint32_t pdi_ddr4_vddr_max_limit=0;
+    uint32_t pdi_vpp_slope=0;
+    uint32_t pdi_vpp_intercept=0;
+
+    uint32_t eff_conf_ddr3_vddr_slope=0;
+    uint32_t eff_conf_ddr3_vddr_intercept=0;
+    uint32_t eff_conf_ddr3_vddr_max_limit=0;
+    uint32_t eff_conf_ddr4_vddr_slope=0;
+    uint32_t eff_conf_ddr4_vddr_intercept=0;
+    uint32_t eff_conf_ddr4_vddr_max_limit=0;
+    uint32_t eff_conf_vpp_slope=0;
+    uint32_t eff_conf_vpp_intercept=0;
+
+    // Check input base
+    assert( ( i_base == DEFAULT ) || (i_base == POST_DRAM_INIT ),
+            "set_eff_config_attrs_helper: Invalid i_base passed in: %d",
+            i_base);
+
+    // Get Node Target
+    TARGETING::Target* sysTgt = NULL;
+    TARGETING::targetService().getTopLevelTarget(sysTgt);
+    assert(sysTgt != NULL,"System target was NULL.");
+
+    TARGETING::TargetHandleList l_nodeList;
+
+    TARGETING::PredicateCTM isaNode(TARGETING::CLASS_ENC,
+                                    TARGETING::TYPE_NODE);
+
+    TARGETING::targetService().getAssociated(
+                                   l_nodeList,
+                                   sysTgt,
+                                   TARGETING::TargetService::CHILD,
+                                   TARGETING::TargetService::IMMEDIATE,
+                                   &isaNode);
+
+    // Node list should only have 1 tgt
+    assert ( l_nodeList.size() == 1,
+             "System target returned multiple or zero nodes ");
+    TARGETING::Target* nodeTgt=l_nodeList[0];
+
+
+
+    // Look for POST_DRAM_INIT Attributes if requested
+    if ( i_base == POST_DRAM_INIT )
+    {
+        // POST_DRAM_INIT DDR3 VDDR
+        pdi_ddr3_vddr_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT>();
+
+        pdi_ddr3_vddr_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT>();
+
+        pdi_ddr3_vddr_max_limit =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT>();
+
+        // POST_DRAM_INIT DDR4 VDDR
+        pdi_ddr4_vddr_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT>();
+
+        pdi_ddr4_vddr_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT>();
+
+        pdi_ddr4_vddr_max_limit =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT>();
+
+
+        // POST_DRAM_INIT VPP
+        pdi_vpp_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT>();
+
+        pdi_vpp_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT>();
+    }
+    o_post_dram_inits_found = ( pdi_ddr3_vddr_slope || pdi_ddr3_vddr_intercept ||
+                                pdi_ddr3_vddr_max_limit ||
+                                pdi_ddr4_vddr_slope || pdi_ddr4_vddr_intercept ||
+                                pdi_ddr4_vddr_max_limit ||
+                                pdi_vpp_slope || pdi_vpp_intercept )
+                              ? true : false;
+
+    // -----------------------------------
+    // EFF CONFIG: DDR3 VDDR
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system values
+        eff_conf_ddr3_vddr_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE>();
+
+        eff_conf_ddr3_vddr_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT>();
+
+        eff_conf_ddr3_vddr_max_limit =
+                 sysTgt->getAttr<
+                    TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT values
+        eff_conf_ddr3_vddr_slope     = pdi_ddr3_vddr_slope;
+        eff_conf_ddr3_vddr_intercept = pdi_ddr3_vddr_intercept;
+        eff_conf_ddr3_vddr_max_limit = pdi_ddr3_vddr_max_limit;
+    }
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_intercept);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_max_limit);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "DDR3 _EFF_CONFIG(%d, %d): slope=%d, intercept=%d, max_limit=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_ddr3_vddr_slope,
+               eff_conf_ddr3_vddr_intercept,
+               eff_conf_ddr3_vddr_max_limit);
+
+
+    // -----------------------------------
+    // EFF CONFIG: DDR4 VDDR
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system value
+        eff_conf_ddr4_vddr_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE>();
+
+        eff_conf_ddr4_vddr_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT>();
+
+        eff_conf_ddr4_vddr_max_limit =
+                 sysTgt->getAttr<
+                    TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT value
+        eff_conf_ddr4_vddr_slope     = pdi_ddr4_vddr_slope;
+        eff_conf_ddr4_vddr_intercept = pdi_ddr4_vddr_intercept;
+        eff_conf_ddr4_vddr_max_limit = pdi_ddr4_vddr_max_limit;
+    }
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_intercept);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_max_limit);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "DDR4 _EFF_CONFIG(%d, %d): slope=%d, intercept=%d, max_limit=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_ddr4_vddr_slope,
+               eff_conf_ddr4_vddr_intercept,
+               eff_conf_ddr4_vddr_max_limit);
+
+    // -----------------------------------
+    // EFF CONFIG: VPP
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system value
+        eff_conf_vpp_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_VPP_SLOPE>();
+
+        eff_conf_vpp_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT value
+        eff_conf_vpp_slope     = pdi_vpp_slope;
+        eff_conf_vpp_intercept = pdi_vpp_intercept;
+    }
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_EFF_CONFIG>\
+             (eff_conf_vpp_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_vpp_intercept);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "VPP _EFF_CONFIG(%d, %d): slope=%d, intercept=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_vpp_slope,
+               eff_conf_vpp_intercept);
+
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "set_eff_config_attrs_helper: setting _EFF_CONFIG "
+               "attributes exit");
+
+}
+
 //
 //  Wrapper function to call host_collect_dimm_spd
 //
@@ -528,6 +752,10 @@ void* call_mss_volt( void *io_pArgs )
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_volt entry" );
 
+    // Check that VPP, DDR3 VDDR, and DDR4 VDDR _EFF_CONFIG attributes are set
+    bool unused = false;
+    set_eff_config_attrs_helper(DEFAULT, unused);
+
     TARGETING::TargetHandleList l_membufTargetList;
     getAllChips(l_membufTargetList, TYPE_MEMBUF);
 
diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.H b/src/usr/hwpf/hwp/mc_config/mc_config.H
index 12b25b36c..8e53cdbd1 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.H
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -180,6 +182,32 @@ void*    call_mss_eff_config( void * io_pArgs );
 void*    call_mss_attr_update( void *io_pArgs );
 
 
+/**
+ *  @brief Enum specifying what attributes should be used to set the
+ *         memory _EFF_CONFIG attributes
+ *
+ */
+enum EFF_CONFIG_ATTRIBUTES_BASE
+{
+    DEFAULT         = 0x00, ///< Use System Defaults
+    POST_DRAM_INIT  = 0x01, ///< Use POST_DRAM_INIT attributes if non-zero
+};
+
+
+/**
+ * @brief  Helper function to set memory _EFF_CONFIG attributes for HWPs
+ *
+ *  param[in]  i_base - Determines base of EFF_CONFIG attributes values
+ *
+ *  param[out] o_post_dram_inits_found - if i_base==POST_DRAM_INIT and
+ *                                          POST_DRAM_INIT attributes were
+ *                                          found return TRUE;
+ *                                       else, return FALSE
+ */
+void set_eff_config_attrs_helper( const EFF_CONFIG_ATTRIBUTES_BASE i_base,
+                                  bool & o_post_dram_inits_found);
+
+
 };   // end namespace
 
 #endif
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
index daeb4bcc0..5fd0ed7d4 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vcs_offset.C,v 1.7 2014/06/19 16:06:11 dcadiga Exp $
+// $Id: mss_volt_vcs_offset.C,v 1.8 2015/07/22 14:15:46 sglancy Exp $
 /* File mss_volt_vcs_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.8    | sglancy  | 03/24/15 | Updated for 2Z/3Z ATTR update
 //  1.7    | sglancy  | 06/19/14 | Includes update to force the VCS to be 100 mV higher than the VDD
 //  1.6    | sglancy  | 06/18/14 | Updated errors
 //  1.5    | sglancy  | 06/09/14 | Updated debug statements
@@ -90,12 +91,14 @@ fapi::ReturnCode mss_volt_vcs_offset(std::vector<fapi::Target> & i_targets)
     }
     
     //computes vcs value
-    //gets the necessary attributes and checks for errors
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_ACTIVE,NULL,slope_active); 
+    //gets the necessary attributes and checks for errors - attributes should be the same accross each node
+    //attributes are stored at the centaur level, only the first centaur in the vector is grabbed
+    // this code should only be called with 1 or more centaur's configured, so this is a valid assumption to make
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_ACTIVE,&i_targets[0],slope_active);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INACTIVE,NULL,slope_inactive); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INACTIVE,&i_targets[0],slope_inactive);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INTERCEPT,NULL,intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INTERCEPT,&i_targets[0],intercept);
     if(l_rc) return l_rc;
 
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
index 3fa305d0c..950ebd6fb 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vdd_offset.C,v 1.6 2014/06/18 20:34:34 dcadiga Exp $
+// $Id: mss_volt_vdd_offset.C,v 1.7 2015/07/22 14:15:53 sglancy Exp $
 /* File mss_volt_vdd_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.7    | sglancy  | 03/24/15 | Updated for 2Z/3Z ATTR update
 //  1.6    | sglancy  | 06/18/14 | Updated error flags
 //  1.5    | sglancy  | 06/09/14 | Updated debug statements
 //  1.4    | sglancy  | 06/04/14 | Updated to include output attribute
@@ -89,12 +90,14 @@ fapi::ReturnCode mss_volt_vdd_offset(std::vector<fapi::Target> & i_targets)
     }
 
     //computes vdd value
-    //gets the necessary attributes and checks for errors
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_ACTIVE,NULL,slope_active); 
+    //gets the necessary attributes and checks for errors - attributes should be the same accross each node
+    //attributes are stored at the centaur level, only the first centaur in the vector is grabbed
+    // this code should only be called with 1 or more centaur's configured, so this is a valid assumption to make
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_ACTIVE,&i_targets[0],slope_active);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INACTIVE,NULL,slope_inactive); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INACTIVE,&i_targets[0],slope_inactive);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INTERCEPT,NULL,intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INTERCEPT,&i_targets[0],intercept);
     if(l_rc) return l_rc;
     
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
index 15540644c..120a0212b 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vddr_offset.C,v 1.24 2015/01/21 18:13:30 sglancy Exp $
+// $Id: mss_volt_vddr_offset.C,v 1.25 2015/07/22 14:16:02 sglancy Exp $
 /* File mss_volt_vddr_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.25   | sglancy  | 07/22/15 | Updates for 2z/3z and DDR4
 //  1.24   | sglancy  | 01/21/15 | Updated for addition of ATTR_CENTAUR_EC_DISABLE_VDDR_DYNAMIC_VID
 //  1.23   | sglancy  | 11/20/14 | Updated for rounding
 //  1.22   | sglancy  | 11/20/14 | Fixed compile issue
@@ -235,20 +236,20 @@ fapi::ReturnCode mss_volt_vddr_offset(std::vector<fapi::Target> & i_targets)
     
     //gets the attributes and computes var_power_on based upon whether the DRAM type is DDR3 or DDR4
     if(dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_SLOPE,NULL,volt_slope); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_SLOPE,&i_targets[0],volt_slope);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_INTERCEPT,NULL,volt_intercept); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_INTERCEPT,&i_targets[0],volt_intercept);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR3_VDDR_MAX_LIMIT,NULL,vddr_max_limit_mv); 
+       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR3_VDDR_MAX_LIMIT,&i_targets[0],vddr_max_limit_mv);
        if(l_rc) return l_rc;
     }
     //ddr4
     else {
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_SLOPE,NULL,volt_slope); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_SLOPE,&i_targets[0],volt_slope);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_INTERCEPT,NULL,volt_intercept); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_INTERCEPT,&i_targets[0],volt_intercept);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR4_VDDR_MAX_LIMIT,NULL,vddr_max_limit_mv); 
+       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR4_VDDR_MAX_LIMIT,&i_targets[0],vddr_max_limit_mv);
        if(l_rc) return l_rc;
     }
     
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
index 26ef2938e..b8740823b 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vpp_offset.C,v 1.18 2014/09/12 15:37:51 sglancy Exp $
+// $Id: mss_volt_vpp_offset.C,v 1.20 2015/07/22 14:15:06 sglancy Exp $
 /* File mss_volt_vpp_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.20   | sglancy  | 07/22/15 | DDR4 updates allowing both DDR3 and DDR4 DIMMs on the same VPP plane
+//  1.19   | sglancy  | 04/21/15 | Added support for mixed voltage plane configurations.  still checks for mixed centaur bugs
 //  1.18   | sglancy  | 09/12/14 | Removed references to EFF attributes
 //  1.17   | sglancy  | 09/12/14 | Fixed bugs
 //  1.16   | sglancy  | 09/11/14 | Fixed bugs
@@ -90,13 +92,16 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     uint32_t vpp_slope, vpp_intercept;
     uint8_t dram_width, enable, dram_gen;
     uint8_t cur_dram_gen, is_functional; 
+    bool dram_gen_found_mc = false;
     bool dram_gen_found = false;
+    bool dram_gen_ddr4 = false;
     uint8_t num_spares[2][2][4];
     uint8_t rank_config, num_non_functional;
     num_non_functional = 0;
     std::vector<fapi::Target>  l_mbaChiplets;
     std::vector<fapi::Target>  l_dimm_targets;
-    
+    std::vector<uint8_t> dram_gen_vector; //used to ID whether an MC needs to be used in the VPP offset calculations
+
     //checks to make sure that all of the DRAM generation attributes are the same, if not error out
     for(uint32_t i = 0; i < i_targets.size();i++) {
        //gets the functional attribute to check for an active centaur
@@ -108,7 +113,9 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
        if(is_functional != fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) {
           num_non_functional++;
        }
-       
+
+       dram_gen_found_mc = false;
+
        //loops through all MBA chiplets to compare the DRAM technology generation attribute
        l_mbaChiplets.clear();
        l_rc=fapiGetChildChiplets(i_targets[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets, fapi::TARGET_STATE_PRESENT);
@@ -147,12 +154,13 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
 	     }
 	     //if this is the first DIMM that has a valid DRAM Technology level, then set the level and continue
 	     //otherwise throw an error and exit
-	     if(!dram_gen_found) {
+	     if(!dram_gen_found_mc) {
 	        dram_gen = cur_dram_gen;
 		dram_gen_found = true;
+		dram_gen_found_mc = true;
 	     } //end if
 	     else {
-	        //values are not equal -> set the fapi RC and exit out
+	        //values are not equal for one given centaur -> set the fapi RC and exit out
     	  	if(cur_dram_gen != dram_gen){
     	  	   // this just needs to be deconfiged at the dimm level
     	  	   const uint8_t &DRAM_GEN_MISCOMPARE = cur_dram_gen;
@@ -163,9 +171,23 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     	  	   FAPI_ERR("Not all DRAM technology generations are the same.\nExiting....");
     	  	   return l_rc;
     	  	}//end if
+		//is a DDR4 type, go and set the DDR4 flag -> means that the vpp offset flag will be set
+		if(cur_dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
+		   dram_gen_ddr4 = true;
+		}
 	     }//end else
 	  }
        }//end for
+
+       //if a DRAM gen was not found for this MC, then assume that this is a DDR4 DIMM to err on the side of caution
+       //please note: dram_gen_ddr4 flag is not set here intentionally, this is because the voltage offset is only desirable if a card is confirmed as DDR4
+       if(!dram_gen_found_mc) {
+          dram_gen_vector.push_back(fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4);
+       }
+       //otherwise, do the current DRAM gen for the card
+       else {
+          dram_gen_vector.push_back(cur_dram_gen);
+       }
     }//end for
     
     //found a bad VPD
@@ -189,7 +211,7 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     }
     
     //checks to see if the DIMMs are DDR3 DIMMs if so, return 0 and exit
-    if(dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
+    if(!dram_gen_ddr4) {
        uint32_t param_vpp_voltage_mv = 0; 
        //debug output statement
        FAPI_INF("ATTR_MSS_VPP_OFFSET: %d",param_vpp_voltage_mv);
@@ -210,9 +232,9 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     if(enable == fapi::ENUM_ATTR_MSS_VPP_OFFSET_DISABLE_DISABLE) return l_rc;
 
     //gets the slope and intercepts
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE,NULL,vpp_slope); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE,&i_targets[0],vpp_slope);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE_INTERCEPT,NULL,vpp_intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE_INTERCEPT,&i_targets[0],vpp_intercept);
     if(l_rc) return l_rc;
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
     if((vpp_slope * vpp_intercept) == 0) {
@@ -222,12 +244,15 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
        FAPI_ERR("One or more dynamic VPP attributes is 0.\nExiting....");
        return l_rc;
     }
-    
+
 
     //continues computing VPP for DDR4
     //loops through all DIMMs
     num_chips=0;
     for(uint32_t i=0;i<i_targets.size();i++) {
+       //skips the curent target if it's not DDR4 (no DRAMs drawing power)
+       if(dram_gen_vector[i] != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) continue;
+
        //resets the number of ranks and spares
        l_mbaChiplets.clear();
        l_rc=fapiGetChildChiplets(i_targets[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets, fapi::TARGET_STATE_PRESENT);
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index a78cfdf34..529d5056b 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -2654,7 +2654,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VDD_SLOPE_ACTIVE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID VDD adjustment for ACTIVE parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2663,7 +2663,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VDD_SLOPE_INACTIVE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID VDD adjustment for INACTIVE parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2672,7 +2672,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VDD_SLOPE_INTERCEPT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Intercept value used to determine the dynamic VID VDD adjustment for all parts. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2681,7 +2681,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VCS_SLOPE_ACTIVE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID VCS adjustment for ACTIVE parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2690,7 +2690,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VCS_SLOPE_INACTIVE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID VCS adjustment for INACTIVE parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2699,7 +2699,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VCS_SLOPE_INTERCEPT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Intercept value used to determine the dynamic VID VCS adjustment for all parts. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2708,7 +2708,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VPP_SLOPE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID VPP adjustment for all parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2717,7 +2717,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_VPP_SLOPE_INTERCEPT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Intercept value used to determine the dynamic VID VPP adjustment for all parts. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2726,7 +2726,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_DDR3_VDDR_SLOPE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2735,7 +2735,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_DDR3_VDDR_INTERCEPT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2744,7 +2744,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_DDR4_VDDR_SLOPE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2753,7 +2753,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MSS_DDR4_VDDR_INTERCEPT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2880,7 +2880,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MRW_DDR3_VDDR_MAX_LIMIT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -2889,7 +2889,7 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MRW_DDR4_VDDR_MAX_LIMIT</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV.</description>
     <valueType>uint32</valueType>
     <platInit/>
diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C
index fd22a350b..5c2bf00f6 100644
--- a/src/usr/hwpf/plat/fapiPlatAttributeService.C
+++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C
@@ -1799,6 +1799,211 @@ fapi::ReturnCode fapiPlatGetTpVitlSpyOffsetAttr(
     return l_rc;
 }
 
+fapi::ReturnCode fapiPlatGetMemAttrData (
+                              const fapi::Target * i_pTarget,
+                              const TARGETING::ATTRIBUTE_ID i_attr,
+                              uint32_t & o_val)
+{
+
+    FAPI_DBG("fapiPlatGetMemAttrData: START: i_attr=0x%X", i_attr);
+
+    fapi::ReturnCode l_rc;
+    TARGETING::Target * l_pTgt = NULL;
+
+    do {
+
+        // Get non-FAPI Centaur Target
+        l_rc = getTargetingTarget(i_pTarget, l_pTgt,
+                                  TARGETING::TYPE_MEMBUF);
+
+        if (l_rc)
+        {
+            FAPI_ERR("fapiPlatGetMemAttrData: Error from getTargetingTarget");
+            break;
+        }
+
+        // Get NODE from MEMBUF target
+        TARGETING::TargetHandleList l_nodeList;
+        TARGETING::TargetService& tS = TARGETING::targetService();
+
+        TARGETING::PredicateCTM isaNode(TARGETING::CLASS_ENC,
+                                        TARGETING::TYPE_NODE);
+        tS.getAssociated( l_nodeList,
+                          l_pTgt,
+                          TARGETING::TargetService::PARENT,
+                          TARGETING::TargetService::ALL,
+                          &isaNode);
+
+        // Node list should only have 1 tgt
+        if (l_nodeList.size() != 1 )
+        {
+            FAPI_ERR("fapiPlatGetMemAttrData: expect 1 node %d ",
+                     l_nodeList.size());
+
+            /*@
+             * @errortype
+             * @moduleid     MOD_PLAT_ATTR_SVC_GET_MEM_ATTR_DATA
+             * @reasoncode   RC_NO_SINGLE_NODE
+             * @userdata1    Number of Nodes
+             * @userdata2    MEMBUF Target HUID
+             * @devdesc      fapiPlatGetMemAttrData could not find the single
+             *               node associated with this membuf target
+             */
+            const bool hbSwError = true;
+            errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                MOD_PLAT_ATTR_SVC_GET_MEM_ATTR_DATA,
+                RC_NO_SINGLE_NODE,
+                l_nodeList.size(),
+                TARGETING::get_huid(l_pTgt),
+                hbSwError);
+
+            // Attach the error log to the fapi::ReturnCode
+            l_rc.setPlatError(reinterpret_cast<void *> (l_pError));
+            break;
+        }
+
+        // Get the attribute from the node level
+        // NOTE: Using switch statement to explicitly track the attributes
+        //       that need to do this lookup.
+        bool l_success = false;
+
+        switch ( i_attr )
+        {
+            case TARGETING::ATTR_MSS_CENT_VDD_SLOPE_ACTIVE:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_CENT_VDD_SLOPE_ACTIVE>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_CENT_VDD_SLOPE_INACTIVE:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_CENT_VDD_SLOPE_INACTIVE>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_CENT_VDD_INTERCEPT:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_CENT_VDD_INTERCEPT>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_CENT_VCS_SLOPE_ACTIVE:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_CENT_VCS_SLOPE_ACTIVE>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_CENT_VCS_SLOPE_INACTIVE:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_CENT_VCS_SLOPE_INACTIVE>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_CENT_VCS_INTERCEPT:
+                l_success = l_nodeList[0]->tryGetAttr<
+                            TARGETING::ATTR_MSS_CENT_VCS_INTERCEPT>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_EFF_CONFIG>(o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG>
+                            (o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG>
+                            (o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG
+                        >(o_val);
+                break;
+
+            case TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG>
+                            (o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG>
+                            (o_val);
+                break;
+
+            case TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG
+                        >(o_val);
+                break;
+
+            case TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG:
+                l_success =
+                    l_nodeList[0]->tryGetAttr<
+                        TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG>
+                            (o_val);
+                break;
+
+            default:
+                // Use error creation below
+                l_success = false;
+                break;
+        }
+
+        if (!l_success)
+        {
+            FAPI_ERR("fapiPlatGetMemAttrData: Error from _tryGetAttr");
+
+            /*@
+             *  @errortype
+             *  @moduleid   MOD_PLAT_ATTR_SVC_GET_MEM_ATTR_DATA
+             *  @reasoncode RC_FAILED_TO_ACCESS_ATTRIBUTE
+             *  @userdata1[0:31]  Platform attribute ID
+             *  @userdata1[32:64] MEMBUF Target
+             *  @userdata2  FAPI target type, or NULL if system target
+             *  @devdesc    Failed to get requested attribute.
+             *      Possible causes: Invalid target, attribute not implemented,
+             *          attribute not present on given target, target service
+             *          not initialized
+             */
+            const bool hbSwError = true;
+            errlHndl_t l_pError = new ERRORLOG::ErrlEntry(
+                ERRORLOG::ERRL_SEV_INFORMATIONAL,
+                MOD_PLAT_ATTR_SVC_GET_MEM_ATTR_DATA,
+                RC_FAILED_TO_ACCESS_ATTRIBUTE,
+                TWO_UINT32_TO_UINT64(
+                    i_attr,
+                    TARGETING::get_huid(l_pTgt)),
+                i_pTarget ? i_pTarget->getType(): NULL,
+                hbSwError);
+            l_rc.setPlatError(reinterpret_cast<void *>(l_pError));
+        }
+
+    } while (0);
+
+    FAPI_DBG("fapiPlatGetMemAttrData: EXIT: i_attr=0x%X --> o_val = %d (0x%X)",
+             i_attr, o_val, o_val);
+
+    return l_rc;
+
+}
+
 } // End platAttrSvc namespace
 
 } // End fapi namespace
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index e07d21d4d..a720c4441 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -156,6 +156,7 @@ my $sysPolicy = parse_xml_file($system_policy_file,
 my $reqPol = $sysPolicy->{"required-policy-settings"};
 
 my @systemAttr; # Repeated {ATTR, VAL, ATTR, VAL, ATTR, VAL...}
+my @nodeAttr; # Repeated {ATTR, VAL, ATTR, VAL, ATTR, VAL...}
 
 #No mirroring supported yet so the policy is just based on multi-node or not
 my $placement = 0x0; #NORMAL
@@ -316,66 +317,86 @@ if ($MAXNODE > 1 && $sysname !~ m/mfg/)
 my $optMrwPolicies = $sysPolicy->{"optional-policy-settings"};
 use constant MRW_NAME => 'mrw-name';
 
-my %optTargPolicies = ();
-$optTargPolicies{'MIN_FREQ_MHZ'}{MRW_NAME}
+my %optSysPolicies = ();
+my %optNodePolicies = ();
+
+# Add the optional system-level attributes
+$optSysPolicies{'MIN_FREQ_MHZ'}{MRW_NAME}
     = "minimum-frequency" ;
-$optTargPolicies{'NOMINAL_FREQ_MHZ'}{MRW_NAME}
+$optSysPolicies{'NOMINAL_FREQ_MHZ'}{MRW_NAME}
     = "nominal-frequency" ;
-$optTargPolicies{'FREQ_CORE_MAX'}{MRW_NAME}
+$optSysPolicies{'FREQ_CORE_MAX'}{MRW_NAME}
     = "maximum-frequency" ;
-$optTargPolicies{'MSS_CENT_AVDD_OFFSET_DISABLE'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_AVDD_OFFSET_DISABLE'}{MRW_NAME}
     = "mem_avdd_offset_disable" ;
-$optTargPolicies{'MSS_CENT_VDD_OFFSET_DISABLE'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_VDD_OFFSET_DISABLE'}{MRW_NAME}
     = "mem_vdd_offset_disable" ;
-$optTargPolicies{'MSS_CENT_VCS_OFFSET_DISABLE'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_VCS_OFFSET_DISABLE'}{MRW_NAME}
     = "mem_vcs_offset_disable" ;
-$optTargPolicies{'MSS_VOLT_VPP_OFFSET_DISABLE'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_VPP_OFFSET_DISABLE'}{MRW_NAME}
     = "mem_vpp_offset_disable" ;
-$optTargPolicies{'MSS_VOLT_VDDR_OFFSET_DISABLE'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_VDDR_OFFSET_DISABLE'}{MRW_NAME}
     = "mem_vddr_offset_disable" ;
-$optTargPolicies{'MSS_CENT_AVDD_SLOPE_ACTIVE'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_AVDD_SLOPE_ACTIVE'}{MRW_NAME}
     = "mem_avdd_slope_active" ;
-$optTargPolicies{'MSS_CENT_AVDD_SLOPE_INACTIVE'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_AVDD_SLOPE_INACTIVE'}{MRW_NAME}
     = "mem_avdd_slope_inactive" ;
-$optTargPolicies{'MSS_CENT_AVDD_INTERCEPT'}{MRW_NAME}
+$optSysPolicies{'MSS_CENT_AVDD_INTERCEPT'}{MRW_NAME}
     = "mem_avdd_intercept" ;
-$optTargPolicies{'MSS_CENT_VDD_SLOPE_ACTIVE'}{MRW_NAME}
-    = "mem_vdd_slope_active" ;
-$optTargPolicies{'MSS_CENT_VDD_SLOPE_INACTIVE'}{MRW_NAME}
-    = "mem_vdd_slope_inactive" ;
-$optTargPolicies{'MSS_CENT_VDD_INTERCEPT'}{MRW_NAME}
-    = "mem_vdd_intercept" ;
-$optTargPolicies{'MSS_CENT_VCS_SLOPE_ACTIVE'}{MRW_NAME}
-    = "mem_vcs_slope_active" ;
-$optTargPolicies{'MSS_CENT_VCS_SLOPE_INACTIVE'}{MRW_NAME}
-    = "mem_vcs_slope_inactive" ;
-$optTargPolicies{'MSS_CENT_VCS_INTERCEPT'}{MRW_NAME}
-    = "mem_vcs_intercept" ;
-$optTargPolicies{'MSS_VOLT_VPP_SLOPE'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_VPP_SLOPE'}{MRW_NAME}
     = "mem_vpp_slope" ;
-$optTargPolicies{'MSS_VOLT_VPP_INTERCEPT'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_VPP_INTERCEPT'}{MRW_NAME}
     = "mem_vpp_intercept" ;
-$optTargPolicies{'MSS_VOLT_DDR3_VDDR_SLOPE'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_DDR3_VDDR_SLOPE'}{MRW_NAME}
     = "mem_ddr3_vddr_slope" ;
-$optTargPolicies{'MSS_VOLT_DDR3_VDDR_INTERCEPT'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_DDR3_VDDR_INTERCEPT'}{MRW_NAME}
     = "mem_ddr3_vddr_intercept" ;
-$optTargPolicies{'MSS_VOLT_DDR4_VDDR_SLOPE'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_DDR4_VDDR_SLOPE'}{MRW_NAME}
     = "mem_ddr4_vddr_slope" ;
-$optTargPolicies{'MSS_VOLT_DDR4_VDDR_INTERCEPT'}{MRW_NAME}
+$optSysPolicies{'MSS_VOLT_DDR4_VDDR_INTERCEPT'}{MRW_NAME}
     = "mem_ddr4_vddr_intercept" ;
-$optTargPolicies{'MRW_DDR3_VDDR_MAX_LIMIT'}{MRW_NAME}
+$optSysPolicies{'MRW_DDR3_VDDR_MAX_LIMIT'}{MRW_NAME}
     = "mem_ddr3_vddr_max_limit" ;
-$optTargPolicies{'MRW_DDR4_VDDR_MAX_LIMIT'}{MRW_NAME}
+$optSysPolicies{'MRW_DDR4_VDDR_MAX_LIMIT'}{MRW_NAME}
     = "mem_ddr4_vddr_max_limit" ;
 
-foreach my $policy ( keys %optTargPolicies )
+
+# Add the optional node-level attributes
+$optNodePolicies{'MSS_CENT_VDD_SLOPE_ACTIVE'}{MRW_NAME}
+    = "mem_vdd_slope_active" ;
+$optNodePolicies{'MSS_CENT_VDD_SLOPE_INACTIVE'}{MRW_NAME}
+    = "mem_vdd_slope_inactive" ;
+$optNodePolicies{'MSS_CENT_VDD_INTERCEPT'}{MRW_NAME}
+    = "mem_vdd_intercept" ;
+$optNodePolicies{'MSS_CENT_VCS_SLOPE_ACTIVE'}{MRW_NAME}
+    = "mem_vcs_slope_active" ;
+$optNodePolicies{'MSS_CENT_VCS_SLOPE_INACTIVE'}{MRW_NAME}
+    = "mem_vcs_slope_inactive" ;
+$optNodePolicies{'MSS_CENT_VCS_INTERCEPT'}{MRW_NAME}
+    = "mem_vcs_intercept" ;
+
+
+# Add System Attributes
+foreach my $policy ( keys %optSysPolicies )
 {
-    if(exists $optMrwPolicies->{ $optTargPolicies{$policy}{MRW_NAME}})
+    if(exists $optMrwPolicies->{ $optSysPolicies{$policy}{MRW_NAME}})
     {
         push @systemAttr, [ $policy ,
-          $optMrwPolicies->{$optTargPolicies{$policy}{MRW_NAME}}];
+          $optMrwPolicies->{$optSysPolicies{$policy}{MRW_NAME}}];
     }
 }
+
+# Add Node Attribues
+foreach my $policy ( keys %optNodePolicies )
+{
+    if(exists $optMrwPolicies->{ $optNodePolicies{$policy}{MRW_NAME}})
+    {
+        push @nodeAttr, [ $policy ,
+          $optMrwPolicies->{$optNodePolicies{$policy}{MRW_NAME}}];
+    }
+}
+
+
 #OpenPOWER policies
 foreach my $policy (keys %{$optMrwPolicies->{"open_power"}})
 {
@@ -2672,6 +2693,9 @@ sub generate_system_node
         <default>instance:$computeNodeList{$node}->{'instancePath'}</default>
     </compileAttribute>";
 
+    print "    <!-- Node Attributes from MRW -->\n";
+    addNodeAttrs();
+
         # $TODO RTC:110399
         # hardcode for now both palmetto and habenaro are
         # currently the same - this will change though
@@ -4962,6 +4986,33 @@ sub addSysAttrs
     }
 }
 
+sub addNodeAttrs
+{
+    for my $i (0 .. $#nodeAttr)
+    {
+        my $j =0;
+        my $nodeAttrArraySize=$#{$nodeAttr[$i]};
+        while ($j<$nodeAttrArraySize)
+        {
+            # nodeAttr is an array of pairs
+            #  even index is the attribute id
+            #  odd index has its default value
+            my $l_default = $nodeAttr[$i][$j+1];
+            if (substr($l_default,0,2) eq "0b") #convert bin to hex
+            {
+                $l_default = sprintf('0x%X', oct($l_default));
+            }
+            print "    <attribute>\n";
+            print "        <id>$nodeAttr[$i][$j]</id>\n";
+            print "        <default>$l_default</default>\n";
+            print "    </attribute>\n";
+            $j+=2; # next attribute id and default pair
+        }
+    }
+}
+
+
+
 sub addProcPmAttrs
 {
     my ($position,$nodeId) = @_;
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 5d777827e..81aad3ee5 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -12878,6 +12878,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_VRM_VOFFSET_VDD</id>
         <macro>DIRECT</macro>
@@ -12899,6 +12900,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_VRM_VOFFSET_VCS</id>
         <macro>DIRECT</macro>
@@ -12946,6 +12948,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_R_LOADLINE_VDD</id>
         <macro>DIRECT</macro>
@@ -12967,6 +12970,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_R_LOADLINE_VCS</id>
         <macro>DIRECT</macro>
@@ -12988,6 +12992,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_R_DISTLOSS_VDD</id>
         <macro>DIRECT</macro>
@@ -13009,6 +13014,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_R_DISTLOSS_VCS</id>
         <macro>DIRECT</macro>
@@ -14159,10 +14165,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VDD_SLOPE_ACTIVE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14176,10 +14179,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VDD_SLOPE_INACTIVE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14193,10 +14193,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VDD_SLOPE_INTERCEPT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14210,10 +14207,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VCS_SLOPE_ACTIVE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14227,10 +14221,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VCS_SLOPE_INACTIVE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14244,10 +14235,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VCS_SLOPE_INTERCEPT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14261,10 +14249,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VPP_SLOPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
@@ -14278,13 +14262,66 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VPP_SLOPE_INTERCEPT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
+    <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id>
+    <description>Units: uV/DRAM
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id>
+    <description>Units: uV/DRAM
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+
+<attribute>
     <id>MSS_VOLT_DDR3_VDDR_SLOPE</id>
     <description>Units: 1/Amps
     </description>
@@ -14295,10 +14332,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DDR3_VDDR_SLOPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
@@ -14312,10 +14345,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DDR3_VDDR_INTERCEPT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
@@ -14330,10 +14359,92 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MRW_DDR3_VDDR_MAX_LIMIT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id>
+    <description>Units: 1/Amps
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id>
+    <description>Maximum voltage limit for the dynamic VID DDR3 VDDR
+        voltage setpoint. In mV.
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id>
+    <description>Units: 1/Amps
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id>
+    <description>Maximum voltage limit for the dynamic VID DDR3 VDDR
+        voltage setpoint. In mV.
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
 </attribute>
 
 <attribute>
@@ -14347,10 +14458,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DDR4_VDDR_SLOPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
@@ -14364,10 +14471,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DDR4_VDDR_INTERCEPT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
 </attribute>
 
 <attribute>
@@ -14382,10 +14485,92 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MRW_DDR4_VDDR_MAX_LIMIT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id>
+    <description>Units: 1/Amps
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id>
+    <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage
+        setpoint. In mV.
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id>
+    <description>Units: 1/Amps
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id>
+    <description>Units: mV
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id>
+    <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage
+        setpoint. In mV.
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
 </attribute>
 
 <attribute>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index e85502f92..0d1de1f5a 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -263,12 +263,6 @@
     <attribute><id>MSS_CENT_AVDD_SLOPE_ACTIVE</id></attribute>
     <attribute><id>MSS_CENT_AVDD_SLOPE_INACTIVE</id></attribute>
     <attribute><id>MSS_CENT_AVDD_INTERCEPT</id></attribute>
-    <attribute><id>MSS_CENT_VDD_SLOPE_ACTIVE</id></attribute>
-    <attribute><id>MSS_CENT_VDD_SLOPE_INACTIVE</id></attribute>
-    <attribute><id>MSS_CENT_VDD_INTERCEPT</id></attribute>
-    <attribute><id>MSS_CENT_VCS_SLOPE_ACTIVE</id></attribute>
-    <attribute><id>MSS_CENT_VCS_SLOPE_INACTIVE</id></attribute>
-    <attribute><id>MSS_CENT_VCS_INTERCEPT</id></attribute>
     <attribute><id>MSS_VOLT_VPP_SLOPE</id></attribute>
     <attribute><id>MSS_VOLT_VPP_INTERCEPT</id></attribute>
     <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE</id></attribute>
@@ -920,6 +914,28 @@
     <attribute><id>TPM_BACKUP_INFO</id></attribute>
     <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute>
     <attribute><id>VPD_REC_NUM</id></attribute>
+    <attribute><id>MSS_CENT_VDD_SLOPE_ACTIVE</id></attribute>
+    <attribute><id>MSS_CENT_VDD_SLOPE_INACTIVE</id></attribute>
+    <attribute><id>MSS_CENT_VDD_INTERCEPT</id></attribute>
+    <attribute><id>MSS_CENT_VCS_SLOPE_ACTIVE</id></attribute>
+    <attribute><id>MSS_CENT_VCS_SLOPE_INACTIVE</id></attribute>
+    <attribute><id>MSS_CENT_VCS_INTERCEPT</id></attribute>
+    <attribute><id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute>
+    <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute>
+    <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute>
+    <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute>
+    <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute>
+    <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute>
+    <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute>
+    <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute>
+    <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute>
 </targetType>
 
 <targetType>