ZZ VPD Pass 4 Board Update

- Split both ZZ and ZZ_lab folder trees
- Update ZZ VPD files with new MR and MT settings
- Update README.md
- Update gen_vpd.pl
- Introduce BIAS_TRIM attribute
- Add to hb_temp_defaults.xml
- Added enums for ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS
- Modify DQ Map for port swizzling
- Typo Fixes
- Added previousLayoutValue identifier
- MR swap mcs 2 and 3
- New TSYS values

Change-Id: I71f007298853658338a9b25fd8592520c6408b1c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44100
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: FEIHONG YAN <fyan@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: FEIHONG YAN <fyan@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44189
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>

9 files changed, 2064 insertions, 1035 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index f9c12454a..232d8fd7b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -21382,6 +21382,28 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Default value for 2N Mode from Signal Integrity. 0x01 = 1N Mode , 0x02 = 2N
+/// Mode
+///
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t& o_value)
+{
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, o_value) );
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
@@ -23230,69 +23252,69 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
+/// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
+/// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
+/// cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23303,80 +23325,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15,
+                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15,
+                            l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23387,80 +23409,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16,
+                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16,
+                            l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23471,80 +23493,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14,
+                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
 /// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23555,80 +23577,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
-/// cycle of
+/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
+/// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
-/// cycle of
+/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
+/// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one
-/// cycle of
+/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
+/// of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23639,80 +23661,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2:
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15,
-                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15,
-                            l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23723,80 +23745,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Targ
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16,
-                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16,
-                            l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23807,80 +23829,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Targ
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14,
-                            i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+                            l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of
-/// one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23891,80 +23913,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Targe
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
-/// of one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
-/// of one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128
-/// of one cycle of
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
+/// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -23975,80 +23997,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24059,80 +24081,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24143,12 +24165,12 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
@@ -24322,7 +24344,7 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
@@ -24331,24 +24353,24 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
@@ -24357,25 +24379,25 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
@@ -24384,7 +24406,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24395,18 +24417,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
@@ -24415,24 +24437,24 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
@@ -24441,25 +24463,25 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
@@ -24468,7 +24490,7 @@ fapi_try_exit:
 /// 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24479,80 +24501,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24563,80 +24585,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are
-/// 1/128 of one cycle of
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
+/// are 1/128 of one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24647,80 +24669,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24731,80 +24753,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24815,80 +24837,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24899,80 +24921,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(i_target)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t& o_value)
 {
     uint8_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
                             l_value) );
     o_value = l_value[mss::index(l_mca)];
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks
-/// are 1/128 of one cycle of
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of
+/// one cycle of
 /// clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t* o_array)
 {
     if (o_array == nullptr)
@@ -24983,34 +25005,12 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fa
 
     uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value) );
     memcpy(o_array, &l_value, 2);
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)",
-             uint64_t(fapi2::current_err), mss::c_str(i_target));
-    return fapi2::current_err;
-}
-
-///
-/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter
-/// @param[in] const ref to the TARGET_TYPE_MCS
-/// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Default value for 2N Mode from Signal Integrity. 0x01 = 1N Mode , 0x02 = 2N
-/// Mode
-///
-inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t& o_value)
-{
-
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, o_value) );
-    return fapi2::current_err;
-
-fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
@@ -25839,6 +25839,88 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is
+/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 =
+/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum
+/// power)
+///
+inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is
+/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 =
+/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum
+/// power)
+///
+inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is
+/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 =
+/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum
+/// power)
+///
+inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint32_t
@@ -27295,9 +27377,9 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
-/// in draminit_mc. Default is
-/// 0
+/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in
+/// this file is 2's compliment
+/// hex
 ///
 inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, int16_t& o_value)
 {
@@ -27320,9 +27402,9 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
-/// in draminit_mc. Default is
-/// 0
+/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in
+/// this file is 2's compliment
+/// hex
 ///
 inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, int16_t& o_value)
 {
@@ -27346,9 +27428,9 @@ fapi_try_exit:
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
-/// in draminit_mc. Default is
-/// 0
+/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in
+/// this file is 2's compliment
+/// hex
 ///
 inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, int16_t* o_array)
 {
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
index 62ab40dc5..f34eac317 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -30,16 +30,14 @@
 
 #include <fapi2.H>
 
-#include <mss.H>
 #include <lib/shared/mss_const.H>
 #include <lib/mss_utils.H>
+#include <lib/mss_attribute_accessors.H>
 
 namespace mss
 {
 namespace decoder
 {
-
-// VPD Keyword Version Byte: 00
 ///
 /// @brief ATTR_MSS_VPD_MT_0_VERSION_LAYOUT decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
@@ -50,11 +48,15 @@ namespace decoder
 inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
-    uint8_t l_value;
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 0;
+
+    memcpy(&l_value, i_blobs[0] + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blobs[0] + 0, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_0_VERSION_LAYOUT start: 0, len: 1");
+              "Unable to decode and set ATTR_MSS_VPD_MT_0_VERSION_LAYOUT start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -70,11 +72,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
-    uint8_t l_value;
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 1;
+
+    memcpy(&l_value, i_blobs[0] + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blobs[0] + 1, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_1_VERSION_DATA start: 1, len: 1");
+              "Unable to decode and set ATTR_MSS_VPD_MT_1_VERSION_DATA start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -90,12 +96,16 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
-    uint32_t l_value;
+    uint32_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 4;
+    constexpr uint64_t l_offset = 2;
 
-    memcpy(&l_value, i_blobs[0] + 2, 4);
+    memcpy(&l_value, i_blobs[0] + l_offset, l_num_bytes_to_copy);
     l_value = be32toh(l_value);
+
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_2_SIGNATURE_HASH start: 2, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_2_SIGNATURE_HASH start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -117,18 +127,23 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target<fapi2::TARGE
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2];
-    constexpr uint64_t l_length = 4 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2] = {};
+    constexpr uint64_t l_start = 6;
+    constexpr uint64_t l_length = 4;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 6 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA start: 6, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -150,18 +165,23 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target<fapi2::TARG
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2];
-    constexpr uint64_t l_length = 4 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2] = {};
+    constexpr uint64_t l_start = 10;
+    constexpr uint64_t l_length = 4;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 10 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE start: 10, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -183,18 +203,23 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target<fapi2::TARGE
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2];
-    constexpr uint64_t l_length = 4 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2] = {};
+    constexpr uint64_t l_start = 14;
+    constexpr uint64_t l_length = 4;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 14 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS start: 14, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -216,18 +241,23 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target<fapi2::TARG
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2];
-    constexpr uint64_t l_length = 4 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2] = {};
+    constexpr uint64_t l_start = 18;
+    constexpr uint64_t l_length = 4;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 18 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT start: 18, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -249,18 +279,23 @@ inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target<fapi2::T
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    constexpr uint64_t l_start = 22;
+    constexpr uint64_t l_length = 16;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 22 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS start: 22, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -282,18 +317,23 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target<fapi2::TARGET_T
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    constexpr uint64_t l_start = 38;
+    constexpr uint64_t l_length = 16;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 38 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_NOM start: 38, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_NOM start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -315,18 +355,23 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target<fapi2::TARGET_
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    constexpr uint64_t l_start = 54;
+    constexpr uint64_t l_length = 16;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 54 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_PARK start: 54, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_PARK start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -348,18 +393,81 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target<fapi2::TARGET_TY
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    constexpr uint64_t l_start = 70;
+    constexpr uint64_t l_length = 16;
+
+    constexpr uint64_t l_num_bytes_to_copy = l_length / mss::PORTS_PER_MCS;
 
     for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
     {
         const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 70 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        const uint64_t l_offset = l_start + (l_index * l_num_bytes_to_copy);
+
+        memcpy(&(l_value[l_index][0][0]), l_blob + l_offset, l_num_bytes_to_copy);
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_WR start: 70, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_DRAM_RTT_WR start: %d, len: %d for %s", l_start, l_length,
+              mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM decode and set (array)
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is 3.
+/// [VPD Value] = [Binary bit value set in register]
+/// 0 = 110 (Minimal power)
+/// 1 = 010
+/// 2 = 100
+/// 3 = 000 (Default)
+/// 4 = 111
+/// 5 = 011
+/// 6 = 101
+/// 7 = 001 (Maximum power)
+///
+inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        const std::vector<uint8_t*>& i_blobs)
+{
+    if (i_blobs.size() != mss::PORTS_PER_MCS)
+    {
+        FAPI_ERR("%s found vpd blob vector with incorrect number of elements %d", mss::c_str(i_target), i_blobs.size());
+        fapi2::Assert(false);
+    }
+
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_max_layout_version = 1;
+
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version));
+
+    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    {
+        constexpr uint64_t l_offset = 86;
+        constexpr uint64_t l_num_bytes_to_copy = 2;
+        constexpr uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        if( l_layer_version == l_max_layout_version)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+        else
+        {
+            // setting this to default value from VPD template
+            constexpr uint64_t l_prev_layout_val = 0x03;
+            l_value[l_index] = l_prev_layout_val;
+        }
+    }
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_BIAS_TRIM for %s", mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -391,14 +499,42 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::T
         fapi2::Assert(false);
     }
 
-    uint32_t l_value[2];
-    constexpr uint64_t l_length = 8 / mss::PORTS_PER_MCS;
+    uint32_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 86 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 86;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        case 1:
+            l_offset = 88;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -407,7 +543,8 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target<fapi2::T
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP start: 86, len: 8");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -439,14 +576,42 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2:
         fapi2::Assert(false);
     }
 
-    uint32_t l_value[2];
-    constexpr uint64_t l_length = 8 / mss::PORTS_PER_MCS;
+    uint32_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 94 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 94;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        case 1:
+            l_offset = 96;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -455,7 +620,8 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target<fapi2:
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN start: 94, len: 8");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -487,14 +653,42 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::T
         fapi2::Assert(false);
     }
 
-    uint32_t l_value[2];
-    constexpr uint64_t l_length = 8 / mss::PORTS_PER_MCS;
+    uint32_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 102 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 102;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        case 1:
+            l_offset = 104;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -503,7 +697,8 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target<fapi2::T
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP start: 102, len: 8");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -533,14 +728,42 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET
         fapi2::Assert(false);
     }
 
-    uint64_t l_value[2];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint64_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 110 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 110;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        case 1:
+            l_offset = 112;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -549,7 +772,8 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target<fapi2::TARGET
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP start: 110, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -579,14 +803,42 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET
         fapi2::Assert(false);
     }
 
-    uint64_t l_value[2];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint64_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 126 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 126;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        case 1:
+            l_offset = 128;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -595,7 +847,8 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target<fapi2::TARGET
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES start: 126, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -617,18 +870,47 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 142 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 142;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 144;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK start: 142, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -650,18 +932,47 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::T
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 144 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 144;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 146;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR start: 144, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -683,18 +994,47 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGE
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 146 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 146;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 148;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL start: 146, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -716,18 +1056,47 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARG
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 148 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 148;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 150;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID start: 148, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -749,18 +1118,47 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target<fapi2::TAR
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][5];
-    constexpr uint64_t l_length = 10 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][5] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 150 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 150;
+            l_num_bytes_to_copy = 10;
+            break;
+
+        case 1:
+            l_offset = 152;
+            l_num_bytes_to_copy = 10;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS start: 150, len: 10");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -782,18 +1180,47 @@ inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TAR
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][5];
-    constexpr uint64_t l_length = 10 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][5] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 160 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 160;
+            l_num_bytes_to_copy = 10;
+            break;
+
+        case 1:
+            l_offset = 162;
+            l_num_bytes_to_copy = 10;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index][0]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS start: 160, len: 10");
+              "Unable to decode and set ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -804,7 +1231,8 @@ fapi_try_exit:
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  READ, On Die Termination triggering bitmap.
+/// @note  READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
+/// The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A]
 ///
 inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
                                        const std::vector<uint8_t*>& i_blobs)
@@ -815,18 +1243,47 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MC
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 170 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 170;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        case 1:
+            l_offset = 172;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_ODT_RD start: 170, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_ODT_RD start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -837,7 +1294,8 @@ fapi_try_exit:
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  WRITE, On Die Termination triggering bitmap.
+/// @note  WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
+/// The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A]
 ///
 inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
                                        const std::vector<uint8_t*>& i_blobs)
@@ -848,18 +1306,47 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MC
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2][2][4];
-    constexpr uint64_t l_length = 16 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2][2][4] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 186 + (l_index * l_length);
-        memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 186;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        case 1:
+            l_offset = 188;
+            l_num_bytes_to_copy = 16;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index][0][0]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_ODT_WR start: 186, len: 16");
+              "Unable to decode and set ATTR_MSS_VPD_MT_ODT_WR start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -871,7 +1358,8 @@ fapi_try_exit:
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option.
-/// "0" means 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b 00010001
+/// The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble.
+/// E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE
 ///
 inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
@@ -882,18 +1370,47 @@ inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 202 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 202;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 204;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_PREAMBLE start: 202, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_PREAMBLE start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -915,18 +1432,47 @@ inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target<fapi2::TARGET_T
         fapi2::Assert(false);
     }
 
-    uint8_t l_value[2];
-    constexpr uint64_t l_length = 2 / mss::PORTS_PER_MCS;
+    uint8_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 204 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 204;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        case 1:
+            l_offset = 206;
+            l_num_bytes_to_copy = 2;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_VREF_DRAM_WR start: 204, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MT_VREF_DRAM_WR start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -948,14 +1494,42 @@ inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYP
         fapi2::Assert(false);
     }
 
-    uint32_t l_value[2];
-    constexpr uint64_t l_length = 8 / mss::PORTS_PER_MCS;
+    uint32_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 206 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 206;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        case 1:
+            l_offset = 208;
+            l_num_bytes_to_copy = 8;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -964,7 +1538,8 @@ inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target<fapi2::TARGET_TYP
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_VREF_MC_RD start: 206, len: 8");
+              "Unable to decode and set ATTR_MSS_VPD_MT_VREF_MC_RD start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -975,7 +1550,8 @@ fapi_try_exit:
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr in draminit_mc. Default is 0
+/// @note  Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. Default is 0
+/// Specification of the value in this file is 2's compliment hex
 ///
 inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
@@ -986,14 +1562,42 @@ inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET
         fapi2::Assert(false);
     }
 
-    int16_t l_value[2];
-    constexpr uint64_t l_length = 4 / mss::PORTS_PER_MCS;
+    int16_t l_value[2] = {};
+    uint64_t l_num_bytes_to_copy = 0;
+    uint64_t l_offset = 0;
 
-    for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+    uint8_t l_layer_version = 0;
+    FAPI_TRY( mss::vpd_mt_0_version_layout(i_target, l_layer_version) );
+
+    switch(l_layer_version)
     {
-        const uint8_t* l_blob = i_blobs[l_index];
-        const uint64_t l_start = 214 + (l_index * l_length);
-        memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        case 0:
+            l_offset = 214;
+            l_num_bytes_to_copy = 4;
+            break;
+
+        case 1:
+            l_offset = 216;
+            l_num_bytes_to_copy = 4;
+            break;
+
+        default:
+            FAPI_ERR("Invalid layer version received: %d for %s", l_layer_version, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+
+    };
+
+    {
+        const uint64_t l_length = l_num_bytes_to_copy / mss::PORTS_PER_MCS;
+
+        for (size_t l_index = 0; l_index < mss::PORTS_PER_MCS; ++l_index)
+        {
+            const uint8_t* l_blob = i_blobs[l_index];
+            const uint64_t l_start = l_offset + (l_index * l_length);
+            memcpy(&(l_value[l_index]), l_blob + l_start, l_length);
+        }
+
     }
 
     for (size_t i = 0; i < 2; ++i)
@@ -1002,14 +1606,62 @@ inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET
     }
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MT_WINDAGE_RD_CTR start: 214, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MT_WINDAGE_RD_CTR start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
+///
+/// @brief ATTR_MSS_VPD_CKE_MAP decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank.
+/// There are 8 bits, but only 4 are currently used
+/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A]
+/// E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank.
+///
+inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value[2][2][4] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 16;
+    constexpr uint64_t l_offset = 0;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_CKE_MAP, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_CKE_MAP start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_DQ_MAP decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  [PORT][Dimm DQ PIN]  The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout
+///
+inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value[2][72] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 144;
+    constexpr uint64_t l_offset = 0;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_DQ_MAP, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_DQ_MAP start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
-// VPD Keyword Version Byte: 00
 ///
 /// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
@@ -1020,11 +1672,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value;
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 0;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 0, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_0_VERSION_LAYOUT start: 0, len: 1");
+              "Unable to decode and set ATTR_MSS_VPD_MR_0_VERSION_LAYOUT start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1040,11 +1696,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value;
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 1;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 1, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_1_VERSION_DATA start: 1, len: 1");
+              "Unable to decode and set ATTR_MSS_VPD_MR_1_VERSION_DATA start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1060,12 +1720,16 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint32_t l_value;
+    uint32_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 4;
+    constexpr uint64_t l_offset = 2;
 
-    memcpy(&l_value, i_blob + 2, 4);
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
     l_value = be32toh(l_value);
+
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_2_SIGNATURE_HASH start: 2, len: 4");
+              "Unable to decode and set ATTR_MSS_VPD_MR_2_SIGNATURE_HASH start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1080,11 +1744,15 @@ fapi_try_exit:
 ///
 inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 6;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 6, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_GPO start: 6, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_GPO start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1099,11 +1767,15 @@ fapi_try_exit:
 ///
 inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 8;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 8, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_RLO start: 8, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_RLO start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1118,11 +1790,40 @@ fapi_try_exit:
 ///
 inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 10;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 10, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_WLO start: 10, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_WLO start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  Default value for 2N Mode from Signal Integrity.
+/// 0x01 = 1N Mode , 0x02 = 2N Mode
+///
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        const uint8_t* i_blob)
+{
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 98;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1138,11 +1839,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 12;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 12, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 start: 12, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1158,11 +1863,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 14;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 14, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 start: 14, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1178,11 +1887,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 16;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 16, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 start: 16, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1198,11 +1911,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 18;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 18, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 start: 18, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1218,11 +1935,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 20;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 20, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 start: 20, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1238,11 +1959,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 22;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 22, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 start: 22, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1258,11 +1983,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 24;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 24, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 start: 24, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1278,11 +2007,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 26;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 26, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 start: 26, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1298,11 +2031,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 28;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 28, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 start: 28, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1318,11 +2055,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 30;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 30, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 start: 30, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1338,11 +2079,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 32;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 32, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 start: 32, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1358,11 +2103,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 34;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 34, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 start: 34, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1378,11 +2127,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 36;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 36, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 start: 36, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1398,11 +2151,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 38;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 38, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 start: 38, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1418,11 +2175,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 40;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 40, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 start: 40, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1438,11 +2199,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 42;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 42, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 start: 42, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1458,11 +2223,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 44;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 44, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 start: 44, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1478,11 +2247,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 46;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 46, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 start: 46, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1498,11 +2271,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 48;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 48, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 start: 48, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1518,11 +2295,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 50;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 50, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 start: 50, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1538,11 +2319,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 52;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 52, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 start: 52, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1558,231 +2343,279 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 54;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 54, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 start: 54, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 64;
 
-    memcpy(&l_value, i_blob + 56, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP start: 56, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 66;
 
-    memcpy(&l_value, i_blob + 58, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN start: 58, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 68;
 
-    memcpy(&l_value, i_blob + 60, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP start: 60, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 70;
 
-    memcpy(&l_value, i_blob + 62, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN start: 62, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 72;
 
-    memcpy(&l_value, i_blob + 64, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN start: 64, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 74;
 
-    memcpy(&l_value, i_blob + 66, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 start: 66, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 76;
 
-    memcpy(&l_value, i_blob + 68, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 start: 68, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 82;
 
-    memcpy(&l_value, i_blob + 70, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 start: 70, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 84;
 
-    memcpy(&l_value, i_blob + 72, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR start: 72, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 90;
 
-    memcpy(&l_value, i_blob + 74, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 start: 74, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 92;
 
-    memcpy(&l_value, i_blob + 76, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 start: 76, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1798,11 +2631,15 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 78;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 78, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 start: 78, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1818,192 +2655,207 @@ fapi_try_exit:
 inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 80;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 80, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 start: 80, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
-
-    memcpy(&l_value, i_blob + 82, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 start: 82, len: 2");
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 86;
 
-///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[in] i_blob the VPD blob for this MCS
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
-///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        const uint8_t* i_blob)
-{
-    uint8_t l_value[2];
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 84, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 start: 84, len: 2");
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 88;
 
-    memcpy(&l_value, i_blob + 86, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 start: 86, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 94;
 
-    memcpy(&l_value, i_blob + 88, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 start: 88, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 96;
 
-    memcpy(&l_value, i_blob + 90, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 start: 90, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 58;
 
-    memcpy(&l_value, i_blob + 92, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 start: 92, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 56;
 
-    memcpy(&l_value, i_blob + 94, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 start: 94, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 62;
 
-    memcpy(&l_value, i_blob + 96, 2);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 start: 96, len: 2");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET decode and set
+/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Default value for 2N Mode from Signal Integrity.
-/// 0x01 = 1N Mode , 0x02 = 2N Mode
+/// @note  Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
 ///
-inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value;
+    uint8_t l_value[2] = {};
+    constexpr uint64_t l_num_bytes_to_copy = 2;
+    constexpr uint64_t l_offset = 60;
 
-    memcpy(&l_value, i_blob + 98, 1);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET start: 98, len: 1");
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP start: %d, len: %d for %s", l_offset,
+              l_num_bytes_to_copy, mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -2021,11 +2873,15 @@ fapi_try_exit:
 ///
 inline fapi2::ReturnCode vpd_mr_tsys_adr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
-    uint8_t l_value;
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 99;
+
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-    memcpy(&l_value, i_blob + 99, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_TSYS_ADR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_ADR start: 99, len: 1");
+              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_ADR start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -2043,56 +2899,15 @@ fapi_try_exit:
 ///
 inline fapi2::ReturnCode vpd_mr_tsys_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
 {
-    uint8_t l_value;
-
-    memcpy(&l_value, i_blob + 100, 1);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_DATA start: 100, len: 1");
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
-
-
-// VPD Keyword Version Byte: map
-///
-/// @brief ATTR_MSS_VPD_CKE_MAP decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[in] i_blob the VPD blob for this MCS
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank.
-/// There are 8 bits, but only 4 are currently used
-/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A]
-/// E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank.
-///
-inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
-{
-    uint8_t l_value[2][2][4];
-
-    memcpy(&l_value, i_blob + 0, 16);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_CKE_MAP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_CKE_MAP start: 0, len: 16");
-
-fapi_try_exit:
-    return fapi2::current_err;
-}
+    uint8_t l_value = 0;
+    constexpr uint64_t l_num_bytes_to_copy = 1;
+    constexpr uint64_t l_offset = 100;
 
+    memcpy(&l_value, i_blob + l_offset, l_num_bytes_to_copy);
 
-// VPD Keyword Version Byte: map
-///
-/// @brief ATTR_MSS_VPD_DQ_MAP decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[in] i_blob the VPD blob for this MCS
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  [PORT][Dimm DQ PIN]  The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout
-///
-inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
-{
-    uint8_t l_value[2][72];
-
-    memcpy(&l_value, i_blob + 0, 144);
-    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_DQ_MAP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_DQ_MAP start: 0, len: 144");
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_DATA start: %d, len: %d for %s", l_offset, l_num_bytes_to_copy,
+              mss::c_str(i_target));
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -2109,7 +2924,10 @@ fapi_try_exit:
 /// @note Decodes the blobs and sets all the attributes.
 ///
 inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-                                    const std::vector<uint8_t*>& i_mt_blob, const uint8_t* i_mr_blob, const uint8_t* i_cke_blob, const uint8_t* i_dq_blob)
+                                    const std::vector<uint8_t*>& i_mt_blob,
+                                    const uint8_t* i_mr_blob,
+                                    const uint8_t* i_cke_blob,
+                                    const uint8_t* i_dq_blob)
 {
     FAPI_TRY (decoder::vpd_mt_0_version_layout(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_1_version_data(i_target, i_mt_blob) );
@@ -2122,6 +2940,7 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mt_dram_rtt_nom(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_dram_rtt_park(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_dram_rtt_wr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_mc_bias_trim(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_rd_up(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_wr_down(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_mc_dq_acboost_wr_up(i_target, i_mt_blob) );
@@ -2139,12 +2958,15 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mt_vref_dram_wr(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_vref_mc_rd(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_windage_rd_ctr(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_cke_map(i_target, i_cke_blob) );
+    FAPI_TRY (decoder::vpd_dq_map(i_target, i_dq_blob) );
     FAPI_TRY (decoder::vpd_mr_0_version_layout(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_1_version_data(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_2_signature_hash(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_dphy_gpo(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_dphy_rlo(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_dphy_wlo(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_2n_mode_autoset(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a00(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a01(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a02(i_target, i_mr_blob) );
@@ -2167,10 +2989,6 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c1(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_c2(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkp(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkn(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkp(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkn(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_actn(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_casn_a15(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(i_target, i_mr_blob) );
@@ -2178,21 +2996,22 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cmd_par(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_cke0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_cke1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke1(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_csn0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_csn1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn0(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn1(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_odt0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d0_odt1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_cke1(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn0(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_csn1(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt1(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_mc_2n_mode_autoset(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkn(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d0_clkp(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkn(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_mc_phase_rot_d1_clkp(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_tsys_adr(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_tsys_data(i_target, i_mr_blob) );
-    FAPI_TRY (decoder::vpd_cke_map(i_target, i_cke_blob) );
-    FAPI_TRY (decoder::vpd_dq_map(i_target, i_dq_blob) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -2200,4 +3019,4 @@ fapi_try_exit:
 
 
 } // close ns mss
-#endif
+#endif
\ No newline at end of file
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
index 7f6e51222..a2274cc5f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
@@ -36,6 +36,7 @@
 #include <lib/utils/fake_vpd.H>
 #include <lib/shared/mss_const.H>
 #include <generic/memory/lib/utils/pos.H>
+#include <generic/memory/lib/utils/c_str.H>
 
 #ifndef DOXYGEN
 
@@ -44,7 +45,7 @@ namespace mss
 
 // VPD data from template_mt and template_mr - should be VBU/sim settings
 constexpr auto raw_mt_size = 255;
-static constexpr uint8_t raw_mt[raw_mt_size] =
+static constexpr uint8_t raw_mt_layout_ver0[raw_mt_size] =
 {
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a,
     0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
@@ -64,8 +65,34 @@ static constexpr uint8_t raw_mt[raw_mt_size] =
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
 
+static constexpr uint8_t zz_ver1_raw_bin_zz_mt_X0_bin[raw_mt_size] =
+{
+    0x01, 0x01, 0x86, 0xb8, 0x63, 0xa8, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a,
+    0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x22, 0x22,
+    0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
+    0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00,
+    0x55, 0x55, 0x55, 0x55, 0x55, 0x00, 0x00, 0x00, 0xb6, 0xdb, 0x6d, 0xb6,
+    0xdb, 0x6d, 0xb6, 0xd0, 0xb6, 0xdb, 0x6d, 0xb6, 0xdb, 0x6d, 0xb6, 0xd0,
+    0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x22, 0x22, 0x22, 0x22,
+    0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c,
+    0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x0d, 0x0d, 0x00, 0x01, 0x17, 0x44, 0x00, 0x01, 0x17, 0x44,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00
+};
+
 constexpr auto raw_mr_size = 255;
-static constexpr uint8_t raw_mr[raw_mr_size] =
+static constexpr uint8_t raw_mr_layout_ver0[raw_mr_size] =
 {
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x01, 0x01, 0x01, 0x01, 0x03, 0x08, 0x03, 0x06,
     0x03, 0x09, 0x04, 0x04, 0x00, 0x01, 0x01, 0x00, 0x04, 0x02, 0x03, 0x00, 0x06, 0x0a, 0x02, 0x01,
@@ -85,13 +112,13 @@ static constexpr uint8_t raw_mr[raw_mr_size] =
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
 
-// The CKE blob has a header on it, and we want to return a pointer past that. Howevre, to
+// The CKE blob has a header on it, and we want to return a pointer past that. However, to
 // make creating this file easier we take the entire blob (header included)
 // Note:: ZZ (and hence Monza?) CKE mapping is the same for VBU - so only one mapping needed
-constexpr auto raw_cke_header = 4;
-constexpr auto raw_cke_size = 136;
+constexpr auto raw_ck_size = 136;
+constexpr auto raw_ck_header = 4;
 
-static constexpr uint8_t raw_cke[raw_cke_size] =
+static constexpr uint8_t raw_ck[raw_ck_size] =
 {
     0x01, 0x08, 0x10, 0x00, 0x80, 0x40, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x80, 0x40, 0x00, 0x00,
     0x08, 0x04, 0x00, 0x00, 0x80, 0x40, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x80, 0x40, 0x00, 0x00,
@@ -181,25 +208,149 @@ static constexpr uint8_t zz_dq[MCS_PER_MC * MC_PER_MODULE][raw_dq_size] =
 };
 
 ///
-/// @brief Return a blob of memory VPD data associated with the input target
-/// @param[in] i_target     a valid fapi2 target
-/// @param[in] io_vpd_info  fapi2::VPDInfo class that specifies which piece of data to return
-/// @param[out] o_blob      the blob of raw data from the vpd
-/// @return FAPI2_RC_SUCCESS if there's no problem
+/// @brief VPD helper function that imitates getVPD behavior
+/// @tparam N size of the input array
+/// @param[in] i_raw_vpd array of VPD data
+/// @param[in,out] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of data from the DIMM - raw
 /// @note passing nullptr for o_blob will return the size of the keyword
 ///
-/// Example:
-/// fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS> vpdInfo(MR_keyword);
-/// vpdInfo.iv_freq = 2667;
+template< size_t N >
+void vpd_helper( const uint8_t (&i_raw_vpd)[N],
+                 fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                 uint8_t* o_blob)
+{
+    io_vpd_info.iv_size = sizeof( i_raw_vpd );
+
+    if( o_blob != nullptr )
+    {
+        memcpy( o_blob, i_raw_vpd, io_vpd_info.iv_size );
+    }
+
+    return;
+}
+
 ///
-/// uint8_t * blob = NULL;
+/// @brief Helper function to retrieve MT raw data
+/// @param[in] i_target a valid fapi2 target
+/// @param[in] i_version_layout version layout number
+/// @param[in,out] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of raw data from the vpd
+/// @note passing nullptr for o_blob will return the size of the keyword
 ///
-/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
-/// blob = static_cast<uint8_t *>(malloc(vpdInfo.iv_size));
-/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
-/// blob now contains the VPD data for the MCS.
+void mt_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                const uint64_t i_version_layout,
+                fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                uint8_t* o_blob )
+{
+    switch(i_version_layout)
+    {
+        case 0:
+            vpd_helper(raw_mt_layout_ver0, io_vpd_info, o_blob);
+            break;
+
+        case 1:
+            vpd_helper(zz_ver1_raw_bin_zz_mt_X0_bin, io_vpd_info, o_blob);
+            break;
+
+        default:
+            FAPI_ERR("Invalid layout version layout received %d for %s", i_version_layout, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+    };
+
+    return;
+}
+
+///
+/// @brief Helper function to retrieve MR raw data
+/// @param[in] i_target a valid fapi2 target
+/// @param[in] i_version_layout version layout number
+/// @param[in,out] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of raw data from the vpd
+/// @note passing nullptr for o_blob will return the size of the keyword
+///
+void mr_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                const uint64_t i_version_layout,
+                fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                uint8_t* o_blob )
+{
+    switch(i_version_layout)
+    {
+        case 0:
+            vpd_helper(raw_mr_layout_ver0, io_vpd_info, o_blob);
+            break;
+
+        default:
+            FAPI_ERR("Invalid layout version layout received %d for %s", i_version_layout, mss::c_str(i_target));
+            fapi2::Assert(false);
+            break;
+    };
+
+    return;
+}
+
+///
+/// @brief Helper function to retrieve CK raw data
+/// @param[in] i_target a valid fapi2 target
+/// @param[in,out] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of raw data from the vpd
+/// @note passing nullptr for o_blob will return the size of the keyword
+///
+static void ck_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                       fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                       uint8_t* o_blob )
+{
+    io_vpd_info.iv_size = raw_ck_size - raw_ck_header;
+
+    if (o_blob != nullptr)
+    {
+        memcpy(o_blob, raw_ck + raw_ck_header, io_vpd_info.iv_size);
+    }
+}
+
+///
+/// @brief Helper function to retrieve DQ raw data
+/// @param[in] i_target a valid fapi2 target
+/// @param[in,out] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of raw data from the vpd
+/// @note passing nullptr for o_blob will return the size of the keyword
+///
+static fapi2::ReturnCode dq_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                                    fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                                    uint8_t* o_blob )
+{
+    io_vpd_info.iv_size = raw_dq_size;
+
+    if (o_blob != nullptr)
+    {
+        uint8_t l_sim = 0;
+        FAPI_TRY( is_simulation(l_sim) );
+
+        // If we're in sim, we return the DQ map of the VBU (raw) DQ map - 1-1 more or less
+        // If we're not in sim, we return the DQ map which corresponds with our MCS relative
+        // postion.
+        const uint8_t* blob = l_sim ? raw_dq : zz_dq[mss::relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(i_target)];
+        memcpy(o_blob, blob, io_vpd_info.iv_size);
+    }
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Return a blob of memory VPD data associated with the input target
+/// @param[in] i_target a valid fapi2 target
+/// @param[in] i_version_layout version layout number
+/// @param[in] io_vpd_info fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob the blob of raw data from the vpd
+/// @return FAPI2_RC_SUCCESS if there's no problem
+/// @note passing nullptr for o_blob will return the size of the keyword
 ///
 fapi2::ReturnCode getVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                         const uint64_t i_version_layout,
                          fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
                          uint8_t* o_blob)
 {
@@ -207,60 +358,30 @@ fapi2::ReturnCode getVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
     switch (io_vpd_info.iv_vpd_type)
     {
         case fapi2::MemVpdData::MR:
-            io_vpd_info.iv_size = raw_mr_size;
-
-            if (o_blob != nullptr)
-            {
-                memcpy(o_blob, raw_mr, raw_mr_size);
-            }
-
+            mr_helper(i_target, i_version_layout, io_vpd_info, o_blob);
             break;
 
         case fapi2::MemVpdData::MT:
-            io_vpd_info.iv_size = raw_mt_size;
-
-            if (o_blob != nullptr)
-            {
-                memcpy(o_blob, raw_mt, raw_mt_size);
-            }
-
+            mt_helper(i_target, i_version_layout, io_vpd_info, o_blob);
             break;
 
         case fapi2::MemVpdData::CK:
-            io_vpd_info.iv_size = raw_cke_size - raw_cke_header;
-
-            if (o_blob != nullptr)
-            {
-                memcpy(o_blob, raw_cke + raw_cke_header, io_vpd_info.iv_size);
-            }
-
+            FAPI_INF("CK isn't layout version dependent for %s", mss::c_str(i_target));
+            ck_helper(i_target, io_vpd_info, o_blob);
             break;
 
         case fapi2::MemVpdData::DQ:
-            {
-                io_vpd_info.iv_size = raw_dq_size;
-
-                if (o_blob != nullptr)
-                {
-                    uint8_t l_sim = 0;
-                    FAPI_TRY( is_simulation(l_sim) );
-
-                    // If we're in sim, we return the DQ map of the VBU (raw) DQ map - 1-1 more or less
-                    // Ifwe're not in sim, we return the DQ map which corresponds with our MCS relative
-                    // postion.
-                    const uint8_t* blob = l_sim ? raw_dq : zz_dq[mss::relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(i_target)];
-                    memcpy(o_blob, blob, io_vpd_info.iv_size);
-                }
-            }
+            FAPI_INF("DQ isn't layout version dependent for %s", mss::c_str(i_target));
+            FAPI_TRY( dq_helper(i_target, io_vpd_info, o_blob) );
             break;
 
         case fapi2::MemVpdData::MP:
-            FAPI_ERR("No MP?");
+            FAPI_ERR("No MP? for %s", mss::c_str(i_target));
             return fapi2::FAPI2_RC_INVALID_PARAMETER;
             break;
 
         default:
-            FAPI_ERR("No vpd type %d?", io_vpd_info.iv_vpd_type);
+            FAPI_ERR("No vpd type %d? for %s", io_vpd_info.iv_vpd_type, mss::c_str(i_target));
             return fapi2::FAPI2_RC_INVALID_PARAMETER;
             break;
     };
@@ -269,7 +390,6 @@ fapi2::ReturnCode getVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
 
 fapi_try_exit:
     return fapi2::current_err;
-
 }
 
 } // ns mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
index a39d9412b..bfbd60f20 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -46,23 +46,14 @@ namespace mss
 ///
 /// @brief Return a blob of memory VPD data associated with the input target
 /// @param[in] i_target     a valid fapi2 target
+/// @param[in] i_version_layout version layout number
 /// @param[in] io_vpd_info  fapi2::VPDInfo class that specifies which piece of data to return
 /// @param[out] o_blob      the blob of raw data from the vpd
 /// @return FAPI2_RC_SUCCESS if there's no problem
 /// @note passing nullptr for o_blob will return the size of the keyword
 ///
-/// Example:
-/// fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS> vpdInfo(MR_keyword);
-/// vpdInfo.iv_freq = 2667;
-///
-/// uint8_t * blob = NULL;
-///
-/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
-/// blob = static_cast<uint8_t *>(malloc(vpdInfo.iv_size));
-/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
-/// blob now contains the VPD data for the MCS.
-///
 fapi2::ReturnCode getVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                         const uint64_t i_version_layout,
                          fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
                          uint8_t* o_blob);
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml
index 5c7de669c..de1a6e118 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -35,7 +35,6 @@
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
         <mssBlobStart>0</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
         <mssAccessorName>vpd_cke_map</mssAccessorName>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml
index 2107319a7..977094159 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_dq_attributes.xml
@@ -22,7 +22,6 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-
 <attributes>
 
   <attribute>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
index ff39283f8..32785aade 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -117,6 +117,21 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Default value for 2N Mode from Signal Integrity.
+            0x01 = 1N Mode , 0x02 = 2N Mode
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssBlobStart>98</mssBlobStart>
+        <mssBlobLength>1</mssBlobLength>
+        <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
+    </attribute>
+
+    <attribute>
         <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
@@ -469,178 +484,178 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>56</mssBlobStart>
+        <mssBlobStart>64</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>58</mssBlobStart>
+        <mssBlobStart>66</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>60</mssBlobStart>
+        <mssBlobStart>68</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>62</mssBlobStart>
+        <mssBlobStart>70</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>64</mssBlobStart>
+        <mssBlobStart>72</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>66</mssBlobStart>
+        <mssBlobStart>74</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>68</mssBlobStart>
+        <mssBlobStart>76</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>70</mssBlobStart>
+        <mssBlobStart>82</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>72</mssBlobStart>
+        <mssBlobStart>84</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>74</mssBlobStart>
+        <mssBlobStart>90</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>76</mssBlobStart>
+        <mssBlobStart>92</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
         <array>2</array>
     </attribute>
 
@@ -677,7 +692,7 @@
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
@@ -686,14 +701,14 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>82</mssBlobStart>
+        <mssBlobStart>86</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
@@ -702,125 +717,109 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>84</mssBlobStart>
+        <mssBlobStart>88</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>86</mssBlobStart>
+        <mssBlobStart>94</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>88</mssBlobStart>
+        <mssBlobStart>96</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>90</mssBlobStart>
+        <mssBlobStart>58</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>92</mssBlobStart>
+        <mssBlobStart>56</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>94</mssBlobStart>
+        <mssBlobStart>62</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id>
+        <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>96</mssBlobStart>
+        <mssBlobStart>60</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
+        <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName>
         <array>2</array>
     </attribute>
 
     <attribute>
-        <id>ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET</id>
-        <targetType>TARGET_TYPE_MCS</targetType>
-        <description>
-            Default value for 2N Mode from Signal Integrity.
-            0x01 = 1N Mode , 0x02 = 2N Mode
-        </description>
-        <initToZero></initToZero>
-        <valueType>uint8</valueType>
-        <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>98</mssBlobStart>
-        <mssBlobLength>1</mssBlobLength>
-        <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
-    </attribute>
-
-    <attribute>
         <id>ATTR_MSS_VPD_MR_TSYS_ADR</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
index 49cc606e9..cf3a5a93b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
@@ -62,7 +62,6 @@
         <initToZero></initToZero>
         <valueType>uint32</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
         <mssBlobStart>2</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
         <mssAccessorName>vpd_mt_2_signature_hash</mssAccessorName>
@@ -205,6 +204,30 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_VPD_MT_MC_BIAS_TRIM</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is 3.
+            [VPD Value] = [Binary bit value set in register]
+            0 = 110 (Minimal power)
+            1 = 010
+            2 = 100
+            3 = 000 (Default)
+            4 = 111
+            5 = 011
+            6 = 101
+            7 = 001 (Maximum power)
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssBlobStart>86</mssBlobStart>
+        <mssBlobLength>2</mssBlobLength>
+        <mssAccessorName>vpd_mt_mc_bias_trim</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
         <id>ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
@@ -223,8 +246,7 @@
         <initToZero></initToZero>
         <valueType>uint32</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>86</mssBlobStart>
+        <mssBlobStart>88</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_dq_acboost_rd_up</mssAccessorName>
         <array>2</array>
@@ -249,8 +271,7 @@
         <initToZero></initToZero>
         <valueType>uint32</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>94</mssBlobStart>
+        <mssBlobStart>96</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_dq_acboost_wr_down</mssAccessorName>
         <array>2</array>
@@ -275,8 +296,7 @@
         <initToZero></initToZero>
         <valueType>uint32</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>102</mssBlobStart>
+        <mssBlobStart>104</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_dq_acboost_wr_up</mssAccessorName>
         <array>2</array>
@@ -299,8 +319,7 @@
         <initToZero></initToZero>
         <valueType>uint64</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>110</mssBlobStart>
+        <mssBlobStart>112</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_dq_ctle_cap</mssAccessorName>
         <array>2</array>
@@ -323,8 +342,7 @@
         <initToZero></initToZero>
         <valueType>uint64</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>126</mssBlobStart>
+        <mssBlobStart>128</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_dq_ctle_res</mssAccessorName>
         <array>2</array>
@@ -341,7 +359,7 @@
         <writeable/>
         <enum>OHM30 = 30, OHM40 = 40</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>142</mssBlobStart>
+        <mssBlobStart>144</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_drv_imp_clk</mssAccessorName>
         <array>2</array>
@@ -358,7 +376,7 @@
         <writeable/>
         <enum>OHM30 = 30, OHM40 = 40</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>144</mssBlobStart>
+        <mssBlobStart>146</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_drv_imp_cmd_addr</mssAccessorName>
         <array>2</array>
@@ -375,7 +393,7 @@
         <writeable/>
         <enum>OHM30 = 30, OHM40 = 40</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>146</mssBlobStart>
+        <mssBlobStart>148</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_drv_imp_cntl</mssAccessorName>
         <array>2</array>
@@ -392,7 +410,7 @@
         <writeable/>
         <enum>OHM30 = 30, OHM40 = 40</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>148</mssBlobStart>
+        <mssBlobStart>150</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_drv_imp_cscid</mssAccessorName>
         <array>2</array>
@@ -409,7 +427,7 @@
         <writeable/>
         <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>150</mssBlobStart>
+        <mssBlobStart>152</mssBlobStart>
         <mssBlobLength>10</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_drv_imp_dq_dqs</mssAccessorName>
         <array>2 5</array>
@@ -426,7 +444,7 @@
         <writeable/>
         <enum>DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum>
         <mssUnits>ohm</mssUnits>
-        <mssBlobStart>160</mssBlobStart>
+        <mssBlobStart>162</mssBlobStart>
         <mssBlobLength>10</mssBlobLength>
         <mssAccessorName>vpd_mt_mc_rcv_imp_dq_dqs</mssAccessorName>
         <array>2 5</array>
@@ -442,8 +460,7 @@
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>170</mssBlobStart>
+        <mssBlobStart>172</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
         <mssAccessorName>vpd_mt_odt_rd</mssAccessorName>
         <array>2 2 4</array>
@@ -459,8 +476,7 @@
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>186</mssBlobStart>
+        <mssBlobStart>188</mssBlobStart>
         <mssBlobLength>16</mssBlobLength>
         <mssAccessorName>vpd_mt_odt_wr</mssAccessorName>
         <array>2 2 4</array>
@@ -478,7 +494,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>nCK</mssUnits>
-        <mssBlobStart>202</mssBlobStart>
+        <mssBlobStart>204</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_preamble</mssAccessorName>
         <array>2</array>
@@ -493,8 +509,7 @@
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
-        <mssUnits></mssUnits>
-        <mssBlobStart>204</mssBlobStart>
+        <mssBlobStart>206</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mt_vref_dram_wr</mssAccessorName>
         <array>2</array>
@@ -511,7 +526,7 @@
         <writeable/>
         <enum>VDD91875 = 91875, VDD91333 = 91333, VDD90791 = 90791, VDD90250 = 90250, VDD89708 = 89708, VDD89166 = 89166, VDD88625 = 88625, VDD88083 = 88083, VDD87541 = 87541, VDD87000 = 87000, VDD86458 = 86458, VDD85916 = 85916, VDD85375 = 85375, VDD84833 = 84833, VDD84291 = 84291, VDD83750 = 83750, VDD83208 = 83208, VDD82666 = 82666, VDD82125 = 82125, VDD81583 = 81583, VDD81041 = 81041, VDD80500 = 80500, VDD79958 = 79958, VDD79416 = 79416, VDD78875 = 78875, VDD78333 = 78333, VDD77791 = 77791, VDD77250 = 77250, VDD76708 = 76708, VDD76166 = 76166, VDD75625 = 75625, VDD75083 = 75083, VDD74541 = 74541, VDD74000 = 74000, VDD73458 = 73458, VDD72916 = 72916, VDD72375 = 72375, VDD71833 = 71833, VDD71291 = 71291, VDD70750 = 70750, VDD70208 = 70208, VDD69666 = 69666, VDD69125 = 69125, VDD68583 = 68583, VDD68041 = 68041, VDD67500 = 67500, VDD66958 = 66958, VDD66416 = 66416, VDD65875 = 65875, VDD65333 = 65333, VDD64791 = 64791, VDD64250 = 64250, VDD63708 = 63708, VDD63166 = 63166, VDD62625 = 62625, VDD62083 = 62083, VDD61541 = 61541, VDD61000 = 61000, VDD60458 = 60458, VDD59916 = 59916, VDD59375 = 59375, VDD58833 = 58833, VDD58291 = 58291, VDD57750 = 57750, VDD57208 = 57208, VDD56666 = 56666, VDD56125 = 56125, VDD55583 = 55583, VDD55041 = 55041, VDD54500 = 54500, VDD53958 = 53958, VDD53416 = 53416, VDD52875 = 52875, VDD52333 = 52333, VDD51791 = 51791, VDD51250 = 51250, VDD50708 = 50708, VDD50166 = 50166, VDD49625 = 49625, VDD49083 = 49083, VDD48541 = 48541, VDD48000 = 48000, VDD47458 = 47458, VDD46916 = 46916, VDD46375 = 46375, VDD45833 = 45833, VDD45291 = 45291, VDD44750 = 44750, VDD44208 = 44208, VDD43666 = 43666, VDD43125 = 43125, VDD42583 = 42583, VDD42041 = 42041, VDD41500 = 41500, VDD40958 = 40958, VDD40416 = 40416, VDD39875 = 39875, VDD39333 = 39333, VDD38791 = 38791, VDD38250 = 38250, VDD37708 = 37708, VDD37166 = 37166, VDD36625 = 36625, VDD36083 = 36083, VDD35541 = 35541, VDD35000 = 35000, VDD34458 = 34458, VDD33916 = 33916, VDD33375 = 33375, VDD32833 = 32833, VDD32291 = 32291, VDD31750 = 31750, VDD31208 = 31208</enum>
         <mssUnits>percent of Vdd</mssUnits>
-        <mssBlobStart>206</mssBlobStart>
+        <mssBlobStart>208</mssBlobStart>
         <mssBlobLength>8</mssBlobLength>
         <mssAccessorName>vpd_mt_vref_mc_rd</mssAccessorName>
         <array>2</array>
@@ -521,13 +536,14 @@
         <id>ATTR_MSS_VPD_MT_WINDAGE_RD_CTR</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr in draminit_mc. Default is 0
+            Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. Default is 0
+            Specification of the value in this file is 2's compliment hex
         </description>
         <initToZero></initToZero>
         <valueType>int16</valueType>
         <writeable/>
         <mssUnits>signed</mssUnits>
-        <mssBlobStart>214</mssBlobStart>
+        <mssBlobStart>216</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
         <mssAccessorName>vpd_mt_windage_rd_ctr</mssAccessorName>
         <array>2</array>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index 3c927243d..94f00ac24 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -337,6 +337,10 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_VPD_MT_MC_BIAS_TRIM</id>
+    </attribute>
+
+    <attribute>
         <id>ATTR_CORE_INSIDE_SPECIAL_WAKEUP</id>
         <default>0x00</default>
     </attribute>
@@ -349,7 +353,7 @@
     <attribute>
         <id>ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE</id>
         <default>0x00</default>
-    </attribute>    
+    </attribute>
 
 <!-- =====================================================================
      End of temporary definitions