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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-10-06 14:38:51 +0200 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-10-09 14:41:29 -0400 |
| commit | afc07df37efc00a3532704331c209ec069361902 (patch) | |
| tree | c447b3dec4d2c41a7ae8d6998ed0bd70b4b8ebb9 | |
| parent | d2822317832d3caee9de11ba900d01777b25f2ce (diff) | |
| download | blackbird-hostboot-afc07df37efc00a3532704331c209ec069361902.tar.gz blackbird-hostboot-afc07df37efc00a3532704331c209ec069361902.zip | |
p9_sbe_chiplet_reset: Set VITL_AL flag for MC chiplets
There is a phase sync signal between the Nest and MC chiplets that is
only needed for combined synchronous LBIST of the inter-chiplet interface,
but can disrupt scanning in async MC operation. So it should be masked in
normal operation by setting the VITL_AL flag in NET_CTRL0.
Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251
CQ: HW422475
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: LENNARD G. STREAT <lstreat@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48058
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index e52f2dc86..df5caef09 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -63,6 +63,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + NET_CNTL0_SET_VITL_AL = 0x0020000000000000ull, HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, HANG_PULSE_0X06 = 0x06, |
