Add support for Venice in PRD rule files.

Change-Id: I53cf9771e328a93304cfa4cfa61c8defecaf21fb
RTC: 62713
CMVC-Coreq: 874444
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3758
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Christopher T. Phan <cphan@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4513

5 files changed, 767 insertions, 36 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc.rule
index aaec466ed..82c09a2a7 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc.rule
@@ -201,17 +201,17 @@ group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit
     /** GLOBAL_FIR[17]
      *  Attention from EX1 (Venice only)
      */
-    (GlobalFir, bit(17)) ? defaultMaskedError;
+    (GlobalFir, bit(17)) ? analyzeEx1;
 
     /** GLOBAL_FIR[18]
      *  Attention from EX2 (Venice only)
      */
-    (GlobalFir, bit(18)) ? defaultMaskedError;
+    (GlobalFir, bit(18)) ? analyzeEx2;
 
     /** GLOBAL_FIR[19]
      *  Attention from EX3 (Venice only)
      */
-    (GlobalFir, bit(19)) ? defaultMaskedError;
+    (GlobalFir, bit(19)) ? analyzeEx3;
 
     /** GLOBAL_FIR[20]
      *  Attention from EX4
@@ -231,17 +231,17 @@ group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit
     /** GLOBAL_FIR[25]
      *  Attention from EX9 (Venice only)
      */
-    (GlobalFir, bit(25)) ? defaultMaskedError;
+    (GlobalFir, bit(25)) ? analyzeEx9;
 
     /** GLOBAL_FIR[26]
      *  Attention from EX10 (Venice only)
      */
-    (GlobalFir, bit(26)) ? defaultMaskedError;
+    (GlobalFir, bit(26)) ? analyzeEx10;
 
     /** GLOBAL_FIR[27]
      *  Attention from EX11 (Venice only)
      */
-    (GlobalFir, bit(27)) ? defaultMaskedError;
+    (GlobalFir, bit(27)) ? analyzeEx11;
 
     /** GLOBAL_FIR[28]
      *  Attention from EX12
@@ -284,17 +284,17 @@ group gGlobalSpa attntype SPECIAL filter singlebit
     /** GLOBAL_SPA[11]
      *  Attention from EX1 (Venice only)
      */
-    (GlobalSpa, bit(11)) ? defaultMaskedError;
+    (GlobalSpa, bit(11)) ? analyzeEx1;
 
     /** GLOBAL_SPA[12]
      *  Attention from EX2 (Venice only)
      */
-    (GlobalSpa, bit(12)) ? defaultMaskedError;
+    (GlobalSpa, bit(12)) ? analyzeEx2;
 
     /** GLOBAL_SPA[13]
      *  Attention from EX3 (Venice only)
      */
-    (GlobalSpa, bit(13)) ? defaultMaskedError;
+    (GlobalSpa, bit(13)) ? analyzeEx3;
 
     /** GLOBAL_SPA[14]
      *  Attention from EX4
@@ -314,17 +314,17 @@ group gGlobalSpa attntype SPECIAL filter singlebit
     /** GLOBAL_SPA[19]
      *  Attention from EX9 (Venice only)
      */
-    (GlobalSpa, bit(19)) ? defaultMaskedError;
+    (GlobalSpa, bit(19)) ? analyzeEx9;
 
     /** GLOBAL_SPA[20]
      *  Attention from EX10 (Venice only)
      */
-    (GlobalSpa, bit(20)) ? defaultMaskedError;
+    (GlobalSpa, bit(20)) ? analyzeEx10;
 
     /** GLOBAL_SPA[21]
      *  Attention from EX11 (Venice only)
      */
-    (GlobalSpa, bit(21)) ? defaultMaskedError;
+    (GlobalSpa, bit(21)) ? analyzeEx11;
 
     /** GLOBAL_SPA[22]
      *  Attention from EX12
@@ -368,6 +368,15 @@ group gGlobalSpa attntype SPECIAL filter singlebit
 #                          Analyze Connected Parts                             #
 ################################################################################
 
+/** Analyze connected EX1 */
+actionclass analyzeEx1 { analyze(connected(TYPE_EX, 1)); };
+
+/** Analyze connected EX2 */
+actionclass analyzeEx2 { analyze(connected(TYPE_EX, 2)); };
+
+/** Analyze connected EX3 */
+actionclass analyzeEx3 { analyze(connected(TYPE_EX, 3)); };
+
 /** Analyze connected EX4 */
 actionclass analyzeEx4 { analyze(connected(TYPE_EX, 4)); };
 
@@ -377,6 +386,15 @@ actionclass analyzeEx5 { analyze(connected(TYPE_EX, 5)); };
 /** Analyze connected EX6 */
 actionclass analyzeEx6 { analyze(connected(TYPE_EX, 6)); };
 
+/** Analyze connected EX9 */
+actionclass analyzeEx9 { analyze(connected(TYPE_EX, 9)); };
+
+/** Analyze connected EX10 */
+actionclass analyzeEx10 { analyze(connected(TYPE_EX, 10)); };
+
+/** Analyze connected EX11 */
+actionclass analyzeEx11 { analyze(connected(TYPE_EX, 11)); };
+
 /** Analyze connected EX12 */
 actionclass analyzeEx12 { analyze(connected(TYPE_EX, 12)); };
 
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule
index b608daf9a..130676bad 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule
@@ -48,22 +48,22 @@ group gTpChipletFir filter singlebit
     /** TP_CHIPLET_FIR[5]
      *  Attention from MCIFIR (MCS 00 Venice only)
      */
-    (TpChipletFir, bit(5)) ? defaultMaskedError;
+    (TpChipletFir, bit(5)) ? analyzeMcs00;
 
     /** TP_CHIPLET_FIR[6]
      *  Attention from MCIFIR (MCS 01 Venice only)
      */
-    (TpChipletFir, bit(6)) ? defaultMaskedError;
+    (TpChipletFir, bit(6)) ? analyzeMcs01;
 
     /** TP_CHIPLET_FIR[7]
      *  Attention from MCIFIR (MCS 10 Venice only)
      */
-    (TpChipletFir, bit(7)) ? defaultMaskedError;
+    (TpChipletFir, bit(7)) ? analyzeMcs10;
 
     /** TP_CHIPLET_FIR[8]
      *  Attention from MCIFIR (MCS 11 Venice only)
      */
-    (TpChipletFir, bit(8)) ? defaultMaskedError;
+    (TpChipletFir, bit(8)) ? analyzeMcs11;
 
     /** TP_CHIPLET_FIR[9]
      *  Attention from MCIFIR (MCS 20)
@@ -126,22 +126,22 @@ group gTpChipletSpa filter singlebit
     /** TP_CHIPLET_SPA[1]
      *  Attention from MCIFIR_00 (Venice only)
      */
-    (TpChipletSpa, bit(1)) ? defaultMaskedError;
+    (TpChipletSpa, bit(1)) ? analyzeMcs00;
 
     /** TP_CHIPLET_SPA[2]
      *  Attention from MCIFIR_01 (Venice only)
      */
-    (TpChipletSpa, bit(2)) ? defaultMaskedError;
+    (TpChipletSpa, bit(2)) ? analyzeMcs01;
 
     /** TP_CHIPLET_SPA[3]
      *  Attention from MCIFIR_10 (Venice only)
      */
-    (TpChipletSpa, bit(3)) ? defaultMaskedError;
+    (TpChipletSpa, bit(3)) ? analyzeMcs10;
 
     /** TP_CHIPLET_SPA[4]
-     *  Attention from MCIFIR_10 (Venice only)
+     *  Attention from MCIFIR_11 (Venice only)
      */
-    (TpChipletSpa, bit(4)) ? defaultMaskedError;
+    (TpChipletSpa, bit(4)) ? analyzeMcs11;
 
     /** TP_CHIPLET_SPA[5]
      *  Attention from MCIFIR_20
@@ -775,6 +775,34 @@ group gPmcFir filter singlebit
 # Actions specific to TP chiplet
 ################################################################################
 
+/** Analyze connected MCS 00 */
+actionclass analyzeMcs00
+{
+    analyze(connected(TYPE_MCS, 0));
+    funccall("MaskMCS00IfCentaurCheckstop");
+};
+
+/** Analyze connected MCS 01 */
+actionclass analyzeMcs01
+{
+    analyze(connected(TYPE_MCS, 1));
+    funccall("MaskMCS01IfCentaurCheckstop");
+};
+
+/** Analyze connected MCS 10 */
+actionclass analyzeMcs10
+{
+    analyze(connected(TYPE_MCS, 2));
+    funccall("MaskMCS10IfCentaurCheckstop");
+};
+
+/** Analyze connected MCS 11 */
+actionclass analyzeMcs11
+{
+    analyze(connected(TYPE_MCS, 3));
+    funccall("MaskMCS11IfCentaurCheckstop");
+};
+
 /** Analyze connected MCS 20 */
 actionclass analyzeMcs20
 {
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule
index 3c45bfc65..9707db90f 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_XBUS.rule
@@ -28,9 +28,9 @@
 rule XbusChipletFir
 {
   CHECK_STOP:
-     (XBUS_CHIPLET_CS_FIR       & `1F80000000000000`) & ~XBUS_CHIPLET_FIR_MASK;
+     (XBUS_CHIPLET_CS_FIR       & `1FC0000000000000`) & ~XBUS_CHIPLET_FIR_MASK;
   RECOVERABLE:
-    ((XBUS_CHIPLET_RE_FIR >> 2) & `1F80000000000000`) & ~XBUS_CHIPLET_FIR_MASK;
+    ((XBUS_CHIPLET_RE_FIR >> 2) & `1FC0000000000000`) & ~XBUS_CHIPLET_FIR_MASK;
 };
 
 group gXbusChipletFir filter singlebit
@@ -48,7 +48,7 @@ group gXbusChipletFir filter singlebit
     /** XbusChipletFir[5]
      *  Attention from IOXFIR_0 (Venice only)
      */
-    (XbusChipletFir, bit(5)) ? defaultMaskedError;
+    (XbusChipletFir, bit(5)) ? analyze(gIoxFir_0);
 
     /** XbusChipletFir[6]
      *  Attention from IOXFIR_1
@@ -58,12 +58,17 @@ group gXbusChipletFir filter singlebit
     /** XbusChipletFir[7]
      *  Attention from IOXFIR_2 (Venice only)
      */
-    (XbusChipletFir, bit(7)) ? defaultMaskedError;
+    (XbusChipletFir, bit(7)) ? analyze(gIoxFir_2);
 
     /** XbusChipletFir[8]
      *  Attention from IOXFIR_3 (Venice only)
      */
-    (XbusChipletFir, bit(8)) ? defaultMaskedError;
+    (XbusChipletFir, bit(8)) ? analyze(gIoxFir_3);
+
+    /** XbusChipletFir[9]
+     *  Attention from PSIFIR (Venice only)
+     */
+    (XbusChipletFir, bit(9)) ? analyze(gXbusPsiFir);
 };
 
 ################################################################################
@@ -253,6 +258,169 @@ group gPbenFir filter singlebit
 };
 
 ################################################################################
+# XBUS Chiplet IOXFIR_0
+################################################################################
+
+rule IoxFir_0
+{
+    CHECK_STOP:  IOXFIR_0 & ~IOXFIR_0_MASK & ~IOXFIR_0_ACT0 & ~IOXFIR_0_ACT1;
+    RECOVERABLE: IOXFIR_0 & ~IOXFIR_0_MASK & ~IOXFIR_0_ACT0 &  IOXFIR_0_ACT1;
+};
+
+group gIoxFir_0 filter singlebit
+{
+    /** IOXFIR_0[0]
+     * FIR_RX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_0, bit(0)) ? defaultMaskedError;
+
+    /** IOXFIR_0[1]
+     * FIR_TX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_0, bit(1)) ? defaultMaskedError;
+
+    /** IOXFIR_0[2]
+     *  FIR_GCR_HANG_ERROR
+     */
+    (IoxFir_0, bit(2)) ? defaultMaskedError;
+
+    /** IOXFIR_0[8]
+     * FIR_RX_BUS0_TRAINING_ERROR
+     */
+    (IoxFir_0, bit(8)) ? defaultMaskedError;
+
+    /** IOXFIR_0[9]
+     *  FIR_RX_BUS0_SPARE_DEPLOYED
+     */
+    (IoxFir_0, bit(9)) ? defaultMaskedError;
+
+    /** IOXFIR_0[10]
+     * FIR_RX_BUS0_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_0, bit(10)) ? defaultMaskedError;
+
+    /** IOXFIR_0[11]
+     * FIR_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_0, bit(11)) ? defaultMaskedError;
+
+    /** IOXFIR_0[12]
+     *  FIR_RX_BUS0_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_0, bit(12)) ? defaultMaskedError;
+
+    /** IOXFIR_0[16]
+     *  FIR_RX_BUS1_TRAINING_ERROR
+     */
+    (IoxFir_0, bit(16)) ? defaultMaskedError;
+
+    /** IOXFIR_0[17]
+     *  FIR_RX_BUS1_SPARE_DEPLOYED
+     */
+    (IoxFir_0, bit(17)) ? defaultMaskedError;
+
+    /** IOXFIR_0[18]
+     *  FIR_RX_BUS1_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_0, bit(18)) ? defaultMaskedError;
+
+    /** IOXFIR_0[19]
+     *  FIR_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_0, bit(19)) ? defaultMaskedError;
+
+    /** IOXFIR_0[20]
+     *  FIR_RX_BUS1_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_0, bit(20)) ? defaultMaskedError;
+
+    /** IOXFIR_0[24]
+     *  FIR_RX_BUS2_TRAINING_ERROR
+     */
+    (IoxFir_0, bit(24)) ? defaultMaskedError;
+
+    /** IOXFIR_0[25]
+     *  FIR_RX_BUS2_SPARE_DEPLOYED
+     */
+    (IoxFir_0, bit(25)) ? defaultMaskedError;
+
+    /** IOXFIR_0[26]
+     *  FIR_RX_BUS2_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_0, bit(26)) ? defaultMaskedError;
+
+    /** IOXFIR_0[27]
+     *  FIR_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_0, bit(27)) ? defaultMaskedError;
+
+    /** IOXFIR_0[28]
+     *  FIR_RX_BUS2_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_0, bit(28)) ? defaultMaskedError;
+
+    /** IOXFIR_0[32]
+     *  FIR_RX_BUS3_TRAINING_ERROR
+     */
+    (IoxFir_0, bit(32)) ? defaultMaskedError;
+
+    /** IOXFIR_0[33]
+     *  FIR_RX_BUS3_SPARE_DEPLOYED
+     */
+    (IoxFir_0, bit(33)) ? defaultMaskedError;
+
+    /** IOXFIR_0[34]
+     *  FIR_RX_BUS3_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_0, bit(34)) ? defaultMaskedError;
+
+    /** IOXFIR_0[35]
+     *  FIR_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_0, bit(35)) ? defaultMaskedError;
+
+    /** IOXFIR_0[36]
+     *  FIR_RX_BUS3_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_0, bit(36)) ? defaultMaskedError;
+
+    /** IOXFIR_0[40]
+     *  FIR_RX_BUS4_TRAINING_ERROR
+     */
+    (IoxFir_0, bit(40)) ? defaultMaskedError;
+
+    /** IOXFIR_0[41]
+     *  FIR_RX_BUS4_SPARE_DEPLOYED
+     */
+    (IoxFir_0, bit(41)) ? defaultMaskedError;
+
+    /** IOXFIR_0[42]
+     *  FIR_RX_BUS4_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_0, bit(42)) ? defaultMaskedError;
+
+    /** IOXFIR_0[43]
+     *  FIR_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_0, bit(43)) ? defaultMaskedError;
+
+    /** IOXFIR_0[44]
+     *  FIR_RX_BUS4_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_0, bit(44)) ? defaultMaskedError;
+
+    /** IOXFIR_0[48]
+     *  FIR_SCOMFIR_ERROR
+     */
+    (IoxFir_0, bit(48)) ? defaultMaskedError;
+
+    /** IOXFIR_0[49]
+     *  FIR_SCOMFIR_ERROR_CLONE
+     */
+    (IoxFir_0, bit(49)) ? defaultMaskedError;
+};
+
+################################################################################
 # XBUS Chiplet IOXFIR_1
 ################################################################################
 
@@ -446,6 +614,357 @@ group gIoxFir_1 filter singlebit
 };
 
 ################################################################################
+# XBUS Chiplet IOXFIR_2
+################################################################################
+
+rule IoxFir_2
+{
+    CHECK_STOP:  IOXFIR_2 & ~IOXFIR_2_MASK & ~IOXFIR_2_ACT0 & ~IOXFIR_2_ACT1;
+    RECOVERABLE: IOXFIR_2 & ~IOXFIR_2_MASK & ~IOXFIR_2_ACT0 &  IOXFIR_2_ACT1;
+};
+
+group gIoxFir_2 filter singlebit
+{
+    /** IOXFIR_2[0]
+     * FIR_RX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_2, bit(0)) ? defaultMaskedError;
+
+    /** IOXFIR_2[1]
+     * FIR_TX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_2, bit(1)) ? defaultMaskedError;
+
+    /** IOXFIR_2[2]
+     *  FIR_GCR_HANG_ERROR
+     */
+    (IoxFir_2, bit(2)) ? defaultMaskedError;
+
+    /** IOXFIR_2[8]
+     * FIR_RX_BUS0_TRAINING_ERROR
+     */
+    (IoxFir_2, bit(8)) ? defaultMaskedError;
+
+    /** IOXFIR_2[9]
+     *  FIR_RX_BUS0_SPARE_DEPLOYED
+     */
+    (IoxFir_2, bit(9)) ? defaultMaskedError;
+
+    /** IOXFIR_2[10]
+     * FIR_RX_BUS0_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_2, bit(10)) ? defaultMaskedError;
+
+    /** IOXFIR_2[11]
+     * FIR_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_2, bit(11)) ? defaultMaskedError;
+
+    /** IOXFIR_2[12]
+     *  FIR_RX_BUS0_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_2, bit(12)) ? defaultMaskedError;
+
+    /** IOXFIR_2[16]
+     *  FIR_RX_BUS1_TRAINING_ERROR
+     */
+    (IoxFir_2, bit(16)) ? defaultMaskedError;
+
+    /** IOXFIR_2[17]
+     *  FIR_RX_BUS1_SPARE_DEPLOYED
+     */
+    (IoxFir_2, bit(17)) ? defaultMaskedError;
+
+    /** IOXFIR_2[18]
+     *  FIR_RX_BUS1_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_2, bit(18)) ? defaultMaskedError;
+
+    /** IOXFIR_2[19]
+     *  FIR_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_2, bit(19)) ? defaultMaskedError;
+
+    /** IOXFIR_2[20]
+     *  FIR_RX_BUS1_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_2, bit(20)) ? defaultMaskedError;
+
+    /** IOXFIR_2[24]
+     *  FIR_RX_BUS2_TRAINING_ERROR
+     */
+    (IoxFir_2, bit(24)) ? defaultMaskedError;
+
+    /** IOXFIR_2[25]
+     *  FIR_RX_BUS2_SPARE_DEPLOYED
+     */
+    (IoxFir_2, bit(25)) ? defaultMaskedError;
+
+    /** IOXFIR_2[26]
+     *  FIR_RX_BUS2_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_2, bit(26)) ? defaultMaskedError;
+
+    /** IOXFIR_2[27]
+     *  FIR_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_2, bit(27)) ? defaultMaskedError;
+
+    /** IOXFIR_2[28]
+     *  FIR_RX_BUS2_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_2, bit(28)) ? defaultMaskedError;
+
+    /** IOXFIR_2[32]
+     *  FIR_RX_BUS3_TRAINING_ERROR
+     */
+    (IoxFir_2, bit(32)) ? defaultMaskedError;
+
+    /** IOXFIR_2[33]
+     *  FIR_RX_BUS3_SPARE_DEPLOYED
+     */
+    (IoxFir_2, bit(33)) ? defaultMaskedError;
+
+    /** IOXFIR_2[34]
+     *  FIR_RX_BUS3_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_2, bit(34)) ? defaultMaskedError;
+
+    /** IOXFIR_2[35]
+     *  FIR_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_2, bit(35)) ? defaultMaskedError;
+
+    /** IOXFIR_2[36]
+     *  FIR_RX_BUS3_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_2, bit(36)) ? defaultMaskedError;
+
+    /** IOXFIR_2[40]
+     *  FIR_RX_BUS4_TRAINING_ERROR
+     */
+    (IoxFir_2, bit(40)) ? defaultMaskedError;
+
+    /** IOXFIR_2[41]
+     *  FIR_RX_BUS4_SPARE_DEPLOYED
+     */
+    (IoxFir_2, bit(41)) ? defaultMaskedError;
+
+    /** IOXFIR_2[42]
+     *  FIR_RX_BUS4_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_2, bit(42)) ? defaultMaskedError;
+
+    /** IOXFIR_2[43]
+     *  FIR_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_2, bit(43)) ? defaultMaskedError;
+
+    /** IOXFIR_2[44]
+     *  FIR_RX_BUS4_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_2, bit(44)) ? defaultMaskedError;
+
+    /** IOXFIR_2[48]
+     *  FIR_SCOMFIR_ERROR
+     */
+    (IoxFir_2, bit(48)) ? defaultMaskedError;
+
+    /** IOXFIR_2[49]
+     *  FIR_SCOMFIR_ERROR_CLONE
+     */
+    (IoxFir_2, bit(49)) ? defaultMaskedError;
+};
+
+################################################################################
+# XBUS Chiplet IOXFIR_3
+################################################################################
+
+rule IoxFir_3
+{
+    CHECK_STOP:  IOXFIR_3 & ~IOXFIR_3_MASK & ~IOXFIR_3_ACT0 & ~IOXFIR_3_ACT1;
+    RECOVERABLE: IOXFIR_3 & ~IOXFIR_3_MASK & ~IOXFIR_3_ACT0 &  IOXFIR_3_ACT1;
+};
+
+group gIoxFir_3 filter singlebit
+{
+    /** IOXFIR_3[0]
+     * FIR_RX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_3, bit(0)) ? defaultMaskedError;
+
+    /** IOXFIR_3[1]
+     * FIR_TX_INVALID_STATE_OR_PARITY_ERROR
+     */
+    (IoxFir_3, bit(1)) ? defaultMaskedError;
+
+    /** IOXFIR_3[2]
+     *  FIR_GCR_HANG_ERROR
+     */
+    (IoxFir_3, bit(2)) ? defaultMaskedError;
+
+    /** IOXFIR_3[8]
+     * FIR_RX_BUS0_TRAINING_ERROR
+     */
+    (IoxFir_3, bit(8)) ? defaultMaskedError;
+
+    /** IOXFIR_3[9]
+     *  FIR_RX_BUS0_SPARE_DEPLOYED
+     */
+    (IoxFir_3, bit(9)) ? defaultMaskedError;
+
+    /** IOXFIR_3[10]
+     * FIR_RX_BUS0_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_3, bit(10)) ? defaultMaskedError;
+
+    /** IOXFIR_3[11]
+     * FIR_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_3, bit(11)) ? defaultMaskedError;
+
+    /** IOXFIR_3[12]
+     *  FIR_RX_BUS0_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_3, bit(12)) ? defaultMaskedError;
+
+    /** IOXFIR_3[16]
+     *  FIR_RX_BUS1_TRAINING_ERROR
+     */
+    (IoxFir_3, bit(16)) ? defaultMaskedError;
+
+    /** IOXFIR_3[17]
+     *  FIR_RX_BUS1_SPARE_DEPLOYED
+     */
+    (IoxFir_3, bit(17)) ? defaultMaskedError;
+
+    /** IOXFIR_3[18]
+     *  FIR_RX_BUS1_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_3, bit(18)) ? defaultMaskedError;
+
+    /** IOXFIR_3[19]
+     *  FIR_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_3, bit(19)) ? defaultMaskedError;
+
+    /** IOXFIR_3[20]
+     *  FIR_RX_BUS1_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_3, bit(20)) ? defaultMaskedError;
+
+    /** IOXFIR_3[24]
+     *  FIR_RX_BUS2_TRAINING_ERROR
+     */
+    (IoxFir_3, bit(24)) ? defaultMaskedError;
+
+    /** IOXFIR_3[25]
+     *  FIR_RX_BUS2_SPARE_DEPLOYED
+     */
+    (IoxFir_3, bit(25)) ? defaultMaskedError;
+
+    /** IOXFIR_3[26]
+     *  FIR_RX_BUS2_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_3, bit(26)) ? defaultMaskedError;
+
+    /** IOXFIR_3[27]
+     *  FIR_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_3, bit(27)) ? defaultMaskedError;
+
+    /** IOXFIR_3[28]
+     *  FIR_RX_BUS2_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_3, bit(28)) ? defaultMaskedError;
+
+    /** IOXFIR_3[32]
+     *  FIR_RX_BUS3_TRAINING_ERROR
+     */
+    (IoxFir_3, bit(32)) ? defaultMaskedError;
+
+    /** IOXFIR_3[33]
+     *  FIR_RX_BUS3_SPARE_DEPLOYED
+     */
+    (IoxFir_3, bit(33)) ? defaultMaskedError;
+
+    /** IOXFIR_3[34]
+     *  FIR_RX_BUS3_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_3, bit(34)) ? defaultMaskedError;
+
+    /** IOXFIR_3[35]
+     *  FIR_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_3, bit(35)) ? defaultMaskedError;
+
+    /** IOXFIR_3[36]
+     *  FIR_RX_BUS3_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_3, bit(36)) ? defaultMaskedError;
+
+    /** IOXFIR_3[40]
+     *  FIR_RX_BUS4_TRAINING_ERROR
+     */
+    (IoxFir_3, bit(40)) ? defaultMaskedError;
+
+    /** IOXFIR_3[41]
+     *  FIR_RX_BUS4_SPARE_DEPLOYED
+     */
+    (IoxFir_3, bit(41)) ? defaultMaskedError;
+
+    /** IOXFIR_3[42]
+     *  FIR_RX_BUS4_MAX_SPARES_EXCEEDED
+     */
+    (IoxFir_3, bit(42)) ? defaultMaskedError;
+
+    /** IOXFIR_3[43]
+     *  FIR_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR
+     */
+    (IoxFir_3, bit(43)) ? defaultMaskedError;
+
+    /** IOXFIR_3[44]
+     *  FIR_RX_BUS4_TOO_MANY_BUS_ERRORS
+     */
+    (IoxFir_3, bit(44)) ? defaultMaskedError;
+
+    /** IOXFIR_3[48]
+     *  FIR_SCOMFIR_ERROR
+     */
+    (IoxFir_3, bit(48)) ? defaultMaskedError;
+
+    /** IOXFIR_3[49]
+     *  FIR_SCOMFIR_ERROR_CLONE
+     */
+    (IoxFir_3, bit(49)) ? defaultMaskedError;
+};
+
+################################################################################
+# XBUS Chiplet PSIFIR
+################################################################################
+
+rule XbusPsiFir
+{
+  CHECK_STOP:
+     XBUS_PSIFIR & ~XBUS_PSIFIR_MASK & ~XBUS_PSIFIR_ACT0 & ~XBUS_PSIFIR_ACT1;
+  RECOVERABLE:
+     XBUS_PSIFIR & ~XBUS_PSIFIR_MASK & ~XBUS_PSIFIR_ACT0 &  XBUS_PSIFIR_ACT1;
+};
+
+group gXbusPsiFir filter singlebit
+{
+    /** XBUS_PSIFIR[5]
+     *  INTERNAL_SCOM_ERROR
+     */
+    (XbusPsiFir, bit(5)) ? defaultMaskedError;
+
+    /** XBUS_PSIFIR[6]
+     *  INTERNAL_SCOM_ERROR_CLONE
+     */
+    (XbusPsiFir, bit(6)) ? defaultMaskedError;
+};
+
+################################################################################
 # Actions specific to XBUS chiplet
 ################################################################################
 
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule
index 15a89ced0..63a000cb4 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule
@@ -122,10 +122,41 @@
     };
 
     ############################################################################
-    # XBUS Chiplet IOXFIR_0
+    # XBUS Chiplet IOXFIR_0 (Venice only)
     ############################################################################
 
-    # Venice only scomaddr = TBD
+   register IOXFIR_0
+   {
+        name        "XBUS01.X0.BUSCTL.SCOM.FIR_REG";
+        scomaddr    0x04011000;
+        reset       (&, 0x04011001);
+        mask        (|, 0x04011005);
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_0_MASK
+    {
+        name        "XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG";
+        scomaddr    0x04011003;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_0_ACT0
+    {
+        name        "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG";
+        scomaddr    0x04011006;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_0_ACT1
+    {
+        name        "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG";
+        scomaddr    0x04011007;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
 
     ############################################################################
     # XBUS Chiplet IOXFIR_1
@@ -133,7 +164,7 @@
 
     register IOXFIR_1
     {
-        name        "XBUS1.BUSCTL.SCOM.FIR_REG";
+        name        "XBUS01.X1.BUSCTL.SCOM.FIR_REG";
         scomaddr    0x04011400;
         reset       (&, 0x04011401);
         mask        (|, 0x04011405);
@@ -142,7 +173,7 @@
 
     register IOXFIR_1_MASK
     {
-        name        "XBUS1.BUSCTL.SCOM.FIR_MASK_REG";
+        name        "XBUS01.X1.BUSCTL.SCOM.FIR_MASK_REG";
         scomaddr    0x04011403;
         capture     type secondary;
         capture     group default;
@@ -150,7 +181,7 @@
 
     register IOXFIR_1_ACT0
     {
-        name        "XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG";
+        name        "XBUS01.X1.BUSCTL.SCOM.FIR_ACTION0_REG";
         scomaddr    0x04011406;
         capture     type secondary;
         capture     group default;
@@ -158,21 +189,120 @@
 
     register IOXFIR_1_ACT1
     {
-        name        "XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG";
+        name        "XBUS01.X1.BUSCTL.SCOM.FIR_ACTION1_REG";
         scomaddr    0x04011407;
         capture     type secondary;
         capture     group default;
     };
 
     ############################################################################
-    # XBUS Chiplet IOXFIR_2
+    # XBUS Chiplet IOXFIR_2 (Venice only)
     ############################################################################
 
-    # Venice only scomaddr = TBD
+    register IOXFIR_2
+    {
+        name        "XBUS23.X0.BUSCTL.SCOM.FIR_REG";
+        scomaddr    0x04011800;
+        reset       (&, 0x04011801);
+        mask        (|, 0x04011805);
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_2_MASK
+    {
+        name        "XBUS23.X0.BUSCTL.SCOM.FIR_MASK_REG";
+        scomaddr    0x04011803;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_2_ACT0
+    {
+        name        "XBUS23.X0.BUSCTL.SCOM.FIR_ACTION0_REG";
+        scomaddr    0x04011806;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_2_ACT1
+    {
+        name        "XBUS23.X0.BUSCTL.SCOM.FIR_ACTION1_REG";
+        scomaddr    0x04011807;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
 
     ############################################################################
-    # XBUS Chiplet IOXFIR_3
+    # XBUS Chiplet IOXFIR_3 (Venice only)
     ############################################################################
 
-    # Venice only scomaddr = TBD
+    register IOXFIR_3
+    {
+        name        "XBUS23.X1.BUSCTL.SCOM.FIR_REG";
+        scomaddr    0x04011c00;
+        reset       (&, 0x04011c01);
+        mask        (|, 0x04011c05);
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_3_MASK
+    {
+        name        "XBUS23.X1.XBUS1.BUSCTL.SCOM.FIR_MASK_REG";
+        scomaddr    0x04011c03;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_3_ACT0
+    {
+        name        "XBUS23.X1.XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG";
+        scomaddr    0x04011c06;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register IOXFIR_3_ACT1
+    {
+        name        "XBUS23.X1.XBUS1.BUSCTL.SCOM.FIR_ACTION1_REG";
+        scomaddr    0x04011c07;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    ############################################################################
+    # XBUS Chiplet XBUS_PSIFIR (Venice only)
+    ############################################################################
+
+    register XBUS_PSIFIR
+    {
+        name        "PSI.PSI_MAC.PSI_SCOM.FIR_REG";
+        scomaddr    0x04012400;
+        reset       (&, 0x04012401);
+        mask        (|, 0x04012405);
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register XBUS_PSIFIR_MASK
+    {
+        name        "PSI.PSI_MAC.PSI_SCOM.FIR_MASK_REG";
+        scomaddr    0x04012403;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register XBUS_PSIFIR_ACT0
+    {
+        name        "PSI.PSI_MAC.PSI_SCOM.FIR_ACTION0_REG";
+        scomaddr    0x04012406;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
+
+    register XBUS_PSIFIR_ACT1
+    {
+        name        "PSI.PSI_MAC.PSI_SCOM.FIR_ACTION1_REG";
+        scomaddr    0x04012407;
+        capture     type secondary;
+        capture     group never; #FIXME: RTC 67200
+    };
 
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
index a0675e816..39815f782 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
@@ -672,6 +672,42 @@ int32_t MaskIfCentaurCheckstop( ExtensibleChip * i_chip,
  * @param  i_sc   The step code data struct
  * @returns Failure or Success
  */
+int32_t MaskMCS00IfCentaurCheckstop( ExtensibleChip * i_chip,
+                                     STEP_CODE_DATA_STRUCT & i_sc )
+{
+    int32_t l_rc = SUCCESS;
+    l_rc = MaskIfCentaurCheckstop(i_chip, i_sc, 5);
+    return l_rc;
+}
+PRDF_PLUGIN_DEFINE( Proc, MaskMCS00IfCentaurCheckstop );
+
+int32_t MaskMCS01IfCentaurCheckstop( ExtensibleChip * i_chip,
+                                     STEP_CODE_DATA_STRUCT & i_sc )
+{
+    int32_t l_rc = SUCCESS;
+    l_rc = MaskIfCentaurCheckstop(i_chip, i_sc, 6);
+    return l_rc;
+}
+PRDF_PLUGIN_DEFINE( Proc, MaskMCS01IfCentaurCheckstop );
+
+int32_t MaskMCS10IfCentaurCheckstop( ExtensibleChip * i_chip,
+                                     STEP_CODE_DATA_STRUCT & i_sc )
+{
+    int32_t l_rc = SUCCESS;
+    l_rc = MaskIfCentaurCheckstop(i_chip, i_sc, 7);
+    return l_rc;
+}
+PRDF_PLUGIN_DEFINE( Proc, MaskMCS10IfCentaurCheckstop );
+
+int32_t MaskMCS11IfCentaurCheckstop( ExtensibleChip * i_chip,
+                                     STEP_CODE_DATA_STRUCT & i_sc )
+{
+    int32_t l_rc = SUCCESS;
+    l_rc = MaskIfCentaurCheckstop(i_chip, i_sc, 8);
+    return l_rc;
+}
+PRDF_PLUGIN_DEFINE( Proc, MaskMCS11IfCentaurCheckstop );
+
 int32_t MaskMCS20IfCentaurCheckstop( ExtensibleChip * i_chip,
                                      STEP_CODE_DATA_STRUCT & i_sc )
 {