Workaround invalid SBE use of IPI inject register

Change-Id: I40600399daf2ef563b534bd91143a4f45d00ff79
CQ: SW248610
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9273
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 52 insertions, 1 deletions

diff --git a/src/include/kernel/intmsghandler.H b/src/include/kernel/intmsghandler.H
index 02f681bd0..dad8c4325 100644
--- a/src/include/kernel/intmsghandler.H
+++ b/src/include/kernel/intmsghandler.H
@@ -149,6 +149,12 @@ class InterruptMsgHdlr : public MessageHandler
          */
         static void sendIPI(uint64_t i_pir, uint8_t i_favor = 0x1);
 
+        /**
+         * Issue the sbe/mailbox workaround (issue a mbox EOI to mailbox)
+         *
+         */
+        static void issueSbeMboxWA();
+
     private:
 
         static InterruptMsgHdlr * cv_instance;
diff --git a/src/include/sys/msg.h b/src/include/sys/msg.h
index b9ff8f513..162ef8c50 100644
--- a/src/include/sys/msg.h
+++ b/src/include/sys/msg.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2010,2013              */
+/* COPYRIGHT International Business Machines Corp. 2010,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -61,6 +61,8 @@ enum msg_sys_types_t
 
     MSG_INTR_EXTERN,    //!< Msg sent from kernel to user space on ext intr
     MSG_INTR_ADD_CPU,   //!< Add cpu core, data[0] = cpuid (PIR)
+    MSG_INTR_ISSUE_SBE_MBOX_WA,   //!< Issue EOI to mailbox
+
 };
 
 // System-defined root queue types
diff --git a/src/kernel/intmsghandler.C b/src/kernel/intmsghandler.C
index 1ce9de1b8..8a865eaf3 100644
--- a/src/kernel/intmsghandler.C
+++ b/src/kernel/intmsghandler.C
@@ -208,3 +208,15 @@ MessageHandler::HandleResult InterruptMsgHdlr::handleResponse
     return UNHANDLED_RC;
 }
 
+
+void InterruptMsgHdlr::issueSbeMboxWA()
+{
+    if(cv_instance)
+    {
+        cv_instance->iv_lock.lock();
+        cv_instance->sendMessage(MSG_INTR_ISSUE_SBE_MBOX_WA,
+                     reinterpret_cast<void*>(MSG_INTR_ISSUE_SBE_MBOX_WA),
+                     NULL,NULL);
+        cv_instance->iv_lock.unlock();
+    }
+}
diff --git a/src/kernel/misc.C b/src/kernel/misc.C
index 48c1240de..cba6a152c 100644
--- a/src/kernel/misc.C
+++ b/src/kernel/misc.C
@@ -298,6 +298,8 @@ namespace KernelMisc
         iv_caller->state = TASK_STATE_RUNNING;
         TaskManager::setCurrentTask(iv_caller);
 
+        //Issue sbe master workaround
+        InterruptMsgHdlr::issueSbeMboxWA();
     }
 
     void WinkleCore::nonactiveMainWork()
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index ed86cdfe6..5fb278363 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -656,6 +656,35 @@ void IntrRp::msgHandler()
                 }
                 break;
 
+            case MSG_INTR_ISSUE_SBE_MBOX_WA:
+                {
+                    //The SBE IPI injection on master winkle wakeup
+                    //can clobber a pending mailbox interrupt in the ICP
+                    //To workaround need to issue EOI on mailbox.  If
+                    //mbx intr is not hot this does nothing, if it is
+                    //then the EOI will cause intr to be represented
+
+                    //This is safe on FSPless since the PSI intr are
+                    //always setup on master chip
+                    uint64_t baseAddr = iv_baseAddr +
+                                        cpuOffsetAddr(iv_masterCpu);
+                    uint32_t * xirrAddress =
+                      reinterpret_cast<uint32_t*>(baseAddr + XIRR_OFFSET);
+
+                    //Generate the mailbox IRSN for this node
+                    uint32_t l_irsn = makeXISR(iv_masterCpu, ISN_FSI);
+                    l_irsn |= CPPR_MASK;  //set all CPPR bits - allow any INTR
+
+                    TRACFCOMP(g_trac_intr,
+                              "MBX SBE WA Issue EOI to %x",l_irsn);
+                    *xirrAddress = l_irsn;  //Issue EOI
+
+                    // Acknowlege msg
+                    msg->data[1] = 0;
+                    msg_respond(iv_msgQ, msg);
+                }
+                break;
+
             case MSG_INTR_SHUTDOWN:
                 {
                     TRACFCOMP(g_trac_intr,"Shutdown event received");