Attribute changes to support LRDIMMs through EFF attrs.

Change-Id: Iff8e23ebc02adb3cd91c181692801cffe12d8742
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11916
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

13 files changed, 3455 insertions, 267 deletions

diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index 4f16eb22d..92a32e119 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -1128,7 +1128,7 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
     fapi::platAttrSvc::fapiPlatGetProcPcieBarBaseAddr (PTARGET, VAL )
 #define ATTR_PROC_PCIE_BAR_SIZE_GETMACRO( ID, PTARGET, VAL )   \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetProcPcieBarSize (PTARGET, VAL ) 
+    fapi::platAttrSvc::fapiPlatGetProcPcieBarSize (PTARGET, VAL )
 
 //------------------------------------------------------------------------------
 //  MACROS to support enable attributes in p8_xip_customize_attributes.xml
@@ -1613,6 +1613,152 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
         fapi::FAPI_RC_SUCCESS :\
         fapi::platAttrSvc::getTargetingAttr\
            (PTARGET, TARGETING::ATTR_EFF_TSYS_DP18, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_PAR_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_PAR, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M_ACTN_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_ACTN, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, sizeof(VAL), &VAL)
+#define ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, sizeof(VAL), &VAL)
+
 #endif // CONFIG_VPD_GETMACRO_USE_EFF_ATTR
 
 //------------------------------------------------------------------------------
@@ -1629,6 +1775,11 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
         fapi::FAPI_RC_SUCCESS :\
         fapi::platAttrSvc::getTargetingAttr\
            (PTARGET, TARGETING::ATTR_EFF_DRAM_ADDRESS_MIRRORING, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_ADDRESS_MIRRORING_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::getTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_ADDRESS_MIRRORING, sizeof(VAL), &VAL)
+
 #endif // CONFIG_VPD_GETMACRO_USE_EFF_ATTR
 
 //------------------------------------------------------------------------------
@@ -1923,58 +2074,167 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
         fapi::FAPI_RC_SUCCESS :\
         fapi::platAttrSvc::getTargetingAttr\
            (PTARGET, TARGETING::ATTR_EFF_CKE_PWR_MAP, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_ODT_WR_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_ODT_WR, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_RON_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_RON, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_RTT_NOM_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_RTT_NOM, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_RTT_WR_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_RTT_WR, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CKE_PRI_MAP_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CKE_PRI_MAP, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_CNTL_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_CNTL, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_CNTL_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_CNTL, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_ADDR_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_ADDR, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CKE_PWR_MAP_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CKE_PWR_MAP, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_CLK_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_CLK, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_SPCKE_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_SPCKE, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_RD_VREF_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_RD_VREF, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_SLEW_RATE_CNTL_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_SLEW_RATE_CNTL, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_SLEW_RATE_ADDR_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_SLEW_RATE_ADDR, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_SLEW_RATE_CLK_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_SLEW_RATE_CLK, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_SLEW_RATE_SPCKE_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_SLEW_RATE_SPCKE, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_WR_VREF_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_WR_VREF, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_WRDDR4_VREF_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_WRDDR4_VREF, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_RCV_IMP_DQ_DQS_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_RCV_IMP_DQ_DQS, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_ODT_RD_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_ODT_RD, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_DRV_IMP_DQ_DQS_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_DRV_IMP_DQ_DQS, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_RLO_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_RLO, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_WLO_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_WLO, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_GPO_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_GPO, sizeof(VAL), &VAL)
+
 #endif // CONFIG_VPD_GETMACRO_USE_EFF_ATTR
 
 //------------------------------------------------------------------------------
 //  MACROS to support MBVPD Slope Intercept attributes
 //------------------------------------------------------------------------------
-#define ATTR_CDIMM_VPD_MASTER_POWER_SLOPE_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS :\
-    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData\
+#define ATTR_CDIMM_VPD_MASTER_POWER_SLOPE_GETMACRO(ID, PTARGET, VAL)  \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS :                                           \
+    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData                  \
         (PTARGET, fapi::MASTER_POWER_SLOPE , VAL)
-#define ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS :\
-    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData\
+#define ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS :                                           \
+    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData                  \
         (PTARGET, fapi::MASTER_POWER_INTERCEPT , VAL)
-#define ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS :\
-    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData\
+#define ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS :                                           \
+    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData                  \
         (PTARGET, fapi::SUPPLIER_POWER_SLOPE , VAL)
-#define ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS :\
-    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData\
+#define ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS :                                           \
+    fapi::platAttrSvc::fapiPlatGetSlopeInterceptData                  \
         (PTARGET, fapi::SUPPLIER_POWER_INTERCEPT , VAL)
 
 //------------------------------------------------------------------------------
 //  MACRO to support BAD_DQ_BITMAP Attribute
 //------------------------------------------------------------------------------
-#define ATTR_BAD_DQ_BITMAP_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS : fapi::platAttrSvc::fapiPlatDimmGetBadDqBitmap\
+#define ATTR_BAD_DQ_BITMAP_GETMACRO(ID, PTARGET, VAL)                 \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS : fapi::platAttrSvc::fapiPlatDimmGetBadDqBitmap \
         (PTARGET, VAL)
-#define ATTR_BAD_DQ_BITMAP_SETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::setAttrActionsFunc(fapi::ID, PTARGET,\
-                                               sizeof(VAL), &VAL),\
+#define ATTR_BAD_DQ_BITMAP_SETMACRO(ID, PTARGET, VAL)                 \
+    fapi::AttrOverrideSync::setAttrActionsFunc(fapi::ID, PTARGET,     \
+                                               sizeof(VAL), &VAL),    \
     fapi::platAttrSvc::fapiPlatDimmSetBadDqBitmap(PTARGET, VAL)
 
 //------------------------------------------------------------------------------
 //  MACRO to support VPD_DIMM_SPARE Attribute
 //------------------------------------------------------------------------------
 #ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
-#define ATTR_VPD_DIMM_SPARE_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
-    fapi::FAPI_RC_SUCCESS : fapi::platAttrSvc::fapiPlatDimmGetSpareDram\
+#define ATTR_VPD_DIMM_SPARE_GETMACRO(ID, PTARGET, VAL)                \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
+    fapi::FAPI_RC_SUCCESS : fapi::platAttrSvc::fapiPlatDimmGetSpareDram \
         (PTARGET, VAL)
 #else
-#define ATTR_VPD_DIMM_SPARE_GETMACRO(ID, PTARGET, VAL)\
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ?\
+#define ATTR_VPD_DIMM_SPARE_GETMACRO(ID, PTARGET, VAL)                \
+    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? \
         fapi::FAPI_RC_SUCCESS :\
         fapi::platAttrSvc::getTargetingAttr\
            (PTARGET, TARGETING::ATTR_EFF_DIMM_SPARE, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DIMM_SPARE_SETMACRO(ID, PTARGET, VAL)                \
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DIMM_SPARE, sizeof(VAL), &VAL)
 #endif // CONFIG_VPD_GETMACRO_USE_EFF_ATTR
 
 //------------------------------------------------------------------------------
@@ -2157,6 +2417,12 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
     fapi::FAPI_RC_SUCCESS : fapi::platAttrSvc::fapiPlatGetVpdVersion\
         (PTARGET, VAL)
 
+#ifdef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
+#define ATTR_VPD_VERSION_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_MSS_EFF_VPD_VERSION, sizeof(VAL), &VAL)
+#endif
+
 //------------------------------------------------------------------------------
 //  MACROS to support MBVPD Get Dram 2N Mode Enabled
 //------------------------------------------------------------------------------
@@ -2171,6 +2437,11 @@ fapi::ReturnCode fapiPlatGetOscswitchCtl
         fapi::FAPI_RC_SUCCESS :\
         fapi::platAttrSvc::getTargetingAttr\
            (PTARGET, TARGETING::ATTR_EFF_DRAM_2N_MODE_ENABLED, sizeof(VAL), &VAL)
+
+#define ATTR_VPD_DRAM_2N_MODE_ENABLED_SETMACRO(ID, PTARGET, VAL)\
+        fapi::platAttrSvc::setTargetingAttr\
+           (PTARGET, TARGETING::ATTR_EFF_DRAM_2N_MODE_ENABLED, sizeof(VAL), &VAL)
+
 #endif // CONFIG_VPD_GETMACRO_USE_EFF_ATTR
 
 //------------------------------------------------------------------------------
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile
index dee812c3b..816cb353f 100644
--- a/src/usr/hwpf/hwp/dram_training/makefile
+++ b/src/usr/hwpf/hwp/dram_training/makefile
@@ -27,6 +27,8 @@ ROOTPATH = ../../../../..
 
 MODULE = dram_training
 
+CFLAGS += $(if $(CONFIG_PALMETTO_VDDR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM)
+
 ##      support for Targeting and fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 1ef88fd84..01363c2a5 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -171,6 +173,8 @@
 #include <mss_lrdimm_ddr4_funcs.H>
 #endif
 
+#include <config.h>
+
 #ifndef FAPI_LRDIMM
 using namespace fapi;
 fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(Target& i_target)
@@ -474,6 +478,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	    rc = mss_execute_zq_cal(i_target, port);
 	    if(rc) return rc;
 
+#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
             // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
 	    if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) &&
                  (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
@@ -483,9 +488,10 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 		 rc = mss_mxd_training(i_target,port,0);
 		 if(rc) return rc;
             }
+#endif
 	}
 
-        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && 
+        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) &&
 				(dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
         {
             FAPI_INF("Performing LRDIMM MB-DRAM training");
@@ -713,6 +719,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 			       if(rc) return rc;
                             }
 			}
+#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
                         // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
                         else if ( (group == 0) && (cur_cal_step == 1)
                                   && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
@@ -721,6 +728,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
                            rc = mss_dram_write_leveling(i_target, port);
                            if(rc) return rc;
                         }
+#endif
 
 		        //Set the config register
 			if(port == 0)
@@ -847,7 +855,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	return rc;
     }
 
-    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. 
+    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code.
     if (complete_status == MSS_INIT_CAL_STALL)
     {
 	FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++");
@@ -3417,7 +3425,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 					 rc.setEcmdError(l_ecmdRc);
 					 return rc;
 				}
-				
+
 				for (uint8_t n=0; n < 4; n++)	// check each nibble
 				{
 					uint16_t nmask = 0xF000 >> (4*n);
@@ -3456,7 +3464,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 				}
 
 				FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data);
-				
+
 				// set disable0(dq) reg
 				l_ecmdRc = data_buffer.setHalfWord(3, l_data);
 				if (l_ecmdRc != ECMD_DBUF_SUCCESS)
@@ -3481,7 +3489,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 					FAPI_ERR("Error from fapiPutScom writing disable0 reg");
 					return rc;
 				}
-					
+
 				// set address for disable1(dqs) register
 				l_addr += l_disable1_addr_offset;
 				if (disable1_data != 0)
@@ -4063,7 +4071,7 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port,
                         			const uint8_t & DIMM = i_dimm;
                         			const uint8_t & RANK = i_rank;
 
-						FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", 
+						FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u",
 							dimm_spare[i_port][i_dimm][i_rank]);
 						FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR);
 						return rc;
@@ -4158,7 +4166,7 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port,
 	uint8_t phy_lane;
 	uint8_t phy_block;
  	uint8_t data;
-	
+
     // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
     rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
     if (rc)
diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H
new file mode 100644
index 000000000..0da90f1c3
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H
@@ -0,0 +1,218 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_lrdimm_ddr4_funcs.H,v 1.1 2014/03/14 16:05:51 kcook Exp $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : mss_lrdimm_funcs.H
+// *! DESCRIPTION : Tools for lrdimm centaur procedures
+// *! OWNER NAME : KCOOK
+// *! BACKUP NAME : MWUU
+// #! ADDITIONAL COMMENTS :
+//
+// CCS related and general utility functions.
+// Provides functions for mss_eff_conifg, mss_draminit, and mss_draminit_training
+// for DDR4 LRDIMM.
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.1    | 03/14/14 | kcook   | First drop of Centaur
+
+#ifndef _MSS_LRDIMM_DDR4_FUNCS_H
+#define _MSS_LRDIMM_DDR4_FUNCS_H
+
+//#define LRDIMM 1
+
+//----------------------------------------------------------------------
+//  Constants 
+//----------------------------------------------------------------------
+const uint64_t MAINT0_MBA_MAINT_BUFF0_DATA_ECC0_0x0301065d = 0x0301065d;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_0x800000010301183F = 0x800000010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_0x800004010301183F = 0x800004010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_0x800008010301183F = 0x800008010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_0x80000C010301183F = 0x80000C010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_0x800010010301183F = 0x800010010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_0x800100010301183F = 0x800100010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_0x800104010301183F = 0x800104010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_0x800108010301183F = 0x800108010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_0x80010C010301183F = 0x80010C010301183Full;
+const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_0x800110010301183F = 0x800110010301183Full;
+//----------------------------------------------------------------------
+//  Enums 
+//----------------------------------------------------------------------
+//----------------------------------------------------------------------
+// LRDIMM FUNCS
+//----------------------------------------------------------------------
+//--------------------------------------------------------------
+// mss_create_db_ddr4  
+// Determines DB control words and stores in attribute
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_create_db_ddr4( const fapi::Target& i_target_mba);
+
+//--------------------------------------------------------------
+// mss_lrdimm_ddr4_term_atts  
+// eff config termination rewrite odts 
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_lrdimm_ddr4_term_atts( const fapi::Target& i_target_mba);
+
+//--------------------------------------------------------------
+// mss_lrdimm_ddr4_db_load  
+// Writes initial  DB control words to DB from attributes
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_lrdimm_ddr4_db_load( fapi::Target& i_target, 
+                                          uint32_t i_port_number, 
+                                          uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_bcw_write 
+// Writes single BCW to DB
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_bcw_write( fapi::Target& i_target_mba, uint32_t i_port_number,
+                         uint8_t bcw_width, uint8_t bcw, uint8_t bcw_value,
+                         uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_dram_write_leveling
+// Executes DB-DRAM write leveing
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_dram_write_leveling( fapi::Target& i_target_mba, uint32_t i_port_number);
+
+//--------------------------------------------------------------
+// mss_store_db_delay
+// Used at end of training steps to write found delay values to DB control word registers
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_store_db_delay(fapi::Target& i_target_mba, uint8_t i_mbaPosition, uint32_t i_port_number,
+                                    uint32_t i_dimm_number, uint32_t i_rank_number,
+                                    uint8_t i_cw_reg, uint8_t i_nibble_delay[],
+                                    uint32_t& io_ccs_inst_cnt, uint8_t i_split_fine=0);
+//--------------------------------------------------------------
+// mss_step_delay_cw0
+// Used in mxd training to step DB CW  delay register and query data bus
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_step_delay_cw0(fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_dimm_number, uint8_t i_rank_number,
+		uint8_t i_num_wr_rd, uint8_t o_nibble_delay[], uint8_t i_type, uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_step_delay_cw
+// Used in dram_write_leveling and mrep_training to step DB CW delay registers and query data bus
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_step_delay_cw(fapi::Target& i_target_mba, uint32_t i_port_number, uint32_t i_dimm_number, uint32_t i_rank_number,
+                                   uint8_t i_cw_reg, uint8_t i_num_reads, uint8_t o_nibble_delay[],
+                                   uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_mr1_wr_lvl  
+// Send MR1 command to set DRAM to write leveling mode or normal mode
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_mr1_wr_lvl(fapi::Target& i_target_mba, uint32_t i_port_number,
+                                uint8_t wr_lvl, uint32_t& io_ccs_inst_cnt);
+
+
+
+//--------------------------------------------------------------
+// mss_mrep_training
+// Conducts MDQ Receive Enable Phase Training between DB and DRAM
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_mrep_training( fapi::Target& i_target_mba, uint32_t i_port_number);
+//--------------------------------------------------------------
+// mss_mxd_training
+// Conducts MRD or MWD coarse, normal, or find training. Still in development
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_mxd_training( fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_type);
+//--------------------------------------------------------------
+// mss_add_rdmpr 
+// Adds read command without activate to ccs
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_add_rdmpr( fapi::Target& i_target_mba, 
+                               uint32_t i_port_number, uint32_t dimm_number, uint32_t rank_number,
+                               uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_mpr_operation
+// Sets MR3 command to MPR data flow or normal data flow
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_mpr_operation( fapi::Target& i_target_mba, uint32_t i_port_number,
+                             uint8_t mpr_op,
+                         uint32_t& io_ccs_inst_cnt);
+
+//--------------------------------------------------------------
+// mss_force_fifo_capture
+// Sets force_fifo_capture bit in rd_dia_config5 registers to Force DQ capture or normal operation
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_force_fifo_capture(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, 
+                                        uint32_t i_port_number,
+                            uint32_t force_fifo);
+
+//--------------------------------------------------------------
+// mss_data_bit_set
+// Sets single DQ byte or all DQ bytes to 0 or 1 through DATA_BIT_DIR registers. 
+// Used with DFT_FORCE_OUTPUT during PBA mode
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_data_bit_set(fapi::Target& i_target_mba, uint8_t i_mbaPosition, 
+                                        uint32_t i_port_number,
+                            uint8_t byte, uint8_t dq_value);
+
+//--------------------------------------------------------------
+// mss_dft_force_outputs
+// Sets DFT_FORCE_OUTPUTS bit to 0 or 1 to control DQ bus during PBA mode
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_dft_force_outputs(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, 
+                                        uint32_t i_port_number,
+                            uint32_t force_outputs);
+
+//--------------------------------------------------------------
+
+
+
+
+
+
+
+
+#endif /* _MSS_LRDIMM_DDR4_FUNCS_H */
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C
index bdbea0ba5..63166139c 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C
@@ -45,7 +45,7 @@
 //  1.8    | kcook    |13-FEB-14| More FW updates.
 //  1.7    | kcook    |12-FEB-14| Updated HWP_ERROR per RAS review to be used with memory_mss_lrdimm_funcs.xml
 //  1.6    | bellows  |02-JAN-14| VPD attribute removal
-//  1.5    | kcook    |12/03/13 | Updated VPD attributes. 
+//  1.5    | kcook    |12/03/13 | Updated VPD attributes.
 //  1.4    | bellows  |09/16/13 | Hostboot compile update
 //  1.3    | bellows  |09/16/13 | Added ID tag.
 //  1.2    | kcook    |09/13/13 | Updated define FAPI_LRDIMM token.
@@ -266,7 +266,7 @@ fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, uint32_t port_numb
           data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);
 
           func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-        
+
           //check for rc but not seeing where rc is set in this loop/if statment
           if(rc) return rc;
        }
@@ -477,7 +477,7 @@ fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, uint32_t port_numb
              data_buff_rcd_word.insert(ext_funcs[dimm_number][i][1], 60,4);        // msb data
 
              func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-            
+
             //not sure where the rc call is made
              if(rc) return rc;
            } // end if  has ranks
@@ -574,11 +574,11 @@ fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target , uint32_t i_port_n
 
         ecmdDataBufferBase mrs1(16);
         uint16_t MRS1 = 0;
-        uint32_t mrs_number;
+//        uint32_t mrs_number;
         uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
         uint8_t is_sim = 0;
         uint8_t dram_2n_mode = 0;
- 
+
         uint32_t rank_number;
         uint16_t num_ranks = 2;
         uint8_t func13_rcd_number_array_size;
@@ -689,7 +689,7 @@ fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target , uint32_t i_port_n
               data_buff_rcd_word.clearBit(0,64);
               data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_14, 56,4);
               func_rcd_control_word[dimm_num] = data_buff_rcd_word.getDoubleWord(0);
-            
+
               //not sure need this rc check
               if(rc) return rc;
            }
@@ -877,7 +877,7 @@ fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target , uint32_t i_port_n
            // Only corresponding CS to rank
            rc_num = rc_num | csn_8.setBit(0,8);
            rc_num = rc_num | csn_8.insert(lrdimm_cs8n[rank_number],(4*dimm_number),4,4);
-           mrs_number = 2;
+//           mrs_number = 2;
 
            // Copying the current MRS into address buffer matching the MRS_array order
            // Setting the bank address
@@ -1246,7 +1246,7 @@ fapi::ReturnCode  mss_execute_lrdimm_mb_dram_training(fapi::Target &i_target)
    return rc;
 }
 
-fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba, 
+fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
                                  uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE],
                                  uint32_t mss_freq, uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE])
 {
@@ -1265,7 +1265,7 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
    uint8_t eff_ibm_type[PORT_SIZE][DIMM_SIZE];
    uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
 
-   do 
+   do
    {
       rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array);
       if(rc)
@@ -1273,7 +1273,7 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
           FAPI_ERR("Error retrieving assodiated dimms");
           break;
       }
-   
+
       for (uint8_t l_dimm_index = 0; l_dimm_index < l_target_dimm_array.size(); l_dimm_index += 1)
       {
          rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index],
@@ -1290,7 +1290,7 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
              FAPI_ERR("Error retrieving ATTR_MBA_DIMM");
              break;
          }
-   
+
          // Setup SPD attributes
          rc = FAPI_ATTR_GET(ATTR_SPD_LR_ADDR_MIRRORING, &l_target_dimm_array[l_dimm_index],
              p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm]);
@@ -1365,14 +1365,14 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
              p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
          if(rc) break;
       }
-   
+
       if(rc)
       {
           FAPI_ERR("Error reading spd data from caller");
           break;
       }
-   
-   
+
+
       // Setup attributes
       for (int l_cur_mba_port = 0; l_cur_mba_port < PORT_SIZE; l_cur_mba_port += 1)
       {
@@ -1381,38 +1381,38 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
             if (cur_dimm_spd_valid_u8array[l_cur_mba_port][l_cur_mba_dimm] == MSS_EFF_VALID)
             {
                FAPI_INF("  !! LRDIMM Detected  -MW");
-   
-               ecmdDataBuffer rcd(64);
+
+               ecmdDataBufferBase rcd(64);
                rcd.flushTo0();
-   
+
                rcd.setDoubleWord(0,eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]);
                FAPI_INF("rcd0_15=0x%016llX",rcd.getDoubleWord(0));
-   
+
                rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],12,4,0);  //rcd3
                rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],8,4,4);   //rcd2
-   
+
                rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],20,4,0);  //rcd5
                rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],16,4,4);  //rcd4
-   
+
                rcd.insert(p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm],59,1,7); // address mirroring
-   
+
                eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]=rcd.getDoubleWord(0);
-   
-               ecmdDataBuffer rcd_1(64);
+
+               ecmdDataBufferBase rcd_1(64);
                rcd_1.flushTo0();
                     // F[1]RC11,8
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],44,4,0);  //F[1]RC11 -> rcd11
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],32,4,4);  //F[1]RC8  -> rcd8
-   
+
                     // F[1]RC13,12
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],52,4,0);  //F[1]RC13 -> rcd13
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],48,4,4);  //F[1]RC12 -> rcd12
-   
+
                     // F[1]RC15,14
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],60,4,0);  //F[1]RC15 -> rcd15
                rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],56,4,4);  //F[1]RC14 -> rcd14
-   
-   
+
+
                if ( mss_freq > 1733 ) {
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
@@ -1424,9 +1424,9 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
                     rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
+
                     lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm];
-   
+
                } else if ( mss_freq > 1200 )  {
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
@@ -1438,9 +1438,9 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
                     rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
+
                     lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm];
-   
+
                } else {
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
                     rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
@@ -1452,20 +1452,20 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
                     rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
                     rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
+
                     lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_800_1066[l_cur_mba_port][l_cur_mba_dimm];
                }
-   
+
                uint64_t rcd1 = rcd_1.getDoubleWord(0);
                lrdimm_additional_cntl_words[l_cur_mba_port][l_cur_mba_dimm] = rcd1;
-   
+
                if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8 ) {
                   lrdimm_rank_mult_mode = 4; // Default for 8R is 4x mult mode
                }
-   
+
                    // ========================================================================================
-   
-   
+
+
                                 // FIX finding stack type properly.
                if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1 ) {
                   //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
@@ -1492,7 +1492,7 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
             } // end valid dimm
          } // end dimm loop
       } // end port loop
-   
+
       rc = FAPI_ATTR_SET(ATTR_EFF_IBM_TYPE, &i_target_mba,
               eff_ibm_type);
       rc = FAPI_ATTR_SET(ATTR_LRDIMM_MR12_REG, &i_target_mba,
@@ -1503,7 +1503,7 @@ fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba,
               lrdimm_rank_mult_mode);
       rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba,
               eff_dimm_rcd_cntl_word_0_15);
-   
+
       if(rc)
       {
          FAPI_ERR("Error setting attributes");
@@ -1521,8 +1521,8 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt(const fapi::Target& i_target_mba, uint32
 //   uint8_t l_arr_offset;
    uint32_t l_mss_freq = 0;
    uint8_t l_dram_width_u8;
-   
-   uint32_t *odt_array;
+
+//   uint32_t *odt_array;
 
    // For dual drop, Set ODT_RD as 2rank (8R LRDIMM) or 4rank (4R LRDIMM)
    fapi::Target l_target_centaur;
@@ -1534,20 +1534,20 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt(const fapi::Target& i_target_mba, uint32
 
 //   uint8_t l_start=44, l_end=60;
    if ( (l_num_ranks_per_dimm_u8array[0][1] == 4) || (l_num_ranks_per_dimm_u8array[1][1] == 4) ) {
-      odt_array = var_array_p_array[0];
+//      odt_array = var_array_p_array[0];
       FAPI_INF("Setting LRDIMM ODT_RD as 4 rank dimm");
    } else if ( (l_num_ranks_per_dimm_u8array[0][1] == 8) || (l_num_ranks_per_dimm_u8array[1][1] == 8) ) {
       if ( l_mss_freq <= 1466 ) { // 1333Mbps
          if ( l_dram_width_u8 == 4 ) {
-            odt_array = var_array_p_array[1];
+//            odt_array = var_array_p_array[1];
          } else if ( l_dram_width_u8 == 8 ) {
-            odt_array = var_array_p_array[2];
+//            odt_array = var_array_p_array[2];
          }
       } else if ( l_mss_freq <= 1733 ) { // 1600 Mbps
          if ( l_dram_width_u8 == 4 ) {
-            odt_array = var_array_p_array[3];
+//            odt_array = var_array_p_array[3];
          } else if ( l_dram_width_u8 == 8 ) {
-            odt_array = var_array_p_array[4];
+//            odt_array = var_array_p_array[4];
          }
       }
       FAPI_INF("Setting LRDIMM ODT_RD as 2 logical rank dimm");
@@ -1580,7 +1580,7 @@ fapi::ReturnCode mss_lrdimm_term_atts(const fapi::Target& i_target_mba)
    uint8_t l_num_drops_per_port;
    uint8_t l_dram_density;
    uint8_t l_dram_width_u8;
-   
+
    uint8_t l_lrdimm_mr12_u8array[PORT_SIZE][DIMM_SIZE];
    uint8_t l_lrdimm_rank_mult_mode;
 
@@ -1710,7 +1710,7 @@ fapi::ReturnCode mss_lrdimm_term_atts(const fapi::Target& i_target_mba)
             if ( l_dram_density == 1 ) {
                l_rcd_cntl_word_15 = 5;    // A[15:14]; 4x multiplication, 1 Gbit DDR3 SDRAM
             } else if ( l_dram_density == 2 ) {
-               l_rcd_cntl_word_15 = 6;    // A[16:15]; 4x multiplication, 2 Gbit DDR3 SDRAM               
+               l_rcd_cntl_word_15 = 6;    // A[16:15]; 4x multiplication, 2 Gbit DDR3 SDRAM
             } else if ( l_dram_density == 4 ) {
                l_rcd_cntl_word_15 = 7;    // A[17:16]; 4x multiplication, 4 Gbit DDR3 SDRAM
             } else {
diff --git a/src/usr/hwpf/hwp/lab_dimm_attributes.xml b/src/usr/hwpf/hwp/lab_dimm_attributes.xml
new file mode 100644
index 000000000..cf6f3842d
--- /dev/null
+++ b/src/usr/hwpf/hwp/lab_dimm_attributes.xml
@@ -0,0 +1,104 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/lab_dimm_attributes.xml $                    -->
+<!--                                                                        -->
+<!-- OpenPOWER HostBoot Project                                             -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2014                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- XML file specifying DIMM attributes used by HW Procedures. -->
+<!-- $Id: dimm_attributes.xml,v 1.4 2013/10/03 20:40:52 dedahle Exp $ -->
+<attributes>
+
+<attribute>
+    <id>ATTR_CEN_DQ_TO_DIMM_CONN_DQ</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Centaur DQ to DIMM connector DQ mapping.
+        Uint8 value for each Centaur DQ (0-79).
+        The value is the corresponding DIMM Connector DQ.
+        Therefore if (data[2] == 60) then Centaur DQ 2 maps to DIMM DQ 60
+        If the logical DIMM is on a Centaur-DIMM then the value is the same as the
+        array index because there is no DIMM connector.
+        If the logical DIMM is an IS-DIMM then the value depends on board wiring.
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MBA_PORT</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>MBA Chiplet port this DIMM is connected to</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MBA_DIMM</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>MBA port DIMM number of this DIMM</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_BAD_DQ_BITMAP</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Bad DQ bitmap from a Centaur:MBA point of view.
+        The data is a 10 byte bitmap for each of 4 possible ranks.
+        The bad DQ data is stored in DIMM SPD, it is stored in a special format
+        and is translated to a DIMM Connector point of view for IS-DIMMs.
+        All of these details are hidden from the user of this attribute.
+    </description>
+    <valueType>uint8</valueType>
+    <array>4 10</array>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DIMM_SPARE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+        Spare DRAM availability for all DIMMs connected to the target MBA.
+        For each rank on a DIMM, there are 8 DQ lines to spare DRAMs.
+        - NO_SPARE: No spare DRAMs
+        - LOW_NIBBLE:  x4 DRAMs in use, one spare DRAM connected to SP_DQ0-3
+        - HIGH_NIBBLE: x4 DRAMs in use, one spare DRAM connected to SP_DQ4-7
+        - FULL_BYTE: Either
+          1/ x4 DRAMs in use, two spare DRAMs connected to SP_DQ0-7
+          2/ x8 DRAMs in use, one spare DRAM connected to SP_DQ0-7
+        For C-DIMMs, this is in a VPD field : Record:VSPD, Keyword:AM
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        NO_SPARE = 0x00,
+        LOW_NIBBLE = 0x01,
+        HIGH_NIBBLE = 0x02,
+        FULL_BYTE = 0x03
+    </enum>
+    <array>2 2 4</array>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+</attributes>
diff --git a/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml b/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml
new file mode 100644
index 000000000..149b6dcc5
--- /dev/null
+++ b/src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml
@@ -0,0 +1,2572 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/lab_dimm_spd_attributes.xml $                -->
+<!--                                                                        -->
+<!-- OpenPOWER HostBoot Project                                             -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2014                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: dimm_spd_attributes.xml,v 1.35 2014/05/23 16:33:05 whs Exp $ -->
+<!-- XML file specifying DIMM SPD attributes used by HW Procedures. -->
+<attributes>
+
+<!--
+*******************************************************************************
+The following attributes can be queried from both DDR3 and DDR4 DIMMs
+*******************************************************************************
+-->
+
+<attribute>
+    <id>ATTR_SPD_DRAM_DEVICE_TYPE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        DRAM Device Type.
+        Located in DDR3/DDR4 SPD byte 2.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DDR3 = 0x0b, DDR4 = 0x0c</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_TYPE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Type.
+        Located in DDR3/DDR4 SPD byte 3, bits 3-0.
+        Note that CDIMM designation here is obsolete.  See ATTR_SPD_CUSTOM
+    </description>
+    <valueType>uint8</valueType>
+    <enum>CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, SO_DIMM=0x03, LRDIMM = 0x0b</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CUSTOM</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Type is CUSTOM
+        Located in DDR3/DDR4 SPD byte 3, bit 7. (Most significant bit)
+        If bit 7 (reserved) is a '1' then this attribute value should be set to YES
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NO = 0x0, YES = 0x1</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DENSITY</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        DRAM Density.
+        Located in DDR3/DDR4 SPD byte 4, bits 3-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        D256MB = 0x00, D512Mb = 0x01, D1GB = 0x02, D2GB = 0x03, D4GB = 0x04,
+        D8GB = 0x05, D16GB = 0x06, D32GB=0x07
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR3 SPD byte 4, bits 6-4.
+        Located in DDR4 SPD byte 4, bits 5-4.
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03, B4 = 0x04, UNKNOWN = 0xff</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_ROWS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of Rows.
+        Located in DDR3/DDR4 SPD byte 5, bits 5-3.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03,
+          R16 = 0x04, R17 = 0x05, R18 = 0x06
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_COLUMNS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of Columns.
+        Located in DDR3/DDR4 SPD byte 5, bits 2-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>C9 = 0x00, C10 = 0x01, C11 = 0x02, C12 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR3 SPD byte 6, bits 2-0.
+        Located in DDR4 SPD byte 11, bits 5-0.
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+         NOTOP1_5 = 0x01,
+         OP1_35 = 0x02,
+         OP1_2X = 0x04,
+         OP1_2V = 0x08,
+         END1_2V = 0x10
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_NUM_RANKS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of ranks.
+        Located in DDR3 SPD byte 7, bits 5-3.
+        Located in DDR4 SPD byte 12, bits 5-3.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>R1 = 0x00, R2 = 0x01, R3 = 0x02, R4 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_DRAM_WIDTH</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        DRAM Width.
+        Located in DDR3 SPD byte 7, bits 2-0.
+        Located in DDR4 SPD byte 12, bits 2-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>W4 = 0x00, W8 = 0x01, W16 = 0x02, W32 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_MEMORY_BUS_WIDTH</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Memory Bus Width.
+        Located in DDR3 SPD byte 8, bits 4-0
+        Located in DDR4 SPD byte 13, bits 4-0.
+           Bits 4-3 contain the Bus Width Extension (ECC)
+           Bits 2-0 contain the Primary Bus Width
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        W8 = 0x00, W16 = 0x01, W32 = 0x02, W64 = 0x03,
+        WE8 = 0x08, WE16 = 0x09, WE32 = 0x0a, WE64 = 0x0b
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TCKMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum cycle time (tCKmin).
+        Located in DDR3 SPD byte 12.
+        Located in DDR4 SPD byte 18.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR3 SPD byte 14 (LSB) and byte 15.
+        Located in DDR4 SPD byte 20 (LSB) through byte 23
+        The raw data has different meanings for DDR3 and DDR4.
+        HWPs must use this DDR neutral enumeration to decode.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_24 = 0x00100000,
+        CL_23 = 0x00080000,
+        CL_22 = 0x00040000,
+        CL_21 = 0x00020000,
+        CL_20 = 0x00010000,
+        CL_19 = 0x00008000,
+        CL_18 = 0x00004000,
+        CL_17 = 0x00002000,
+        CL_16 = 0x00001000,
+        CL_15 = 0x00000800,
+        CL_14 = 0x00000400,
+        CL_13 = 0x00000200,
+        CL_12 = 0x00000100,
+        CL_11 = 0x00000080,
+        CL_10 = 0x00000040,
+        CL_9  = 0x00000020,
+        CL_8  = 0x00000010,
+        CL_7  = 0x00000008,
+        CL_6  = 0x00000004,
+        CL_5  = 0x00000002,
+        CL_4  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TAAMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum CAS Latency Time (tAAmin).
+        Located in DDR3 SPD byte 16.
+        Located in DDR4 SPD byte 24.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRCDMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum RAS# to CAS# Delay Time (tRCDmin).
+        Located in DDR3 SPD byte 18.
+        Located in DDR4 SPD byte 25.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRPMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Row Precharge Delay Time (tRPmin).
+        Located in DDR3 SPD byte 20.
+        Located in DDR4 SPD byte 26.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRASMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Active to Precharge Delay Time (tRASmin).
+        Located in DDR3 SPD byte 21, bits 3-0 and byte 22 (LSB).
+        Located in DDR4 SPD byte 27, bits 3-0 and byte 28 (LSB)
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRCMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Active to Active/Refresh Delay Time (tRCmin).
+        Located in DDR3 SPD byte 21, bits 7-4 and byte 23 (LSB).
+        Located in DDR4 SPD byte 27, bits 7-4 and byte 29 (LSB)
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TFAWMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Four Activate Window Delay Time (tFAWmin).
+        Located in DDR3 SPD byte 28, bits 3-0 and byte 29 (LSB).
+        Located in DDR4 SPD byte 36, bits 3-0 and byte 37 (LSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_OPTIONAL_FEATURES</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Optional Features (bitmap).
+        Located in DDR3 SPD byte 30.
+        Located in DDR4 SPD byte 7, will be reserved and set to 0x0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DLL_OFF = 0x80, RZQ7 = 0x02, RZQ6 = 0x01</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Thermal and Refresh Options (bitmap).
+        Located in DDR3 SPD byte 31.
+        Located in DDR4 SPD byte 8, will be reserved and set to 0x0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>PASR = 0x80, ODTS = 0x08, ASR = 0x05, ETRR = 0x02, ETR = 0x01</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_THERMAL_SENSOR</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Thermal Sensor.
+        Located in DDR3 SPD byte 32.
+        Located in DDR4 SPD byte 14.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>PRESENT = 0x80, ACCURACY_MASK = 0x7F</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DEVICE_TYPE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type.
+        Located in DDR3 SPD byte 33, bit 7.
+        Located in DDR4 SPD byte 6, bit 7.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>STANDARD_MONOLITHIC = 0x00, NON_STANDARD = 0x01</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type Signal Loading for stacked DRAMs.
+        Located in DDR3 SPD byte 33, bits 1-0.
+        Located in DDR4 SPD byte 6, bit 1-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NOT_SPECIFIED = 0x00, MULTI_LOAD_STACK = 0x01, SINGLE_LOAD_STACK = 0x02</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DIE_COUNT</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type Die Count.
+        Located in DDR3 SPD byte 33, bits 6-4.
+        Located in DDR4 SPD byte 6, bit 6-4.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DIE1 = 0x00, DIE2 = 0x01, DIE4 = 0x02, DIE8 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TCKMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for SDRAM Minimum Cycle Time (tCKmin).
+        Located in DDR3 SPD byte 34.
+        Located in DDR4 SPD byte 125.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TAAMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for Minimum CAS Latency Time (tAAmin).
+        Located in DDR3 SPD byte 35.
+        Located in DDR4 SPD byte 123.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TRCDMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin).
+        Located in DDR3 SPD byte 36.
+        Located in DDR4 SPD byte 122.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TRPMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for Minimum Row Precharge Delay Time (tRPmin).
+        Located in DDR3 SPD byte 37.
+        Located in DDR4 SPD byte 121.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TRCMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin).
+        Located in DDR3 SPD byte 38.
+        Located in DDR4 SPD byte 120.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of Registers used on RDIMM.
+        Located in DDR3 SPD byte 63 bits 1-0.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_SPECIFIC_SECTION</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Specific Section.
+        Located in DDR3 SPD bytes 60d - 116d.
+        Located in DDR4 SPD bytes 128 - 255d.
+    </description>
+    <valueType>uint8</valueType>
+    <array>57</array>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module ID: Module Manufacturer's JEDEC ID Code.
+        Located in DDR3 SPD bytes 117 (LSB) to 118.
+        Located in DDR4 SPD bytes 320 (LSB) to 321.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_LOCATION</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module ID: Module Manufacturing Location.
+        Located in DDR3 SPD byte 119.
+        Located in DDR4 SPD byte 322.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_DATE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module ID: Module Manufacturing Date.
+        Located in DDR3 SPD bytes 120 (BCD year) to byte 121 (BCD week) (LSB).
+        Located in DDR4 SPD bytes 323 (BCD year) to byte 324 (BCD week) (LSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_ID_MODULE_SERIAL_NUMBER</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module ID: Module Serial Number.
+        Located in DDR3 SPD bytes 122 (LSB) to 125.
+        Located in DDR4 SPD bytes 325 (LSB) to 328.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CYCLICAL_REDUNDANCY_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Cyclical Redundancy Code.
+        Located in DDR3 SPD bytes 126 (LSB) to 127.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_PART_NUMBER</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Part Number.
+        Located in DDR3 SPD bytes 128 - 145.
+        Located in DDR4 SPD bytes 329 - 348.
+    </description>
+    <valueType>uint8</valueType>
+    <array>18</array>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR3 SPD bytes 146 (LSB) to 147.
+        Located in DDR4 SPD byte 349
+        The raw data has a different size for DDR3 and DDR4.
+        HWPs must use this DDR neutral attribute.
+        Platform support must call an Accessor HWP.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        DRAM Manufacturer JEDEC ID Code.
+        Located in DDR3 SPD bytes 148 (LSB) to 149.
+        Located in DDR4 SPD bytes 350 (LSB) to 351.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_BAD_DQ_DATA</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Bad DQ pin data stored in DIMM SPD. This data is in a special fomat.
+        This must only be called by a firmware HWP that knows how to
+        decode the data. HWP/PLAT firmware that needs to get/set the
+        Bad DQ Bitmap from a Centaur DQ point of view must use the
+        ATTR_BAD_DQ_BITMAP attribute.
+    </description>
+    <valueType>uint8</valueType>
+    <array>80</array>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes can be queried from DDR3 DIMMs only
+Querying them from DDR4 DIMMs will result in an error
+*******************************************************************************
+-->
+
+<attribute>
+    <id>ATTR_SPD_FTB_DIVIDEND</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Timebase Dividend.
+        Located in DDR3 SPD byte 9, bits 7-4.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FTB_DIVISOR</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Timebase Divisor.
+        Located in DDR3 SPD byte 9, bits 3-0.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MTB_DIVIDEND</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Medium Timebase Dividend.
+        Located in DDR3 SPD byte 10.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MTB_DIVISOR</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Medium Timebase Divisor.
+        Located in DDR3 SPD byte 11.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TWRMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Write Recovery Time (tWRmin).
+        Located in DDR3 SPD byte 17.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRRDMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Row Active to Row Active Delay Time (tRRDmin).
+        Located in DDR3 SPD byte 19.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRFCMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Refresh Recovery Delay Time (tRFCmin).
+        Located in DDR3 SPD byte 24 (LSB) and byte 25.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TWTRMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Internal Write to Read Command Delay Time (tWTRmin).
+        Located in DDR3 SPD byte 26.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRTPMIN</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum Internal Read to Precharge Command Delay Time (tRTPmin).
+        Located in DDR3 SPD byte 27.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_ADDR_MIRRORING</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced address mirroring attribute.
+        Located in DDR3 SPD byte 63 bits 1-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        NO_RANKS = 0x00,
+        ODD_RANKS = 0x01
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F0RC3_F0RC2</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F0RC3/F0RC2.
+        Timing control AND Drive strength, Address/Command AND QxCS_n
+        Located in DDR3 SPD byte 67.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F0RC5_F0RC4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F0RC5/F0RC4.
+        Drive strength, QxODT AND QxCKE and Clock.
+        Located in DDR3 SPD byte 68.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F1RC11_F1RC8</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F1RC11/F1RC8.
+        Extended delay for clocks, QxCS_n and QxODT AND QxCKE.
+        Located in DDR3 SPD byte 69.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F1RC13_F1RC12</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F1RC13/F1RC12.
+        Additive delay for QxCS_n and QxCA.
+        Located in DDR3 SPD byte 70.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F1RC15_F1RC14</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F1RC15/F1RC14.
+        Additive delay for QxODT and QxCKE.
+        Located in DDR3 SPD byte 71.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F3RC9_F3RC8_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F3RC9/F3RC8 for 800 AND 1066.
+        DRAM interface MDQ Termination and Drive strength.
+        Located in DDR3 SPD byte 72.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F34RC11_F34RC10_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[3,4]RC11/F[3,4]RC10 for 800 AND 1066.
+        Rank 0AND1 Read and Write QxODT control.
+        Located in DDR3 SPD byte 73.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F56RC11_F56RC10_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[5,6]RC11/F[5,6]RC10 for 800 AND 1066.
+        Rank 2AND3 Read and Write QxODT control.
+        Located in DDR3 SPD byte 74.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F78RC11_F78RC10_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[7,8]RC11/F[7,8]RC10 for 800 AND 1066.
+        Rank 4AND5 Read and Write QxODT control.
+        Located in DDR3 SPD byte 75.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F910RC11_F910RC10_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[9,10]RC11/F[9,10]RC10 for 800 AND 1066.
+        Rank 6AND7 Read and Write QxODT control.
+        Located in DDR3 SPD byte 76.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_MR12_FOR_800_1066</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced MR1,2 registers for 800 AND 1066.
+        DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.
+        Located in DDR3 SPD byte 77.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F3RC9_F3RC8_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F3RC9/F3RC8 for 1333 AND 1600.
+        DRAM interface MDQ Termination and Drive strength.
+        Located in DDR3 SPD byte 78.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F34RC11_F34RC10_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[3,4]RC11/F[3,4]RC10 for 1333 AND 1600.
+        Rank 0AND1 Read and Write QxODT control.
+        Located in DDR3 SPD byte 79.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F56RC11_F56RC10_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[5,6]RC11/F[5,6]RC10 for 1333 AND 1600.
+        Rank 2AND3 Read and Write QxODT control.
+        Located in DDR3 SPD byte 80.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F78RC11_F78RC10_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[7,8]RC11/F[7,8]RC10 for 1333 AND 1600.
+        Rank 4AND5 Read and Write QxODT control.
+        Located in DDR3 SPD byte 81.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F910RC11_F910RC10_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[9,10]RC11/F[9,10]RC10 for 1333 AND 1600.
+        Rank 6AND7 Read and Write QxODT control.
+        Located in DDR3 SPD byte 82.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_MR12_FOR_1333_1600</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced MR1,2 registers for 1333 AND 1600.
+        DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.
+        Located in DDR3 SPD byte 83.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F3RC9_F3RC8_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F3RC9/F3RC8 for 1866 AND 2133.
+        DRAM interface MDQ Termination and Drive strength.
+        Located in DDR3 SPD byte 84.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F34RC11_F34RC10_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[3,4]RC11/F[3,4]RC10 for 1866 AND 2133.
+        Rank 0AND1 Read and Write QxODT control.
+        Located in DDR3 SPD byte 85.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F56RC11_F56RC10_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[5,6]RC11/F[5,6]RC10 for 1866 AND 2133.
+        Rank 2AND3 Read and Write QxODT control.
+        Located in DDR3 SPD byte 86.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F78RC11_F78RC10_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[7,8]RC11/F[7,8]RC10 for 1866 AND 2133.
+        Rank 4AND5 Read and Write QxODT control.
+        Located in DDR3 SPD byte 87.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_F910RC11_F910RC10_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced F[9,10]RC11/F[9,10]RC10 for 1866 AND 2133.
+        Rank 6AND7 Read and Write QxODT control.
+        Located in DDR3 SPD byte 88.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_LR_MR12_FOR_1866_2133</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Load Reduced MR1,2 registers for 1866 AND 2133.
+        DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.
+        Located in DDR3 SPD byte 89.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes can be queried from DDR4 DIMMs only
+Querying them from DDR3 DIMMs will result in an error
+*******************************************************************************
+-->
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKGROUPS_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of bank groups.
+        Located in DDR4 SPD byte 4, bits 7-6.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>BG0 = 0x00, BG2 = 0x01, BG4 = 0x02</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TIMEBASE_MTB_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        defines a value in picoseconds that represents the fundamental timebase
+        for medium grain timing calculations. This value is used as a multiplier
+        for formulating subsequent timing parameters.
+        Located in DDR4 SPD byte 17, bits 3-2.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>PS125 = 0x00</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TIMEBASE_FTB_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        defines a value in picoseconds that represents the fundamental timebase
+        for fine grain timing calculations. This value is used as a multiplier
+        for formulating subsequent timing parameters.
+        Located in DDR4 SPD byte 17, bits 1-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>PS1 = 0x00</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TCKMAX_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Maximum cycle time (tCKmax).
+        Located in DDR4 SPD byte 19.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRFC1MIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units
+        Located in DDR4 SPD bytes 30(MSB) and 31(LSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRFC2MIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units
+        Located in DDR4 SPD bytes 32(MSB) and 33(LSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRFC4MIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Minimum SDRAM Refresh Recovery Time Dealy in medium timebase (MTB) units.
+        Located in DDR4 SPD byte 34(LSB) bits 15-8 and SPD byte 35(MSB) 7-0.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRRDSMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        The minimum SDRAM Activate to Activate Delay Time to different bank
+        groups in medium timebase (MTB) units. Controller designers must also
+        note that at some frequencies, a minimum number of clocks may be required
+        resulting in a larger tRRD_Smin value than indicated in the SPD.
+        For example, tRRD_Smin for DDR4-1600 must be 4 clocks.
+        Located in DDR4 SPD byte 38
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TRRDLMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        The minimum SDRAM Activate to Activate Delay Time to same  bank
+        groups in medium timebase (MTB) units. Controller designers must also
+        note that at some frequencies, a minimum number of clocks may be required
+        resulting in a larger tRRD_Smin value than indicated in the SPD.
+        For example, tRRD_Lmin for DDR4-1600 must be 4 clocks.
+        Located in DDR4 SPD byte 39
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_TCCDLMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        The minimum SDRAM CAS to CAS Delay Time to same  bank
+        groups in medium timebase (MTB) units. Controller designers must also
+        note that at some frequencies, a minimum number of clocks may be required
+        resulting in a larger tCCD_Lmin value than indicated in the SPD.
+        For example, tCCD_Lmin for DDR4-2133 must be 6 clocks.
+        Located in DDR4 SPD byte 40
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TCCDLMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Modifies the calculation of SPD Byte 40 with a fine correction
+        using FTB units. The value of tCCD_Lmin comes from the SDRAM data
+        sheet. This value is a two.s complement multiplier for FTB units,
+        ranging from +127 to -128.
+        Located in DDR4 SPD byte 117
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TRRDLMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Modifies the calculation of SPD Byte 39 with a fine correction using
+        FTB units. The value of tRRD_Lmin comes from the SDRAM data sheet.
+        This value is a two.s complement multiplier for FTB units,
+        ranging from +127 to -128.
+        Located in DDR4 SPD byte 118
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TRRDSMIN_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Modifies the calculation of SPD Byte 38 (MTB units) with a fine
+        correction using FTB units. The value of tRRD_Smin comes from the
+        SDRAM data sheet. This value is a two.s complement multiplier for
+        FTB units, ranging from +127 to -128.
+        Located in DDR4 SPD byte 119
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_FINE_OFFSET_TCKMAX_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmax).
+        Located in DDR4 SPD byte 124.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CRC_BASE_CONFIG_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        contains the calculated CRC for bytes 0~125 (0x000~0x07D) in the SPD
+        Located in DDR4 SPD byte 126(LSB) and 127(MSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_DRAM_STEPPING_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Defines the vendor die revision level (often called the .stepping.)
+        of the DRAMs on the module. This byte is optional.
+        For modules without DRAM stepping information, this byte should
+        be programmed to 0xFF.
+        Located in DDR4 SPD byte 352
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CRC_MNFG_SEC_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        contains the calculated CRC for bytes 320~381 (0x140~0x17D) in the SPD
+        Located in DDR4 SPD byte 382(LSB) and 383(MSB).
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_VERSION</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        The VPD Version of this DIMM.  The version number can be an indication of when different DIMM keywords are valid and is loaded from the platform.  A version number of zero is unknown.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes are DDR3 specific. Regular HWPs should query the DDR
+neutral attribute, these attributes should only be queried by the Accessor HWP
+that handles the DDR neutral attribute.
+*******************************************************************************
+-->
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKS_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR3 SPD byte 4, bits 6-4.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_SDRAM_BANKS.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR3 SPD byte 6, bits 2-0.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR3 SPD byte 14 (LSB) and byte 15.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_18 = 0x00004000,
+        CL_17 = 0x00002000,
+        CL_16 = 0x00001000,
+        CL_15 = 0x00000800,
+        CL_14 = 0x00000400,
+        CL_13 = 0x00000200,
+        CL_12 = 0x00000100,
+        CL_11 = 0x00000080,
+        CL_10 = 0x00000040,
+        CL_9  = 0x00000020,
+        CL_8  = 0x00000010,
+        CL_7  = 0x00000008,
+        CL_6  = 0x00000004,
+        CL_5  = 0x00000002,
+        CL_4  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR3</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR3 SPD bytes 146 (LSB) to 147.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes are DDR4 specific. Regular HWPs should query the DDR
+neutral attribute, these attributes should only be queried by the Accessor HWP
+that handles the DDR neutral attribute.
+*******************************************************************************
+-->
+<attribute>
+    <id>ATTR_SPD_SDRAM_BANKS_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of banks.
+        Located in DDR4 SPD byte 4, bits 5-4.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_SDRAM_BANKS.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>B4 = 0x00, B8 = 0x01</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Nominal voltage (bitmap).
+        Located in DDR4 SPD byte 11, bits 5-0.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE.
+    </description>
+    <valueType>uint8</valueType>
+    <!-- Note that current DDR4 spec has TBD for bits 2-5 -->
+    <enum>
+        OP1_2V = 0x01, END1_2V = 0x02,
+        OPTBD1V = 0x04, ENDTBD1V = 0x08,
+        OPTBD2V = 0x10, ENDTBD2V = 0x20
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        CAS Latencies supported (bitmap).
+        Located in DDR4 SPD byte 20 (LSB) through byte 23.
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED.
+    </description>
+    <valueType>uint32</valueType>
+    <enum>
+        CL_24 = 0x00020000,
+        CL_23 = 0x00010000,
+        CL_22 = 0x00008000,
+        CL_21 = 0x00004000,
+        CL_20 = 0x00002000,
+        CL_19 = 0x00001000,
+        CL_18 = 0x00000800,
+        CL_17 = 0x00000400,
+        CL_16 = 0x00000200,
+        CL_15 = 0x00000100,
+        CL_14 = 0x00000080,
+        CL_13 = 0x00000040,
+        CL_12 = 0x00000020,
+        CL_11 = 0x00000010,
+        CL_10 = 0x00000008,
+        CL_9  = 0x00000004,
+        CL_8  = 0x00000002,
+        CL_7  = 0x00000001
+    </enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODULE_REVISION_CODE_DDR4</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Revision Code.
+        Located in DDR4 SPD byte 349
+        This attribute must only be used by an Accessor HWP.
+        Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<!--
+*******************************************************************************
+The following attributes are from Centaur VPD. Consider moving them from this
+file
+*******************************************************************************
+-->
+
+<attribute>
+    <id>ATTR_VPD_DRAM_ADDRESS_MIRRORING</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>
+        The C-DIMM ranks that have address mirroring.
+        This data is in the Record:VSPD, Keyword:AM field in C-DIMM VPD.
+        This attribute is only valid for C-DIMMs, an error should be returned if queried from IS-DIMMs.
+    Note: Muliple ranks can be mirrored.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        RANK0_MIRRORED = 0x08,
+        RANK1_MIRRORED = 0x04,
+        RANK2_MIRRORED = 0x02,
+        RANK3_MIRRORED = 0x01
+    </enum>
+    <platInit/>
+    <array> 2 2</array>
+    <writeable/>
+</attribute>
+
+<!-- Attributes added to support the VPD which was formally using the EFF settings -->
+
+<attribute>
+    <id>ATTR_VPD_ODT_RD</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Read ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT),mss_eff_cnfg_termination
+consumer: various.C files and initfiles
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_ODT_WR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Write ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+Creator: VPD(MT)/ mss_eff_cnfg_termination
+consumer: various.C and initfile
+firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_RON</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Ron. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+OHM48 is for DDR4.
+creator: VPD(MT)/mss_eff_cnfg_termination
+consumer: various.C files (no initfile)
+firmware notes: none
+This Attribute is to be interpreted as an Integer </description>
+    <valueType>uint8</valueType>
+    <enum>INVALID = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_RTT_NOM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Rtt_Nom. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT),mss_eff_cnfg_termination
+consumer: various.C files (no initfiles)
+firmware notes: none
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_RTT_WR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Rtt_WR. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+Creator: VPD(MT), mss_eff_cnfg_termination
+consumer: various.C files (no initfiles)
+firmware notes: none
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0, OHM60 = 60, OHM120 = 120, OHM240 = 240, HIGHZ = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_WR_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: various.C and initfile
+firmware notes: none
+This is the nominal value
+This is for DDR3
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint32</valueType>
+    <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_WRDDR4_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value
+This is for DDR4
+The value is from 0 to 50</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_DRV_IMP_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT)/mss_eff_cnfg_termination
+consumer: initfile,various.C files
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM24_FFE0 = 0x0A, OHM30_FFE0 = 0x08,
+OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x18, OHM34_FFE0 = 0x07, OHM34_FFE480 = 0x47, OHM34_FFE240 = 0x37, OHM34_FFE160 = 0x27, OHM34_FFE120 = 0x17, OHM40_FFE0 = 0x06, OHM40_FFE480 = 0x46, OHM40_FFE240 = 0x36, OHM40_FFE160 = 0x26, OHM40_FFE120 = 0x16</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_DRV_IMP_ADDR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Address Drive Impedance Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: initfile and various.C
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_DRV_IMP_CNTL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Control Drive Impedance Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT)/mss_eff_cnfg_termination
+consumer: initfile,various .C
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_DRV_IMP_CLK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT),mss_eff_cnfg_termination
+consumer: initfiles,various
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_DRV_IMP_SPCKE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Spare Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT) , mss_eff_cnfg_termination
+consumer: initfiles, various.C
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_RCV_IMP_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD, mss_eff_cnfg_termination
+Consumer: initfile + C code
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_SLEW_RATE_DQ_DQS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or  is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT), mss_eff_cnfg_termination
+consumer: initfiles,various.C
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer except MAX</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_SLEW_RATE_ADDR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Address Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT),mss_eff_cnfg_termination
+consumer: initfile,various .C files
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer except Max</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_SLEW_RATE_CLK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Clock Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT)mss_eff_cnfg_termination
+consumer: initfile,various.C files
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer except max</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_SLEW_RATE_SPCKE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Spare Clock Slew Rate Used in various locations and comes from the MT keyword or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: initfile,various.C
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer except max</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7
+</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_SLEW_RATE_CNTL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Control Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: VPD(MT),mss_eff_cnfg_termination
+consumer:initfile, various .C files
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer except for max</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7
+</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_RD_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+Creator: VPD(MT) or mss_eff_cnfg_termination
+consumer: various.C and initfiles
+firmware notes: none
+This is the nominal value
+This Attribute is to be interpreted as an Integer</description>
+    <valueType>uint32</valueType>
+    <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CLK_P0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CLK_P1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CLK_P0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CLK_P1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A4</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A5</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A6</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A7</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A8</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A9</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A10</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A11</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A12</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A13</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A14</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_A15</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_BA2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_CASN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_RASN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_CMD_WEN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_PAR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_PAR</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M_ACTN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M_ACTN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CKE3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_CSN3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_ODT0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M0_CNTL_ODT1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CKE3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_CSN3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_ODT0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from MR keyword on the CDIMM VPD.  This controls the IO M1_CNTL_ODT1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <writeable/>
+</attribute>
+
+<!-- Spare attribute found in eclipz/hwpf/hwp/xml/attribute_info/dimm_attributes.xml -->
+<!-- <attribute> -->
+<!--     <id>ATTR_VPD_DIMM_SPARE</id>  -->
+<!--     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>  -->
+<!--     <description>Spare DRAM availability. It comes from the VPD or SPD in ISDIMM systems</description>  -->
+<!--     <valueType>uint8</valueType>  -->
+<!--     <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum>  -->
+<!--     <platInit/>  -->
+<!--     <odmVisable/>  -->
+<!--     <odmChangeable/>  -->
+<!--     <array> 2 2 4</array>  -->
+<!-- </attribute>  -->
+
+<attribute>
+    <id>ATTR_VPD_CKE_PRI_MAP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A.  Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D.  In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <array>2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CKE_PWR_MAP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A.  Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D. The values for Port A concatenated with port B forms the value for one MBA.  C concat D forms the value for the other MBA</description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <odmVisable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_GPO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A.  Bytes 125 for port B, 189 for port C and 253 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <array>2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_RLO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A.  Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <array>2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_WLO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A.  Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <array>2</array>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_TSYS_ADR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D.    This means that all ADR blocks use this value on an mba level</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <array>2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_TSYS_DP18</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D.  This means all DP18 blocks use this value on a mba level</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <array>2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Custom DIMM Sensor Map for Primary I2C Port (1 byte of data):
+0x00 No sensors attached
+0x01 DIMM sensor 0 attached
+0x02 DIMM sensor 1 attached
+0x04 DIMM sensor 2 attached
+0x08 DIMM sensor 3 attached
+0x10 DIMM sensor 4 attached
+0x20 DIMM sensor 5 attached
+0x40 DIMM sensor 6 attached
+0x80 DIMM sensor 7 attached
+Comes from the VPD MW Keyword</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data):
+0x00 No sensors attached
+0x01 DIMM sensor 0 attached
+0x02 DIMM sensor 1 attached
+0x04 DIMM sensor 2 attached
+0x08 DIMM sensor 3 attached
+0x10 DIMM sensor 4 attached
+0x20 DIMM sensor 5 attached
+0x40 DIMM sensor 6 attached
+0x80 DIMM sensor 7 attached
+Comes from the VPD MW Keyword</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DRAM_2N_MODE_ENABLED</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Describes if this MBA is in 2N address mode.  The DIMM attributes associated with this MBA describes if this mode is needed for SI. Come from the VPD and consumed in the mba_def.initfile.</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CDIMM_VPD_MASTER_POWER_SLOPE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Master Power Slope that comes from the VPD MW Keyword</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Master Power Intercept that comes from the VPD MW Keyword</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Supplier Power Slope that comes from the VPD the MV Keyword</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Supplier Power Intercept that comes from MV Keyword</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_L4_BANK_DELETE_VPD</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>L4 Bank Delete settings in VPD.
+Denotes what banks have been deleted from the L4.
+Data will be pulled from CDIMM VPD if CDIMM present.
+Data will be pulled from backplane VPD if IS DIMMs present.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <persistent/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODSPEC_COM_REF_RAW_CARD_REV</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Reference Raw Card Revision
+        Located in DDR3 SPD byte 62 bits 6-5.
+        Located in DDR4 SPD byte 130 bits 6-5.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_MODSPEC_COM_REF_RAW_CARD</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Reference Raw Card
+        Located in DDR3 SPD byte 62 bit 7 + bits 4-0.
+        Located in DDR4 SPD byte 130 bit 7 + bits 4-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+    A = 0x00, B = 0x01, C = 0x02, D = 0x03, E = 0x04, F = 0x05, G = 0x06, H = 0x07, J = 0x08, K = 0x09, L = 0x0a, M = 0x0b, N = 0x0c, P = 0x0d, R = 0x0e, T = 0x0f, U = 0x10, V = 0x11, W = 0x12, Y = 0x13, AA = 0x14, AB = 0x15, AC = 0x16, AD = 0x17, AE = 0x18, AF = 0x19, AG = 0x1a, AH = 0x1b, AJ = 0x1c, AK = 0x1d, AL = 0x1e, AM = 0x20, AN = 0x21, AP = 0x22, AR = 0x23, AT = 0x24, AU = 0x25, AV = 0x26, AW = 0x27, AY = 0x28, BA = 0x29, BB = 0x2a, BC = 0x2b, BD = 0x2c, BE = 0x2d, BF = 0x2e, BG = 0x2f, BH = 0x30, BJ = 0x31, BK = 0x32, BL = 0x33, BM = 0x34, BN = 0x35, BP = 0x36, BR = 0x37, BT = 0x38, BU = 0x39, BV = 0x3a, BW = 0x3b, BY = 0x3c, CA = 0x3d, CB = 0x3e, ZZ = 0x3f
+    </enum>
+    <platInit/>
+</attribute>
+
+
+</attributes>
diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile
index f6cd0e9f2..aa9c9f31e 100644
--- a/src/usr/hwpf/hwp/mc_config/makefile
+++ b/src/usr/hwpf/hwp/mc_config/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2012,2014
+# Contributors Listed Below - COPYRIGHT 2012,2014
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -24,6 +26,9 @@ ROOTPATH = ../../../../..
 
 MODULE = mc_config
 
+CFLAGS += $(if $(CONFIG_PALMETTO_VDDR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM)
+EXTRAINCDIR += $(if $(CONFIG_PALMETTO_VDDR), ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit)
+
 ##      support for Targeting and fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
index 2f5b1c0cb..43652cb08 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
@@ -48,7 +48,7 @@
 //   1.46  | kcook    |14-MAR-14| Fixed create_db_ddr4 stub function definition
 //   1.45  | kcook    |14-MAR-14| Added DDR4 support
 //   1.44  | mjjones  |07-MAR-14| Only compile if FAPI_MSSLABONLY defined
-//   1.43  | dcadiga  |04-MAR-14| Added in ISDimm support for KG 
+//   1.43  | dcadiga  |04-MAR-14| Added in ISDimm support for KG
 //   1.42  | asaetow  |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.H v1.2
 //   1.41  | dcadiga  |13-JAN-14| Removed checking of dimm type attribute for CDIMM, replaced with custom dimm type attribute
 //   1.40  | bellows  |02-JAN-14| VPD attribute removal
@@ -59,8 +59,8 @@
 //   1.35  | bellows  |16-SEP-13| Hostboot compile update.
 //   1.34  | kcook    |13-SEP-13| Updated define FAPI_LRDIMM token.
 //   1.33  | bellows  |12-SEP-13| set_vpd_dimm_spare function added before AM keyword shows up
-//   1.32  | kcook    |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C.       
-//   1.31  | kcook    |16-AUG-13| Added LRDIMM support.       
+//   1.32  | kcook    |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C.
+//   1.31  | kcook    |16-AUG-13| Added LRDIMM support.
 //   1.30  | dcadiga  |07-AUG-13| Fixed hostboot compile issue
 //   1.29  | dcadiga  |05-AUG-13| KG3 allowed, ifdef removed for lab card uint declaration, added 4R support to 1600, changed 4Rx4 / 4Rx8 RCD Drive Settings
 //   1.28  | asaetow  |05-AUG-13| Added temp workaround for incorrect byte33 SPD data in early lab OLD 16G/32G CDIMMs.
@@ -75,7 +75,7 @@
 //   1.20  | dcadiga  |30-APR-13| Fixed Hostboot Compile Error LN 972
 //   1.19  | dcadiga  |19-APR-13| Added Cdimm RCB/RCC, changed RDIMM settings for MBA0 so that a 1R card will work and a 4R card will work
 //   1.18  | dcadiga  |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift
-//   1.17  | asaetow  |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. 
+//   1.17  | asaetow  |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333.
 //   1.16  | dcadiga  |25-MAR-13| Added in 2N Addressing Mode.
 //   1.15  | dcadiga  |14-MAR-13| Fixed simulation issue.
 //   1.14  | dcadiga  |12-MAR-13| Code re-write for new dimms.  Confirmed working on all systems
@@ -88,11 +88,11 @@
 //         |          |         | Fixed (l_attr_is_simulation || 1) to (l_attr_is_simulation != 0) from v1.8 and v1.9.
 //   1.9   | bellows  |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks
 //   1.8   | bellows  |06-DEC-12| Added sim leg for rotator values
-//   1.7   | asaetow  |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. 
+//   1.7   | asaetow  |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF.
 //   1.6   | asaetow  |17-NOV-12| Fixed uint8_t attr_eff_odt_wr for 4R RDIMMs.
 //   1.5   | asaetow  |17-NOV-12| Added PR settings.
 //         |          |         | Fixed RCD settings for RDIMM.
-//   1.4   | asaetow  |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. 
+//   1.4   | asaetow  |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F.
 //   1.3   | asaetow  |05-NOV-12| Added Paul's SI value for pre-machine parsable workbook.
 //         |          |         | NOTE: DO NOT pick-up without memory_attributes.xml v1.45 or newer.
 //   1.2   | asaetow  |05-SEP-12| Added ATTR_MSS_CAL_STEP_ENABLE.
@@ -126,16 +126,16 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba,
                                   uint32_t *var_array_p_array[5])
 {
    ReturnCode rc;
-   
+
    FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_REWRITE_INVALID_EXEC);
    return rc;
 
 }
-ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) 
+ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba)
 {
    ReturnCode rc;
-   
+
 
    FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_TERM_INVALID_EXEC);
@@ -148,7 +148,7 @@ ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba)
 fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba)
 {
    ReturnCode rc;
-   
+
    FAPI_ERR("Invalid exec of mss_create_rcd_ddr4 on %s!", i_target_mba.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_RCD_DDR4_INVALID_EXEC);
    return rc;
@@ -157,7 +157,7 @@ fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba)
 fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba)
 {
    ReturnCode rc;
-   
+
 
    FAPI_ERR("Invalid exec of mss_create_db_ddr4 on %s!", i_target_mba.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_DB_DDR4_INVALID_EXEC);
@@ -167,7 +167,7 @@ fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba)
 fapi::ReturnCode mss_lrdimm_ddr4_term_atts(const Target& i_target_mba)
 {
    ReturnCode rc;
-  
+
 
    FAPI_ERR("Invalid exec of mss_lrdimm_ddr4_term_atts on %s!", i_target_mba.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_TERM_ATTS_INVALID_EXEC);
@@ -275,7 +275,7 @@ uint8_t attr_vpd_cen_phase_rot_m1_cntl_odt1[PORT_SIZE];
 
 //Declare the different dimms here:
 //Cdimm rc_A
-uint32_t cdimm_default[STORE_ARRAY_SIZE] = 
+uint32_t cdimm_default[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
@@ -283,7 +283,7 @@ uint32_t cdimm_rca_1r_1333_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
-uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = 
+uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
@@ -306,100 +306,100 @@ uint32_t cdimm_rcb4_2r_1600_mba1[210] =
 /*
 
 //RDIMM A/B Ports MBA0 Glacier
-uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
 
 //RDIMM C/D Ports MBA1 Glacier
 
-uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
 
-uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = 
+uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
 //UDIMM TEMP FOR JAKE ICICLE
-uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = 
+uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
-uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = 
+uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
 };
 
 
-//KG3 
+//KG3
 
 uint32_t rdimm_kg3_1333_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
 };
@@ -454,99 +454,99 @@ uint32_t rdimm_kg3_1600_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RC
 
 
 //RDIMM A/B Ports MBA0 Glacier
-uint32_t rdimm_glacier_1600_r10_mba0[210] = 
+uint32_t rdimm_glacier_1600_r10_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r20e_mba0[210] = 
+uint32_t rdimm_glacier_1333_r20e_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r20e_mba0[210] = 
+uint32_t rdimm_glacier_1600_r20e_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r20b_mba0[210] = 
+uint32_t rdimm_glacier_1333_r20b_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r20b_mba0[210] = 
+uint32_t rdimm_glacier_1600_r20b_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r40_mba0[210] = 
+uint32_t rdimm_glacier_1333_r40_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 //RDIMM C/D Ports MBA1 Glacier
 
-uint32_t rdimm_glacier_1333_r10_mba1[210] = 
+uint32_t rdimm_glacier_1333_r10_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r10_mba1[210] = 
+uint32_t rdimm_glacier_1600_r10_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r20e_mba1[210] = 
+uint32_t rdimm_glacier_1333_r20e_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r20e_mba1[210] = 
+uint32_t rdimm_glacier_1600_r20e_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r20b_mba1[210] = 
+uint32_t rdimm_glacier_1333_r20b_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r20b_mba1[210] = 
+uint32_t rdimm_glacier_1600_r20b_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1066_r40_mba1[210] = 
+uint32_t rdimm_glacier_1066_r40_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r11_mba1[210] = 
+uint32_t rdimm_glacier_1333_r11_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r11_mba1[210] = 
+uint32_t rdimm_glacier_1600_r11_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r22e_mba1[210] = 
+uint32_t rdimm_glacier_1333_r22e_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r22e_mba1[210] = 
+uint32_t rdimm_glacier_1600_r22e_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1333_r22b_mba1[210] = 
+uint32_t rdimm_glacier_1333_r22b_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1600_r22b_mba1[210] = 
+uint32_t rdimm_glacier_1600_r22b_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t rdimm_glacier_1066_r44_mba1[210] = 
+uint32_t rdimm_glacier_1066_r44_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 //UDIMM TEMP FOR JAKE ICICLE
-uint32_t udimm_glacier_1600_r10_mba0[210] = 
+uint32_t udimm_glacier_1600_r10_mba0[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
-uint32_t udimm_glacier_1600_r10_mba1[210] = 
+uint32_t udimm_glacier_1600_r10_mba1[210] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 
-//KG3 
+//KG3
 
 uint32_t rdimm_kg3_1333_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
 };
@@ -646,7 +646,7 @@ extern "C" {
     uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
     uint8_t l_stack_type_u8array[PORT_SIZE][DIMM_SIZE];
     uint8_t l_dimm_size_u8array[PORT_SIZE][DIMM_SIZE];
-   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, 
+   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2,
     uint8_t l_dram_gen_u8;
    // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
     uint8_t l_dimm_type_u8;
@@ -705,7 +705,7 @@ extern "C" {
         if ((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (l_stack_type_u8array[cur_port][cur_dimm] == fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP) && (l_dram_width_u8 == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (l_dimm_size_u8array[cur_port][cur_dimm] == 4)) {
           FAPI_INF("WARNING: Wrong Byte33 SPD detected for OLD 16G/32G CDIMM on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm);
           FAPI_INF("WARNING: Implimenting workaround on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm);
-          l_stack_type_modified = 1; 
+          l_stack_type_modified = 1;
           l_stack_type_u8array[cur_port][cur_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
         }
       }
@@ -742,7 +742,7 @@ extern "C" {
 
       }
       else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){
-        memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t));  
+        memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t));
 
       }
       else{
@@ -761,7 +761,7 @@ extern "C" {
       //FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
       if( l_target_mba_pos == 0){
         if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {     
+          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
                //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
             memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t));
             FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
@@ -786,14 +786,14 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps); return rc;
-            
+
           }
 
 
         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {     
+          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
                //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); 
+            memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t));
             FAPI_INF("LRDIMM: Base - KG3 LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
           }
           else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
@@ -819,17 +819,17 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps); return rc;
-            
+
           }
-        }//1600      
+        }//1600
       }//MBA0
       else{
         if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {     
+          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
                //Removed Width Check, use settings for either x8 or x4,
             memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t));
             FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          } 
+          }
           else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
             memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,210*sizeof(uint32_t));
             FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
@@ -850,12 +850,12 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps_MBA1); return rc;
-            
+
           }
 
 
         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {     
+          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
                //Removed Width Check, use settings for either x8 or x4
             memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t));
             FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
@@ -883,9 +883,9 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps_MBA1); return rc;
-            
+
           }
-        }//1600      
+        }//1600
       }//MBA1
     }
 #endif
@@ -921,7 +921,7 @@ extern "C" {
 
             else{
                FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq);
-               
+
 	       FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1333Mbps); return rc;
             }
               //    memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t));
@@ -957,7 +957,7 @@ extern "C" {
 
             else{
                FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq);
-               
+
 	       FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1600Mbps); return rc;
             }
          }//1600
@@ -965,7 +965,7 @@ extern "C" {
    }
 
 
-    else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ 
+    else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){
       if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) {
 
          //This is a CDIMM!
@@ -990,7 +990,7 @@ extern "C" {
                }
               else{
                  FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq);
-                
+
 		 FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_B4_1600Mbps); return rc;
               }
             }
@@ -1010,14 +1010,14 @@ extern "C" {
             }
             else{
               FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq);
-              
+
 	      FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc;
 
             }
           }
           else{
             FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq);
-            
+
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc;
           }
         }
@@ -1029,14 +1029,14 @@ extern "C" {
             }
             else{
               FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq);
-              
+
 	      FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc;
 
             }
           }
           else{
             FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq);
-            
+
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc;
           }
         }
@@ -1071,7 +1071,7 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1333Mbps); return rc;
-            
+
           }
 
         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
@@ -1099,51 +1099,51 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1600Mbps); return rc;
-            
+
           }
-        }//1600      
+        }//1600
       }//MBA0
       else{
         if ( l_mss_freq <= 1200 ) { // 1066Mbps
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){  
+          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
             memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());  
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){  
-            memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t));  
             FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
+            memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t));
+            FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+          }
           else{
             FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1066Mbps); return rc;
-            
+
           }
 
         } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){  
-            memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t));  
+          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
+            memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){  
-            memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t));  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
+            memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){  
-            memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t));  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){
+            memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){
             memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());  
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){  
-            memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); 
-            FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); 
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){  
-            memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); 
-            FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); 
-          }        
+            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){
+            memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t));
+            FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){
+            memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t));
+            FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+          }
           else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
                //Use 4R MBA0 settings for CD only!
             memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
@@ -1154,35 +1154,35 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1333Mbps); return rc;
-            
+
           }
         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
 
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){  
-            memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t));  
+          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
+            memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){  
-            memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t));  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
+            memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){  
-            memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); 
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){
+            memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
 
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){
             memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());  
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){  
-            memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t));  
+            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){
+            memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }        
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){  
-            memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t));  
+          }
+          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){
+            memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t));
             FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          } 
+          }
           else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
                //Use 4R MBA0 1333 settings for CD only!
             memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
@@ -1191,7 +1191,7 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1600Mbps); return rc;
-            
+
           }
         }//1600
       }//MBA1
@@ -1224,7 +1224,7 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d HERE MBA1\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1333Mbps); return rc;
-            
+
           }
         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
 
@@ -1239,7 +1239,7 @@ extern "C" {
           else{
             FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA1\n",l_mss_freq);
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1600Mbps); return rc;
-            
+
           }
         }
       }//MBA1
@@ -1256,7 +1256,7 @@ extern "C" {
 
         uint32_t *p_b_var_array = &base_var_array[0];
 
-        uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array, 
+        uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array,
         p_1600_x4_mba1_array, p_1600_x8_mba1_array};
 
         rc = mss_lrdimm_rewrite_odt(i_target_mba, p_b_var_array, var_array_p_array);
@@ -1264,7 +1264,7 @@ extern "C" {
         if(rc)
         {
           FAPI_ERR("FAILED LRDIMM rewrite ODT_RD");
-          
+
 	  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_ODT_RD); return rc;
         }
       }
@@ -1272,7 +1272,7 @@ extern "C" {
     else{
       FAPI_ERR("Invalid Dimm Type of %d", l_dimm_type_u8);
       FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_TYPE); return rc;
-      
+
     }
 
    // Now Set All The Attributes
@@ -1280,15 +1280,15 @@ extern "C" {
     attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++];             // keep 0
     attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++];             // keep 1
     attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++];             // keep 2
-    attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++];             // keep 3 
+    attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++];             // keep 3
     attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++];     // keep 4
     attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++];     // keep 5
     attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++];     // keep 6
     attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++];     // keep 7
 
 
-   //Fix for VPD Mode for lab rdimm 
-    if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){
+   //Fix for VPD Mode for lab rdimm
+    if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) )){
       FAPI_INF("RON i %d SHOULD NOT BE HERE\n",i);
       attr_vpd_dram_ron[0][0] = base_var_array[i++];
       attr_vpd_dram_ron[0][1] = base_var_array[i++];
@@ -1717,8 +1717,8 @@ extern "C" {
 
   //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination
 
-    if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && 
-         ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || 
+    if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 &&
+         ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ||
            (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) {
 
       rc = mss_create_rcd_ddr4(i_target_mba);
@@ -1730,7 +1730,7 @@ extern "C" {
       if (rc)
       {
         FAPI_ERR("Setting DDR4 RCD words failed \n");
-        
+
 	FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_RCD); return rc;
       }
 
@@ -1746,7 +1746,7 @@ extern "C" {
             if(l_dram_width_u8 == 4){
               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005050080210000LL;
             }
-            else {						       
+            else {
               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550080210000LL;
 
             }
@@ -1757,10 +1757,10 @@ extern "C" {
           } else {
             l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0000000000000000LL;
           }
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; 
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask;
           if ( l_mss_freq <= 933 ) {         // 800Mbps
             l_mss_freq_mask = 0x0000000000000000LL;
           } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
@@ -1777,11 +1777,11 @@ extern "C" {
             l_mss_volt_mask = 0x0000000000000000LL;
           } else if ( l_mss_volt >= 1270 ) { // 1.35V
             l_mss_volt_mask = 0x0000000000010000LL;
-          } else {                           // 1.2V 
+          } else {                           // 1.2V
             FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString());
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_VOLT); return rc;
-            
-          } 
+
+          }
           if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) {
             l_rcd_ibt_mask = 0x0000000070000000LL;
           } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) {
@@ -1795,7 +1795,7 @@ extern "C" {
           } else {
             FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString());
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_IBT); return rc;
-            
+
           }
           if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) {
             l_rcd_mirror_mode_mask = 0x0000000000000000LL;
@@ -1804,13 +1804,13 @@ extern "C" {
           } else {
             FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString());
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_MIRROR_MODE); return rc;
-	    
-            
+
+
           }
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; 
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; 
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask;
+          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask;
         }
       }
     }
@@ -1925,7 +1925,7 @@ extern "C" {
           attr_eff_wlo[1] = (uint8_t)0;
           attr_eff_gpo[0] = (uint8_t)5;
           attr_eff_gpo[1] = (uint8_t)5;
-*/     
+*/
       if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) {
       // Set for CDIMM B4
           attr_eff_rlo[0] = (uint8_t)0;
@@ -1955,13 +1955,13 @@ extern "C" {
          attr_eff_rlo[0] = (uint8_t)5;
          attr_eff_rlo[1] = (uint8_t)5;
          attr_eff_wlo[0] = (uint8_t)1;
-         attr_eff_wlo[1] = (uint8_t)1; 
-       } 
+         attr_eff_wlo[1] = (uint8_t)1;
+       }
        else {
          attr_eff_rlo[0] = (uint8_t)6;
          attr_eff_rlo[1] = (uint8_t)6;
          attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement
-         attr_eff_wlo[1] = (uint8_t)255; 
+         attr_eff_wlo[1] = (uint8_t)255;
       }
       attr_eff_gpo[0] = (uint8_t)7;
       attr_eff_gpo[1] = (uint8_t)7;
@@ -1970,9 +1970,9 @@ extern "C" {
     else{
       FAPI_ERR("Invalid Card Type RLO Settings \n");
       FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_CARD_TYPE_RLO); return rc;
-      
 
-    } 
+
+    }
 
 
 
@@ -2014,9 +2014,9 @@ extern "C" {
 
    // Set attributes
     rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
-    if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD 
+    if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD
        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-    } 
+    }
     rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc;
     rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc;
     rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
@@ -2053,7 +2053,7 @@ extern "C" {
        || (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ){
       FAPI_INF("IN RDIMM ATTR SETTING\n");
       rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
-      if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD 
+      if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD
         rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
       }
       rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc;
@@ -2213,12 +2213,12 @@ extern "C" {
 
 
     if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)
-    {  
+    {
        if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-       { 
+       {
           rc = mss_lrdimm_term_atts(i_target_mba);
        }
-       else 
+       else
        {
           rc = mss_lrdimm_ddr4_term_atts(i_target_mba);
        }
@@ -2226,7 +2226,7 @@ extern "C" {
       if (rc)
       {
         FAPI_ERR("Setting LR term atts failed \n");
-        
+
 	FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_SETTING_LRDIMM_TERM_ATTRS); return rc;
       }
     }
@@ -2262,7 +2262,7 @@ extern "C" {
       {
         FAPI_ERR("Error retrieving assodiated dimms");
 	FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_ERROR_RETRIEVING_DIMMS); return rc;
-        
+
         break;
       }
 //------------------------------------------------------------------------------
@@ -2378,6 +2378,7 @@ extern "C" {
           return rc;
         }
 
+#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
         uint32_t slope = 0x0000c1be;
         uint32_t intercept = 0x0000c06a;
         rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE, &target_chip, slope);
@@ -2391,6 +2392,7 @@ extern "C" {
 
         rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT, &target_chip, intercept);
         if (rc) return rc;
+#endif
       }
       if(rc) break;
  ////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index a3b818286..9359588ca 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2011,2014
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -180,8 +182,8 @@ HWP_ATTR_XML_FILES += hwp/L2_L3_attributes.xml
 HWP_ATTR_XML_FILES += hwp/scratch_attributes.xml
 HWP_ATTR_XML_FILES += hwp/system_attributes.xml
 HWP_ATTR_XML_FILES += hwp/chip_attributes.xml
-HWP_ATTR_XML_FILES += hwp/dimm_spd_attributes.xml
-HWP_ATTR_XML_FILES += hwp/dimm_attributes.xml
+HWP_ATTR_XML_FILES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), hwp/lab_dimm_spd_attributes.xml, hwp/dimm_spd_attributes.xml)
+HWP_ATTR_XML_FILES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), hwp/lab_dimm_attributes.xml, hwp/dimm_attributes.xml)
 HWP_ATTR_XML_FILES += hwp/unit_attributes.xml
 HWP_ATTR_XML_FILES += hwp/freq_attributes.xml
 HWP_ATTR_XML_FILES += hwp/ei_bus_attributes.xml
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index 6dc433c3d..191ac983e 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2012,2014
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -61,8 +63,8 @@ FAPI_ATTR_SOURCES += L2_L3_attributes.xml
 FAPI_ATTR_SOURCES += scratch_attributes.xml
 FAPI_ATTR_SOURCES += system_attributes.xml
 FAPI_ATTR_SOURCES += chip_attributes.xml
-FAPI_ATTR_SOURCES += dimm_spd_attributes.xml
-FAPI_ATTR_SOURCES += dimm_attributes.xml
+FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_spd_attributes.xml, dimm_spd_attributes.xml)
+FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_attributes.xml, dimm_attributes.xml)
 FAPI_ATTR_SOURCES += unit_attributes.xml
 FAPI_ATTR_SOURCES += freq_attributes.xml
 FAPI_ATTR_SOURCES += ei_bus_attributes.xml
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index a70223770..f97564f55 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1413,7 +1413,7 @@
     <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute>
 
     <attribute><id>VPD_REC_NUM</id></attribute>
-
+    <attribute><id>MSS_EFF_VPD_VERSION</id></attribute>
 </targetType>
 
 <targetType>
diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile
index 43c4f79f5..6d1fff381 100644
--- a/src/usr/targeting/xmltohb/makefile
+++ b/src/usr/targeting/xmltohb/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2011,2014
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -91,7 +93,7 @@ GENFILES = ${XMLTOHB_TARGETS}
 
 EXTRA_PARTS = $(addprefix $(IMGDIR)/, $(XMLTOHB_SYSTEM_BINARIES))
 
-CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES}) 
+CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES})
 CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES:.bin=.xml})
 CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_GENERIC_XML}
 CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_FAPI_XML}