INTRP HW Workaround for Clockgating Issue

  - The issue occurs because the slave procs route their interrupts
    to the master proc, which forces the LSI Interrupt event over the
    PSIHB. However, the master is still using the local wire for its
    LSI Interrupt events. There is a situation where undesirable
    hw behavior can occur because of this (dropped/missed interrupts)

  - This workaround will set the ESB Notification Register on the
    master proc, which will force the lsi interrupts over the PSIHB
    and not the local wire.

Change-Id: If595f62d268b6ac504f714b7e50e452b9f926015
CQ: SW441117
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74719
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 23 insertions, 9 deletions

diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index 5a89ba378..d198610af 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -234,8 +234,8 @@ errlHndl_t IntrRp::resetIntpForMpipl()
         {
             if (*targ_itr != iv_masterHdlr)
             {
-                TRACDCOMP(g_trac_intr, "IntrRp::resetIntpForMpipl() Setting up Slave Proc Interrupt Routing for proc %lx", get_huid((*targ_itr)->proc));
-                enableSlaveProcInterruptRouting(*targ_itr);
+                TRACDCOMP(g_trac_intr, "IntrRp::resetIntpForMpipl() Setting up LSI Interrupt Routing for proc %lx", get_huid((*targ_itr)->proc));
+                routeLSIInterrupts(*targ_itr);
             }
         }
 
@@ -528,6 +528,11 @@ errlHndl_t IntrRp::_init()
                 break;
             }
 
+            //Route LSI interrupt events over PSIHB instead of local wire
+            // This is a HW Bug Workaround for slaves using the PSIHB and
+            // the master using the local wire
+            routeLSIInterrupts(l_procIntrHdlr);
+
             enableLsiInterrupts();
         }
         else
@@ -542,6 +547,11 @@ errlHndl_t IntrRp::_init()
                 break;
             }
 
+            //Route LSI interrupt events over PSIHB instead of local wire
+            // This is a HW Bug Workaround for slaves using the PSIHB and
+            // the master using the local wire
+            routeLSIInterrupts(l_procIntrHdlr);
+
             enableLsiInterrupts();
 
             TRACFCOMP(g_trac_intr, "IntrRp::_init() Enabling PSIHB Interrupts");
@@ -987,7 +997,7 @@ errlHndl_t IntrRp::enableInterrupts(intr_hdlr_t *i_proc)
     return err;
 }
 
-void IntrRp::enableSlaveProcInterruptRouting(intr_hdlr_t *i_proc)
+void IntrRp::routeLSIInterrupts(intr_hdlr_t *i_proc)
 {
     PSIHB_SW_INTERFACES_t * l_psihb_ptr = i_proc->psiHbBaseAddr;
 
@@ -3562,9 +3572,9 @@ errlHndl_t INTR::IntrRp::enableSlaveProcInterrupts(TARGETING::Target * i_target)
             break;
         }
 
-        //Setup the PSIHB interrupt routing to route interrupts from nom-master
+        //Setup the PSIHB interrupt routing to route interrupts from non-master
         //  proc back to master proc
-        enableSlaveProcInterruptRouting(l_procIntrHdlr);
+        routeLSIInterrupts(l_procIntrHdlr);
 
     } while(0);
 
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index c749c1433..d838c4d6b 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -739,11 +739,15 @@ namespace INTR
 
             /**
              * Set correct PSIHB Regs to route + enable LSI interrupts from
-             * non-master proc to correct address on master proc
+             * any proc to correct address on master proc.
+             *
+             * This is used on the master proc as a workaround for a HW bug
+             * involving lsi triggers on the local wire. This forces the lsi
+             * trigger over the PSIHB working around the HW issue
              * @param[in] i_proc, the proc intrp handler
              * @return void
              */
-            void enableSlaveProcInterruptRouting(intr_hdlr_t* i_proc);
+            void routeLSIInterrupts(intr_hdlr_t* i_proc);
 
             /**
              * Initialize the IRSCReg to enable PSI to present interrupts