PM: Design changes in SGPE Boot copier and boot loader.

    - Use of consolidated SRAM Image Size to load SGPE Image.
    - Use of trap instead of self loop for interrupts.
    - Incorporation of SGPE Progress code debug of SGPE Booting

Change-Id: I898f0966a727b76b31f3a737f91cdaa26b71558e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34220
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34221
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 31 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index f03d380fc..41a391c68 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -161,6 +161,8 @@ HCD_CONST(QPMR_AUX_DATA_OFFSET_BYTE,            0x50)
 HCD_CONST(QPMR_AUX_DATA_LENGTH_BYTE,            0x54)
 HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE,           0x58)
 HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE,           0x5C)
+HCD_CONST(QPMR_SGPE_BOOT_PROG_CODE,             0x60)
+HCD_CONST(QPMR_SGPE_IMAGE_SIZE,                 0x64)
 
 /// SGPE Boot
 
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
index 26510a675..ee2df7372 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
@@ -94,8 +94,20 @@ HCD_CONST(OCC_SRAM_PGPE_IMAGE_LENGTH_ADDR,
 
 //--------------------------------------------------------------------------------------
 
-/// SGPE Base
+// Misc constants used in SGPE boot loader and boot copier.
+HCD_CONST(DIVDE_BY_8,  3)
+HCD_CONST(DOUBLE_WORD_SIZE,  8)
+HCD_CONST(SGPE_BOOT_PROG_CODE_POS,  QPMR_SGPE_BOOT_PROG_CODE)
+HCD_CONST(SGPE_SRAM_IMG_SIZE_POS,   QPMR_SGPE_IMAGE_SIZE)
+HCD_CONST(SGPE_IMG_OFFSET_POS,      40)
+HCD_CONST(BOOT_COPIER_LEN_ZERO,     0)
+HCD_CONST(ENABLE_TRAP,              0)
+HCD_CONST(SGPE_BOOT_COPY_SUCCESS,   0x42432d53 ) // ASCII code for BC-S
+HCD_CONST(SGPE_BOOT_COPIER_FAIL,    0x42432d46 ) // ASCII code for BC-F
+HCD_CONST(SGPE_BOOT_LOADER_SUCCESS, 0x424c2d53 ) // ASCII code for BL-S
+HCD_CONST(SGPE_BOOT_LOADER_FAIL,    0x424c2d46 ) // ASCII code for BL-F
 
+/// SGPE Base
 HCD_CONST(OCC_SRAM_SGPE_BASE_ADDR,
           (OCC_SRAM_BASE_ADDR + OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL + OCC_SRAM_PGPE_REGION_SIZE))
 HCD_CONST(OCC_SRAM_SGPE_END_ADDR,
@@ -122,6 +134,7 @@ HCD_CONST(OCC_SRAM_SGPE_BOOT_LOADER_RESET_ADDR,
 HCD_CONST(OCC_SRAM_SGPE_QPMR_HEADER_ADDR,
           (OCC_SRAM_SGPE_BOOT_LOADER_ADDR - OCC_SRAM_SGPE_COPY_QPMR_HEADER_SIZE))
 
+
 /// SGPE Copy
 
 HCD_CONST(OCC_SRAM_SGPE_HCODE_OFFSET_ADDR,
@@ -138,4 +151,5 @@ HCD_CONST(OCC_SRAM_QUAD_SPECIFIC_RINGS_LENGTH_ADDR,
           (OCC_SRAM_SGPE_QPMR_HEADER_ADDR + QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE))
 
 
+
 #endif /* __P9_HCD_MEMMAP_OCC_SRAM_H__ */
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index f6b9eea72..9774a2eda 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -94,6 +94,8 @@ HCD_HDR_UINT32( quadAuxOffset, 0);
 HCD_HDR_UINT32( quadAuxLength, 0);
 HCD_HDR_UINT32( stopFfdcOffset, 0);
 HCD_HDR_UINT32( stopFfdcLength, 0);
+HCD_HDR_UINT32( sgpeBootProgCode, 0 );
+HCD_HDR_UINT32( sgpeSramImageSize, 0 );
 HCD_HDR_PAD(512);
 #ifdef __ASSEMBLER__
 .endm
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 6c0898631..704600c9c 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -33,6 +33,8 @@
 // *HWP Level:          2
 // *HWP Consumed by:    Hostboot: Phyp
 
+// *INDENT-OFF*
+
 //--------------------------------------------------------------------------
 // Includes
 //--------------------------------------------------------------------------
@@ -473,11 +475,10 @@ fapi2::ReturnCode validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t&
     uint32_t rc = IMG_BUILD_SUCCESS;
 
     ImgSizeBank sizebank;
-    sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
     cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
+    QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader);
     PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader;
-
-    o_sramImgSize =  SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset);
+    o_sramImgSize =  SWIZZLE_4_BYTE(pQpmrHdr->sgpeSramImageSize);
 
     rc = sizebank.isSizeGood( PLAT_SGPE, SGPE_SRAM_IMAGE, o_sramImgSize, NULL , 0 );
     FAPI_IMP("SGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" );
@@ -902,6 +903,11 @@ void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrH
 {
     QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader);
     sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
+    io_qpmrHdr.sgpeSramImageSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) +
+                                   SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength) +
+                                   SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength);
+
+    io_qpmrHdr.sgpeSramImageSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeSramImageSize);
     memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) );
     pQpmrHdr->magic_number                  =   SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER);
     pSgpeHdr->g_sgpe_magic_number           =   SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER);
@@ -927,6 +933,7 @@ void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrH
     FAPI_DBG("  Quad Spec Ring Length   : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) );
     FAPI_INF("  Quad SCOM Offset        : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomOffset) );
     FAPI_INF("  Quad SCOM Length        : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomLength) );
+    FAPI_DBG("  SGPE SRAM Img Size      : 0x%08x", SWIZZLE_4_BYTE(pQpmrHdr->sgpeSramImageSize ) );
     FAPI_DBG("==============================QPMR Ends==============================");
 
     FAPI_DBG("===========================SGPE Image Hdr=============================");
@@ -3585,3 +3592,5 @@ fapi_try_exit:
 } //namespace p9_hcodeImageBuild ends
 
 }// extern "C"
+
+// *INDENT-ON*