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author | Brian Silver <bsilver@us.ibm.com> | 2016-03-16 11:05:46 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-04-01 21:28:31 -0400 |
commit | 1c1e314c6f0c88d9e10a3e1eec28eae152db9db5 (patch) | |
tree | 9b2acf7f5de1f0431a5fda1a24a0bb7c6a05e08e | |
parent | 271394c48faaa6177fec4d9e85d6a4043cc96044 (diff) | |
download | blackbird-hostboot-1c1e314c6f0c88d9e10a3e1eec28eae152db9db5.tar.gz blackbird-hostboot-1c1e314c6f0c88d9e10a3e1eec28eae152db9db5.zip |
Add dp16 io tx dll/vreg config
Move scom blastah
Change-Id: Ib3cb5d46bd4e71f99053adf242de2db01831e61e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22130
Tested-by: Jenkins Server
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22785
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
4 files changed, 237 insertions, 89 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index d52c6e7eb..933589006 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -40,6 +40,7 @@ #include <utils/bit_count.H> #include <utils/dump_regs.H> +#include <utils/scom.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_PROC_CHIP; @@ -54,89 +55,6 @@ namespace mss { /// -/// @brief Blast one peice of data across a vector of addresses -/// @param[in] i_target the target for the scom -/// @param[in] i_addrs const std::vector<uint64_t>& addresses -/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast -/// @return FAPI2_RC_SUCCESS iff ok -/// @note Author is originally from Boston (Pahk mah cah in Havahd Yahd) - -/// @note std::transform might have been tidier, but because of the ReturnCode -/// and the FAPI_TRY mechanism, this is the simplest. -/// -template< fapi2::TargetType T > -fapi2::ReturnCode scom_blastah( const fapi2::Target<T>& i_target, const std::vector<uint64_t>& i_addrs, - const fapi2::buffer<uint64_t>& i_data ) -{ - size_t count(0); - - for (auto a : i_addrs) - { - FAPI_TRY( mss::putScom(i_target, a, i_data) ); - ++count; - } - - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR( "scom_blastah failed: %d of %d executed against %s", count, i_addrs.size(), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief Blast one peice of data across a vector of targets -/// @param[in]i_targets the vector of targets for the scom -/// @param[in] i_addr the address -/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast -/// @return FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode scom_blastah( const std::vector<fapi2::Target<T> >& i_targets, const uint64_t i_addr, - const fapi2::buffer<uint64_t>& i_data ) -{ - size_t count(0); - - for (auto t : i_targets) - { - FAPI_TRY( mss::putScom(t, i_addr, i_data) ); - ++count; - } - - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR( "scom_blastah failed: %d of %d written to 0x%llx", count, i_targets.size(), i_addr); - return fapi2::current_err; -} - -/// -/// @brief Blast one peice of data across a vector of targets -/// @param[in]i_targets the vector of targets for the scom -/// @param[in] i_addrs the vector of addresses -/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast -/// @return FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode scom_blastah( const std::vector<fapi2::Target<T> >& i_targets, - const std::vector<uint64_t>& i_addrs, - const fapi2::buffer<uint64_t>& i_data ) -{ - size_t count(0); - - for (auto t : i_targets) - { - FAPI_TRY( mss::scom_blastah(t, i_addrs, i_data) ); - ++count; - } - - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR( "scom_blastah failed: %d of %dx%d", count, i_targets.size(), i_addrs.size() ); - return fapi2::current_err; -} - -/// /// @brief change resetn to the given state /// @param[in] i_target the mcbist /// @param[in] i_state the desired state @@ -892,6 +810,10 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target // Returned from set_rank_pairs, it tells us how many rank pairs we configured on this port. std::vector<uint64_t> l_pairs; + // Setup the DP16 IO TX, DLL/VREG. They use freq which is an MCBIST attribute + FAPI_TRY( mss::dp16<TARGET_TYPE_MCA>().setup_io_tx_config0(i_target) ); + FAPI_TRY( mss::dp16<TARGET_TYPE_MCA>().setup_dll_vreg_config1(i_target) ); + for( auto p : i_target.getChildren<TARGET_TYPE_MCA>()) { mss::dp16<TARGET_TYPE_MCA> l_dp16; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 78ca595b5..bf30d0e8a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -31,14 +31,15 @@ #include <utility> #include <vector> -#include "../utils/scom.H" -#include "dp16.H" - #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <mss_attribute_accessors.H> + +#include <phy/dp16.H> -#include "../utils/pos.H" -#include "../utils/c_str.H" +#include <utils/scom.H> +#include <utils/pos.H> +#include <utils/c_str.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCBIST; @@ -325,4 +326,78 @@ fapi_try_exit: } +/// +/// @brief Configure the DP16 io_tx config0 registers +/// @param[in] i_target a MCBIST target +/// @return FAPI2_RC_SUCCESS iff ok +/// +template<> +template<> +fapi2::ReturnCode dp16<TARGET_TYPE_MCA>::setup_io_tx_config0( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +{ + static const std::vector<uint64_t> l_addrs( + { + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0, + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1, + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2, + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3, + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4, + } ); + + fapi2::buffer<uint64_t> l_data; + uint64_t l_freq_bitfield; + + // Right now freq is per MCBIST. + uint64_t l_freq; + FAPI_TRY( mss::freq(i_target, l_freq) ); + + l_freq_bitfield = freq_bitfield_helper(l_freq); + + l_data.insertFromRight<MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW, + MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW_LEN>(l_freq_bitfield); + + FAPI_INF("blasting 0x%016lx to dp16 io_tx", l_data); + + FAPI_TRY( mss::scom_blastah(i_target.getChildren<TARGET_TYPE_MCA>(), l_addrs, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Configure ADR DLL/VREG Config 1 +/// @param[in] i_target a MCBIST target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template<> +template<> +fapi2::ReturnCode dp16<TARGET_TYPE_MCA>::setup_dll_vreg_config1( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +{ + static const std::vector<uint64_t> l_addrs( + { + MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0, + MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1, + } ); + + fapi2::buffer<uint64_t> l_data; + uint64_t l_freq_bitfield; + + // Right now freq is per MCBIST. + uint64_t l_freq; + FAPI_TRY( mss::freq(i_target, l_freq) ); + + l_freq_bitfield = freq_bitfield_helper(l_freq); + + l_data.insertFromRight<MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW, + MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_LEN>(l_freq_bitfield); + + FAPI_INF("blasting 0x%016lx to dp16 DLL/VREG config 1", l_data); + + FAPI_TRY( mss::scom_blastah(i_target.getChildren<TARGET_TYPE_MCA>(), l_addrs, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index 48ba78c6c..389dc51c8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -39,6 +39,37 @@ namespace mss { +/// +/// @brief Given a mt/s, create a PHY 'standard' bit field for that freq. +/// @param[in] i_freq the value from mss::freq for your target +/// @return uint64_t a right-aligned bitfield which can be inserted in to a buffer +/// +inline uint64_t freq_bitfield_helper( const uint64_t i_freq ) +{ + fapi2::buffer<uint64_t> l_data(0b1000); + + // Shift l_data over based on freq. + switch(i_freq) + { + // We don't support 1866 on Nimbus. + case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: + l_data >>= 3; + break; + + case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: + l_data >>= 2; + break; + + case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: + l_data >>= 1; + break; + + // 2666 is >> 0 + }; + + return l_data; +} + // I have a dream that the PHY code can be shared among controllers. So, I drive the // engine from a set of traits. This might be folly. Allow me to dream. BRS @@ -135,6 +166,21 @@ class dp16 /// inline fapi2::ReturnCode set_bad_bits(const fapi2::Target<T>& i_target); + /// + /// @brief Configure the DP16 io_tx config0 registers + /// @param[in] i_target a fapi2 target + /// @return FAPI2_RC_SUCCESs iff ok + /// + template< fapi2::TargetType K> + fapi2::ReturnCode setup_io_tx_config0( const fapi2::Target<K>& i_target ); + + /// + /// @brief Configure ADR DLL/VREG Config 1 + /// @param[in] i_target a fapi2 target + /// @return FAPI2_RC_SUCCESs iff ok + /// + template<fapi2::TargetType K> + fapi2::ReturnCode setup_dll_vreg_config1( const fapi2::Target<K>& i_target ); }; /// @@ -203,6 +249,25 @@ inline fapi2::ReturnCode dp16<fapi2::TARGET_TYPE_MCA>::set_bad_bits( return fapi2::FAPI2_RC_SUCCESS; } +/// +/// @brief Configure the DP16 io_tx config0 registers +/// @param[in] i_target a MCBIST target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template<> +template<> +fapi2::ReturnCode dp16<fapi2::TARGET_TYPE_MCA>::setup_io_tx_config0( + const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + +/// +/// @brief Configure ADR DLL/VREG Config 1 +/// @param[in] i_target a MCBIST target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template<> +template<> +fapi2::ReturnCode dp16<fapi2::TARGET_TYPE_MCA>::setup_dll_vreg_config1( + const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H index 43ee2d5d7..a63d20d95 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,6 +31,7 @@ #define _MSS_SCOM_H_ #include <fapi2.H> +#include <utils/c_str.H> // // Wrapping scom operations: We wrap fapi2::get/putScom for two reasons. The @@ -43,6 +44,7 @@ namespace mss { + /// @brief Reads a SCOM register from a chip. /// @tparam K template parameter, passed in target. /// @param[in] i_target HW target to operate on. @@ -106,5 +108,89 @@ inline fapi2::ReturnCode putScomUnderMask(const fapi2::Target<K>& i_target, #endif } +/// +/// @brief Blast one peice of data across a vector of addresses +/// @param[in] i_target the target for the scom +/// @param[in] i_addrs const std::vector<uint64_t>& addresses +/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast +/// @return FAPI2_RC_SUCCESS iff ok +/// @note Author is originally from Boston (Pahk mah cah in Havahd Yahd) + +/// @note std::transform might have been tidier, but because of the ReturnCode +/// and the FAPI_TRY mechanism, this is the simplest. +/// +template< fapi2::TargetType T > +fapi2::ReturnCode scom_blastah( const fapi2::Target<T>& i_target, const std::vector<uint64_t>& i_addrs, + const fapi2::buffer<uint64_t>& i_data ) +{ + size_t count(0); + + for (auto a : i_addrs) + { + FAPI_TRY( mss::putScom(i_target, a, i_data) ); + ++count; + } + + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR( "scom_blastah failed: %d of %d executed against %s", count, i_addrs.size(), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief Blast one peice of data across a vector of targets +/// @param[in]i_targets the vector of targets for the scom +/// @param[in] i_addr the address +/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast +/// @return FAPI2_RC_SUCCESS iff ok +/// +template< fapi2::TargetType T > +fapi2::ReturnCode scom_blastah( const std::vector<fapi2::Target<T> >& i_targets, const uint64_t i_addr, + const fapi2::buffer<uint64_t>& i_data ) +{ + size_t count(0); + + for (auto t : i_targets) + { + FAPI_TRY( mss::putScom(t, i_addr, i_data) ); + ++count; + } + + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR( "scom_blastah failed: %d of %d written to 0x%llx", count, i_targets.size(), i_addr); + return fapi2::current_err; +} + +/// +/// @brief Blast one peice of data across a vector of targets +/// @param[in]i_targets the vector of targets for the scom +/// @param[in] i_addrs the vector of addresses +/// @param[in] i_data const fapi2::buffer<uint64_t>& the data to blast +/// @return FAPI2_RC_SUCCESS iff ok +/// +template< fapi2::TargetType T > +fapi2::ReturnCode scom_blastah( const std::vector<fapi2::Target<T> >& i_targets, + const std::vector<uint64_t>& i_addrs, + const fapi2::buffer<uint64_t>& i_data ) +{ + size_t count(0); + + for (auto t : i_targets) + { + FAPI_TRY( mss::scom_blastah(t, i_addrs, i_data) ); + ++count; + } + + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR( "scom_blastah failed: %d of %dx%d", count, i_targets.size(), i_addrs.size() ); + return fapi2::current_err; +} + + } #endif |