path: root/include/APE_DEVICE2.h

////////////////////////////////////////////////////////////////////////////////
///
/// @file       APE_DEVICE2.h
///
/// @project    ape
///
/// @brief      APE_DEVICE2
///
////////////////////////////////////////////////////////////////////////////////
///
////////////////////////////////////////////////////////////////////////////////
///
/// @copyright Copyright (c) 2018, Evan Lojewski
/// @cond
///
/// All rights reserved.
///
/// Redistribution and use in source and binary forms, with or without
/// modification, are permitted provided that the following conditions are met:
/// 1. Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// 2. Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation
/// and/or other materials provided with the distribution.
/// 3. Neither the name of the <organization> nor the
/// names of its contributors may be used to endorse or promote products
/// derived from this software without specific prior written permission.
///
////////////////////////////////////////////////////////////////////////////////
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
/// @endcond
////////////////////////////////////////////////////////////////////////////////

/** @defgroup APE_DEVICE2_H    APE_DEVICE2 */
/** @addtogroup APE_DEVICE2_H
 * @{
 */
#ifndef APE_DEVICE2_H
#define APE_DEVICE2_H

#include <stdint.h>
#include "APE_DEVICE.h"

#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */
void init_APE_DEVICE2_sim(void* base);
void init_APE_DEVICE2(void);

#include <CXXRegister.h>
typedef CXXRegister<uint8_t,  0,  8> APE_DEVICE2_H_uint8_t;
typedef CXXRegister<uint16_t, 0, 16> APE_DEVICE2_H_uint16_t;
typedef CXXRegister<uint32_t, 0, 32> APE_DEVICE2_H_uint32_t;
#define APE_DEVICE2_H_uint8_t_bitfield(__pos__, __width__)  CXXRegister<uint8_t,  __pos__, __width__>
#define APE_DEVICE2_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__>
#define APE_DEVICE2_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__>
#define register_container struct
#define volatile
#define BITFIELD_BEGIN(__type__, __name__) struct {
#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__;
#define BITFIELD_END(__type__, __name__) } __name__;

#else /* Firmware Data types */
typedef uint8_t  APE_DEVICE2_H_uint8_t;
typedef uint16_t APE_DEVICE2_H_uint16_t;
typedef uint32_t APE_DEVICE2_H_uint32_t;
#define register_container union
#define BITFIELD_BEGIN(__type__, __name__) struct {
#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__;
#define BITFIELD_END(__type__, __name__) } __name__;
#endif /* !CXX_SIMULATOR */

#define REG_DEVICE2_BASE ((volatile void*)0xa0060000) /* Device Registers, function 2 */
#define REG_DEVICE2_SIZE (sizeof(DEVICE_t))

#define REG_DEVICE2_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0060068) /*  */
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK  0x1u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK  0x2u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK  0x4u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK  0x8u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK  0x10u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK  0x20u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK  0x40u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK  0x80u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK  0x100u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK  0x200u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK  0x400u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK  0x800u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__)  (((__reg__) & 0x800) >> 11u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__)  (((__val__) << 11u) & 0x800u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK  0x1000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__)  (((__reg__) & 0x1000) >> 12u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__)  (((__val__) << 12u) & 0x1000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK  0x2000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK  0x4000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK  0x8000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK  0xff0000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__)  (((__reg__) & 0xff0000) >> 16u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__)  (((__val__) << 16u) & 0xff0000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u

#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK  0xf000000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__)  (((__reg__) & 0xf000000) >> 24u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__)  (((__val__) << 24u) & 0xf000000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u

#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK  0xf0000000u
#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__)  (((__reg__) & 0xf0000000) >> 28u)
#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__)  (((__val__) << 28u) & 0xf0000000u)
#define     DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu


#define REG_DEVICE2_PCI_STATE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060070) /*  */
#define     DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u
#define     DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK  0x20u
#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u
#define     DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK  0x40u
#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_PCI_STATE_VPD_AVAILABLE_SHIFT 7u
#define     DEVICE2_PCI_STATE_VPD_AVAILABLE_MASK  0x80u
#define GET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_PCI_STATE_FLAT_VIEW_SHIFT 8u
#define     DEVICE2_PCI_STATE_FLAT_VIEW_MASK  0x100u
#define GET_DEVICE2_PCI_STATE_FLAT_VIEW(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_PCI_STATE_FLAT_VIEW(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u
#define     DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK  0xe00u
#define GET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__)  (((__reg__) & 0xe00) >> 9u)
#define SET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__)  (((__val__) << 9u) & 0xe00u)
#define     DEVICE2_PCI_STATE_CONFIG_RETRY_SHIFT 15u
#define     DEVICE2_PCI_STATE_CONFIG_RETRY_MASK  0x8000u
#define GET_DEVICE2_PCI_STATE_CONFIG_RETRY(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_PCI_STATE_CONFIG_RETRY(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u
#define     DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK  0x10000u
#define GET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__)  (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__)  (((__val__) << 16u) & 0x10000u)
#define     DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u
#define     DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK  0x20000u
#define GET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__)  (((__reg__) & 0x20000) >> 17u)
#define SET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__)  (((__val__) << 17u) & 0x20000u)
#define     DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u
#define     DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK  0x40000u
#define GET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__)  (((__reg__) & 0x40000) >> 18u)
#define SET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__)  (((__val__) << 18u) & 0x40000u)
#define     DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u
#define     DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_MASK  0x80000u
#define GET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__reg__)  (((__reg__) & 0x80000) >> 19u)
#define SET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__val__)  (((__val__) << 19u) & 0x80000u)

#define REG_DEVICE2_REGISTER_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */
#define REG_DEVICE2_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa006007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */
#define REG_DEVICE2_REGISTER_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa0060080) /* Register Data at the location pointed by the Register Base Register. */
#define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE2_H_uint32_t*)0xa0060088) /* UNDI Receive Return Ring Consumer Index Mailbox */
#define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006008c) /* UNDI Receive Return Ring Consumer Index Mailbox */
#define REG_DEVICE2_LINK_STATUS_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00600bc) /* PCIe standard register. */
#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u
#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK  0xf0000u
#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__)  (((__reg__) & 0xf0000) >> 16u)
#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__)  (((__val__) << 16u) & 0xf0000u)
#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u
#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u

#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u
#define     DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK  0x3f00000u
#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__)  (((__reg__) & 0x3f00000) >> 20u)
#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__)  (((__val__) << 20u) & 0x3f00000u)

#define REG_DEVICE2_APE_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa00600f8) /* APE Memory address to read/write using the APE Memory Data register.. */
#define REG_DEVICE2_APE_MEMORY_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa00600fc) /* APE Memory value at the location pointed by the Memory Base Register. */
#define REG_DEVICE2_EMAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060400) /*  */
#define     DEVICE2_EMAC_MODE_GLOBAL_RESET_SHIFT 0u
#define     DEVICE2_EMAC_MODE_GLOBAL_RESET_MASK  0x1u
#define GET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_EMAC_MODE_HALF_DUPLEX_SHIFT 1u
#define     DEVICE2_EMAC_MODE_HALF_DUPLEX_MASK  0x2u
#define GET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_EMAC_MODE_PORT_MODE_SHIFT 2u
#define     DEVICE2_EMAC_MODE_PORT_MODE_MASK  0xcu
#define GET_DEVICE2_EMAC_MODE_PORT_MODE(__reg__)  (((__reg__) & 0xc) >> 2u)
#define SET_DEVICE2_EMAC_MODE_PORT_MODE(__val__)  (((__val__) << 2u) & 0xcu)
#define     DEVICE2_EMAC_MODE_PORT_MODE_NONE 0x0u
#define     DEVICE2_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u
#define     DEVICE2_EMAC_MODE_PORT_MODE_1000 0x2u
#define     DEVICE2_EMAC_MODE_PORT_MODE_TBI 0x3u

#define     DEVICE2_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u
#define     DEVICE2_EMAC_MODE_LOOPBACK_MODE_MASK  0x10u
#define GET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u
#define     DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_MASK  0x80u
#define GET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u
#define     DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_MASK  0x100u
#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_EMAC_MODE_MAX_DEFER_SHIFT 9u
#define     DEVICE2_EMAC_MODE_MAX_DEFER_MASK  0x200u
#define GET_DEVICE2_EMAC_MODE_MAX_DEFER(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_EMAC_MODE_MAX_DEFER(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u
#define     DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_MASK  0x800u
#define GET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__)  (((__reg__) & 0x800) >> 11u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__val__)  (((__val__) << 11u) & 0x800u)
#define     DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u
#define     DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_MASK  0x1000u
#define GET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__)  (((__reg__) & 0x1000) >> 12u)
#define SET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__val__)  (((__val__) << 12u) & 0x1000u)
#define     DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u
#define     DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_MASK  0x2000u
#define GET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u
#define     DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_MASK  0x4000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u
#define     DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_MASK  0x8000u
#define GET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u
#define     DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_MASK  0x10000u
#define GET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__)  (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__val__)  (((__val__) << 16u) & 0x10000u)
#define     DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u
#define     DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_MASK  0x20000u
#define GET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__)  (((__reg__) & 0x20000) >> 17u)
#define SET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__val__)  (((__val__) << 17u) & 0x20000u)
#define     DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u
#define     DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK  0x40000u
#define GET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__)  (((__reg__) & 0x40000) >> 18u)
#define SET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__)  (((__val__) << 18u) & 0x40000u)
#define     DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u
#define     DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK  0x80000u
#define GET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__)  (((__reg__) & 0x80000) >> 19u)
#define SET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__)  (((__val__) << 19u) & 0x80000u)
#define     DEVICE2_EMAC_MODE_ENABLE_TCE_SHIFT 21u
#define     DEVICE2_EMAC_MODE_ENABLE_TCE_MASK  0x200000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_TCE(__reg__)  (((__reg__) & 0x200000) >> 21u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_TCE(__val__)  (((__val__) << 21u) & 0x200000u)
#define     DEVICE2_EMAC_MODE_ENABLE_RDE_SHIFT 22u
#define     DEVICE2_EMAC_MODE_ENABLE_RDE_MASK  0x400000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_RDE(__reg__)  (((__reg__) & 0x400000) >> 22u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_RDE(__val__)  (((__val__) << 22u) & 0x400000u)
#define     DEVICE2_EMAC_MODE_ENABLE_FHDE_SHIFT 23u
#define     DEVICE2_EMAC_MODE_ENABLE_FHDE_MASK  0x800000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__reg__)  (((__reg__) & 0x800000) >> 23u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__val__)  (((__val__) << 23u) & 0x800000u)
#define     DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u
#define     DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK  0x1000000u
#define GET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__)  (((__reg__) & 0x1000000) >> 24u)
#define SET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__)  (((__val__) << 24u) & 0x1000000u)
#define     DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u
#define     DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK  0x2000000u
#define GET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__)  (((__reg__) & 0x2000000) >> 25u)
#define SET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__)  (((__val__) << 25u) & 0x2000000u)
#define     DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u
#define     DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_MASK  0x4000000u
#define GET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__reg__)  (((__reg__) & 0x4000000) >> 26u)
#define SET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__val__)  (((__val__) << 26u) & 0x4000000u)
#define     DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u
#define     DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_MASK  0x8000000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__)  (((__reg__) & 0x8000000) >> 27u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__val__)  (((__val__) << 27u) & 0x8000000u)
#define     DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u
#define     DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_MASK  0x10000000u
#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__)  (((__reg__) & 0x10000000) >> 28u)
#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__val__)  (((__val__) << 28u) & 0x10000000u)
#define     DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u
#define     DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK  0x20000000u
#define GET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__)  (((__reg__) & 0x20000000) >> 29u)
#define SET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__)  (((__val__) << 29u) & 0x20000000u)

#define REG_DEVICE2_LED_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa006040c) /*  */
#define     DEVICE2_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u
#define     DEVICE2_LED_CONTROL_OVERRIDE_LINK_MASK  0x1u
#define GET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_LED_CONTROL_LED_1000_SHIFT 1u
#define     DEVICE2_LED_CONTROL_LED_1000_MASK  0x2u
#define GET_DEVICE2_LED_CONTROL_LED_1000(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_LED_CONTROL_LED_1000(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_LED_CONTROL_LED_100_SHIFT 2u
#define     DEVICE2_LED_CONTROL_LED_100_MASK  0x4u
#define GET_DEVICE2_LED_CONTROL_LED_100(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_LED_CONTROL_LED_100(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_LED_CONTROL_LED_10_SHIFT 3u
#define     DEVICE2_LED_CONTROL_LED_10_MASK  0x8u
#define GET_DEVICE2_LED_CONTROL_LED_10(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_LED_CONTROL_LED_10(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u
#define     DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_MASK  0x10u
#define GET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u
#define     DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_MASK  0x20u
#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_LED_CONTROL_LED_TRAFFIC_SHIFT 6u
#define     DEVICE2_LED_CONTROL_LED_TRAFFIC_MASK  0x40u
#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_LED_CONTROL_LED_STATUS_1000_SHIFT 7u
#define     DEVICE2_LED_CONTROL_LED_STATUS_1000_MASK  0x80u
#define GET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_LED_CONTROL_LED_STATUS_100_SHIFT 8u
#define     DEVICE2_LED_CONTROL_LED_STATUS_100_MASK  0x100u
#define GET_DEVICE2_LED_CONTROL_LED_STATUS_100(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_LED_CONTROL_LED_STATUS_100(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_LED_CONTROL_LED_STATUS_10_SHIFT 9u
#define     DEVICE2_LED_CONTROL_LED_STATUS_10_MASK  0x200u
#define GET_DEVICE2_LED_CONTROL_LED_STATUS_10(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_LED_CONTROL_LED_STATUS_10(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u
#define     DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_MASK  0x400u
#define GET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_LED_CONTROL_LED_MODE_SHIFT 11u
#define     DEVICE2_LED_CONTROL_LED_MODE_MASK  0x1800u
#define GET_DEVICE2_LED_CONTROL_LED_MODE(__reg__)  (((__reg__) & 0x1800) >> 11u)
#define SET_DEVICE2_LED_CONTROL_LED_MODE(__val__)  (((__val__) << 11u) & 0x1800u)
#define     DEVICE2_LED_CONTROL_LED_MODE_MAC 0x0u
#define     DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u
#define     DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u
#define     DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u

#define     DEVICE2_LED_CONTROL_MAC_MODE_SHIFT 13u
#define     DEVICE2_LED_CONTROL_MAC_MODE_MASK  0x2000u
#define GET_DEVICE2_LED_CONTROL_MAC_MODE(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_LED_CONTROL_MAC_MODE(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u
#define     DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK  0x4000u
#define GET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_LED_CONTROL_BLINK_PERIOD_SHIFT 19u
#define     DEVICE2_LED_CONTROL_BLINK_PERIOD_MASK  0x7ff80000u
#define GET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__reg__)  (((__reg__) & 0x7ff80000) >> 19u)
#define SET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__val__)  (((__val__) << 19u) & 0x7ff80000u)
#define     DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u
#define     DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK  0x80000000u
#define GET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
#define SET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__)  (((__val__) << 31u) & 0x80000000u)

#define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060410) /* Upper 2-bytes of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060414) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060418) /* Upper 2-bytes of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_1_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006041c) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_2_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060420) /* Upper 2-bytes of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_2_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060424) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_3_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060428) /* Upper 2-bytes of this node's MAC address. */
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006042c) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE2_WOL_PATTERN_POINTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0060430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */
#define REG_DEVICE2_WOL_PATTERN_CFG ((volatile APE_DEVICE2_H_uint32_t*)0xa0060434) /*  */
#define REG_DEVICE2_MTU_SIZE ((volatile APE_DEVICE2_H_uint32_t*)0xa006043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define     DEVICE2_MTU_SIZE_MTU_SHIFT 0u
#define     DEVICE2_MTU_SIZE_MTU_MASK  0xffffu
#define GET_DEVICE2_MTU_SIZE_MTU(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_MTU_SIZE_MTU(__val__)  (((__val__) << 0u) & 0xffffu)

#define REG_DEVICE2_MII_COMMUNICATION ((volatile APE_DEVICE2_H_uint32_t*)0xa006044c) /*  */
#define     DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u
#define     DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_MASK  0xffffu
#define GET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__val__)  (((__val__) << 0u) & 0xffffu)
#define     DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u
#define     DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_MASK  0x1f0000u
#define GET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__)  (((__reg__) & 0x1f0000) >> 16u)
#define SET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__val__)  (((__val__) << 16u) & 0x1f0000u)
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_MASK  0x3e00000u
#define GET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__reg__)  (((__reg__) & 0x3e00000) >> 21u)
#define SET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__val__)  (((__val__) << 21u) & 0x3e00000u)
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau
#define     DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu

#define     DEVICE2_MII_COMMUNICATION_COMMAND_SHIFT 26u
#define     DEVICE2_MII_COMMUNICATION_COMMAND_MASK  0xc000000u
#define GET_DEVICE2_MII_COMMUNICATION_COMMAND(__reg__)  (((__reg__) & 0xc000000) >> 26u)
#define SET_DEVICE2_MII_COMMUNICATION_COMMAND(__val__)  (((__val__) << 26u) & 0xc000000u)
#define     DEVICE2_MII_COMMUNICATION_COMMAND_WRITE 0x1u
#define     DEVICE2_MII_COMMUNICATION_COMMAND_READ 0x2u

#define     DEVICE2_MII_COMMUNICATION_READ_FAILED_SHIFT 28u
#define     DEVICE2_MII_COMMUNICATION_READ_FAILED_MASK  0x10000000u
#define GET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__reg__)  (((__reg__) & 0x10000000) >> 28u)
#define SET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__val__)  (((__val__) << 28u) & 0x10000000u)
#define     DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u
#define     DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_MASK  0x20000000u
#define GET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__reg__)  (((__reg__) & 0x20000000) >> 29u)
#define SET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__val__)  (((__val__) << 29u) & 0x20000000u)

#define REG_DEVICE2_MII_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060454) /*  */
#define     DEVICE2_MII_MODE_PHY_ADDRESS_SHIFT 5u
#define     DEVICE2_MII_MODE_PHY_ADDRESS_MASK  0x3e0u
#define GET_DEVICE2_MII_MODE_PHY_ADDRESS(__reg__)  (((__reg__) & 0x3e0) >> 5u)
#define SET_DEVICE2_MII_MODE_PHY_ADDRESS(__val__)  (((__val__) << 5u) & 0x3e0u)
#define     DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u
#define     DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK  0x8000u
#define GET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u
#define     DEVICE2_MII_MODE_MII_CLOCK_COUNT_MASK  0x1f0000u
#define GET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__reg__)  (((__reg__) & 0x1f0000) >> 16u)
#define SET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__val__)  (((__val__) << 16u) & 0x1f0000u)

#define REG_DEVICE2_TRANSMIT_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa006045c) /*  */
#define     DEVICE2_TRANSMIT_MAC_MODE_RESET_SHIFT 0u
#define     DEVICE2_TRANSMIT_MAC_MODE_RESET_MASK  0x1u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK  0x2u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK  0x10u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK  0x20u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK  0x40u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u
#define     DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK  0x80u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u
#define     DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK  0x100u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK  0x200u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u
#define     DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK  0x400u
#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__)  (((__val__) << 10u) & 0x400u)

#define REG_DEVICE2_RECEIVE_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060468) /*  */
#define     DEVICE2_RECEIVE_MAC_MODE_RESET_SHIFT 0u
#define     DEVICE2_RECEIVE_MAC_MODE_RESET_MASK  0x1u
#define GET_DEVICE2_RECEIVE_MAC_MODE_RESET(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_RECEIVE_MAC_MODE_RESET(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u
#define     DEVICE2_RECEIVE_MAC_MODE_ENABLE_MASK  0x2u
#define GET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u
#define     DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK  0x100u
#define GET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u
#define     DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK  0x2000000u
#define GET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__)  (((__reg__) & 0x2000000) >> 25u)
#define SET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__)  (((__val__) << 25u) & 0x2000000u)

#define REG_DEVICE2_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060540) /*  */
#define     DEVICE2_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH1_HIGH_HIGH_MASK  0xffffu
#define GET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__val__)  (((__val__) << 0u) & 0xffffu)

#define REG_DEVICE2_PERFECT_MATCH1_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060544) /*  */
#define     DEVICE2_PERFECT_MATCH1_LOW_LOW_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH1_LOW_LOW_MASK  0xffffffffu
#define GET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__val__)  (((__val__) << 0u) & 0xffffffffu)

#define REG_DEVICE2_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060548) /*  */
#define     DEVICE2_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH2_HIGH_HIGH_MASK  0xffffu
#define GET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__val__)  (((__val__) << 0u) & 0xffffu)

#define REG_DEVICE2_PERFECT_MATCH2_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006054c) /*  */
#define     DEVICE2_PERFECT_MATCH2_LOW_LOW_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH2_LOW_LOW_MASK  0xffffffffu
#define GET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__val__)  (((__val__) << 0u) & 0xffffffffu)

#define REG_DEVICE2_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060550) /*  */
#define     DEVICE2_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH3_HIGH_HIGH_MASK  0xffffu
#define GET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__val__)  (((__val__) << 0u) & 0xffffu)

#define REG_DEVICE2_PERFECT_MATCH3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060554) /*  */
#define     DEVICE2_PERFECT_MATCH3_LOW_LOW_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH3_LOW_LOW_MASK  0xffffffffu
#define GET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__val__)  (((__val__) << 0u) & 0xffffffffu)

#define REG_DEVICE2_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060558) /*  */
#define     DEVICE2_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH4_HIGH_HIGH_MASK  0xffffu
#define GET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__val__)  (((__val__) << 0u) & 0xffffu)

#define REG_DEVICE2_PERFECT_MATCH4_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006055c) /*  */
#define     DEVICE2_PERFECT_MATCH4_LOW_LOW_SHIFT 0u
#define     DEVICE2_PERFECT_MATCH4_LOW_LOW_MASK  0xffffffffu
#define GET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
#define SET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__val__)  (((__val__) << 0u) & 0xffffffffu)

#define REG_DEVICE2_SGMII_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa00605b4) /* This register reflects various status of the respective SGMII port when enabled. */
#define     DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u
#define     DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK  0x1u
#define GET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_SGMII_STATUS_LINK_STATUS_SHIFT 1u
#define     DEVICE2_SGMII_STATUS_LINK_STATUS_MASK  0x2u
#define GET_DEVICE2_SGMII_STATUS_LINK_STATUS(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_SGMII_STATUS_LINK_STATUS(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u
#define     DEVICE2_SGMII_STATUS_DUPLEX_STATUS_MASK  0x4u
#define GET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_SGMII_STATUS_SPEED_1000_SHIFT 3u
#define     DEVICE2_SGMII_STATUS_SPEED_1000_MASK  0x8u
#define GET_DEVICE2_SGMII_STATUS_SPEED_1000(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_SGMII_STATUS_SPEED_1000(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_SGMII_STATUS_SPEED_100_SHIFT 4u
#define     DEVICE2_SGMII_STATUS_SPEED_100_MASK  0x10u
#define GET_DEVICE2_SGMII_STATUS_SPEED_100(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_SGMII_STATUS_SPEED_100(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u
#define     DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_MASK  0x20u
#define GET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_SGMII_STATUS_PAUSE_RX_SHIFT 6u
#define     DEVICE2_SGMII_STATUS_PAUSE_RX_MASK  0x40u
#define GET_DEVICE2_SGMII_STATUS_PAUSE_RX(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_SGMII_STATUS_PAUSE_RX(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_SGMII_STATUS_PAUSE_TX_SHIFT 7u
#define     DEVICE2_SGMII_STATUS_PAUSE_TX_MASK  0x80u
#define GET_DEVICE2_SGMII_STATUS_PAUSE_TX(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_SGMII_STATUS_PAUSE_TX(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u
#define     DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK  0x100u
#define GET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u
#define     DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u

#define     DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u
#define     DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_MASK  0x200u
#define GET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u
#define     DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK  0x400u
#define GET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u
#define     DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK  0xffff0000u
#define GET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__)  (((__reg__) & 0xffff0000) >> 16u)
#define SET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__)  (((__val__) << 16u) & 0xffff0000u)

#define REG_DEVICE2_CPMU_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0063600) /*  */
#define     DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u
#define     DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK  0x1u
#define GET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u
#define     DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK  0x2u
#define GET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_CPMU_CONTROL_POWER_DOWN_SHIFT 2u
#define     DEVICE2_CPMU_CONTROL_POWER_DOWN_MASK  0x4u
#define GET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u
#define     DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK  0x10u
#define GET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u
#define     DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK  0x20u
#define GET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u
#define     DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK  0x200u
#define GET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u
#define     DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK  0x400u
#define GET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u
#define     DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK  0x4000u
#define GET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u
#define     DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK  0x10000u
#define GET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__)  (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__)  (((__val__) << 16u) & 0x10000u)
#define     DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u
#define     DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK  0x40000u
#define GET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__)  (((__reg__) & 0x40000) >> 18u)
#define SET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__)  (((__val__) << 18u) & 0x40000u)
#define     DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u
#define     DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK  0x80000u
#define GET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__)  (((__reg__) & 0x80000) >> 19u)
#define SET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__)  (((__val__) << 19u) & 0x80000u)
#define     DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u
#define     DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK  0x10000000u
#define GET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__)  (((__reg__) & 0x10000000) >> 28u)
#define SET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__)  (((__val__) << 28u) & 0x10000000u)

#define REG_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063610) /*  */
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK  0x1f0000u
#define GET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__)  (((__reg__) & 0x1f0000) >> 16u)
#define SET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__)  (((__val__) << 16u) & 0x1f0000u)
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u
#define     DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu


#define REG_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063624) /*  */
#define     DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
#define     DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK  0x1f0000u
#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__)  (((__reg__) & 0x1f0000) >> 16u)
#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__)  (((__val__) << 16u) & 0x1f0000u)
#define     DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u
#define     DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK  0x80000000u
#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__)  (((__reg__) & 0x80000000) >> 31u)
#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__)  (((__val__) << 31u) & 0x80000000u)

#define REG_DEVICE2_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa006362c) /*  */
#define     DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u
#define     DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK  0xfu
#define GET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__)  (((__reg__) & 0xf) >> 0u)
#define SET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__)  (((__val__) << 0u) & 0xfu)
#define     DEVICE2_STATUS_CPMU_POWER_STATE_SHIFT 4u
#define     DEVICE2_STATUS_CPMU_POWER_STATE_MASK  0x70u
#define GET_DEVICE2_STATUS_CPMU_POWER_STATE(__reg__)  (((__reg__) & 0x70) >> 4u)
#define SET_DEVICE2_STATUS_CPMU_POWER_STATE(__val__)  (((__val__) << 4u) & 0x70u)
#define     DEVICE2_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u
#define     DEVICE2_STATUS_ENERGY_DETECT_STATUS_MASK  0x80u
#define GET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_STATUS_POWER_STATE_SHIFT 8u
#define     DEVICE2_STATUS_POWER_STATE_MASK  0x300u
#define GET_DEVICE2_STATUS_POWER_STATE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_STATUS_POWER_STATE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_STATUS_VMAIN_POWER_STATUS_SHIFT 13u
#define     DEVICE2_STATUS_VMAIN_POWER_STATUS_MASK  0x2000u
#define GET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u
#define     DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK  0x4000u
#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u
#define     DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK  0x8000u
#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u
#define     DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_MASK  0x10000u
#define GET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__reg__)  (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__val__)  (((__val__) << 16u) & 0x10000u)
#define     DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u
#define     DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_MASK  0x20000u
#define GET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__reg__)  (((__reg__) & 0x20000) >> 17u)
#define SET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__val__)  (((__val__) << 17u) & 0x20000u)
#define     DEVICE2_STATUS_LINK_IDLE_STATUS_SHIFT 18u
#define     DEVICE2_STATUS_LINK_IDLE_STATUS_MASK  0x40000u
#define GET_DEVICE2_STATUS_LINK_IDLE_STATUS(__reg__)  (((__reg__) & 0x40000) >> 18u)
#define SET_DEVICE2_STATUS_LINK_IDLE_STATUS(__val__)  (((__val__) << 18u) & 0x40000u)
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_MASK  0x180000u
#define GET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__reg__)  (((__reg__) & 0x180000) >> 19u)
#define SET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__val__)  (((__val__) << 19u) & 0x180000u)
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u
#define     DEVICE2_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u

#define     DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u
#define     DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK  0x200000u
#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__)  (((__reg__) & 0x200000) >> 21u)
#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__)  (((__val__) << 21u) & 0x200000u)
#define     DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u
#define     DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK  0x400000u
#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__)  (((__reg__) & 0x400000) >> 22u)
#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__)  (((__val__) << 22u) & 0x400000u)
#define     DEVICE2_STATUS_APE_STATUS_SHIFT 23u
#define     DEVICE2_STATUS_APE_STATUS_MASK  0x1800000u
#define GET_DEVICE2_STATUS_APE_STATUS(__reg__)  (((__reg__) & 0x1800000) >> 23u)
#define SET_DEVICE2_STATUS_APE_STATUS(__val__)  (((__val__) << 23u) & 0x1800000u)
#define     DEVICE2_STATUS_APE_STATUS_ACTIVE 0x0u
#define     DEVICE2_STATUS_APE_STATUS_SLEEP 0x1u
#define     DEVICE2_STATUS_APE_STATUS_DEEP_SLEEP 0x2u

#define     DEVICE2_STATUS_FUNCTION_ENABLE_SHIFT 25u
#define     DEVICE2_STATUS_FUNCTION_ENABLE_MASK  0x3e000000u
#define GET_DEVICE2_STATUS_FUNCTION_ENABLE(__reg__)  (((__reg__) & 0x3e000000) >> 25u)
#define SET_DEVICE2_STATUS_FUNCTION_ENABLE(__val__)  (((__val__) << 25u) & 0x3e000000u)
#define     DEVICE2_STATUS_FUNCTION_NUMBER_SHIFT 30u
#define     DEVICE2_STATUS_FUNCTION_NUMBER_MASK  0xc0000000u
#define GET_DEVICE2_STATUS_FUNCTION_NUMBER(__reg__)  (((__reg__) & 0xc0000000) >> 30u)
#define SET_DEVICE2_STATUS_FUNCTION_NUMBER(__val__)  (((__val__) << 30u) & 0xc0000000u)

#define REG_DEVICE2_CLOCK_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063630) /*  */
#define REG_DEVICE2_GPHY_CONTROL_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063638) /*  */
#define     DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u
#define     DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK  0x1u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u
#define     DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK  0x2u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u
#define     DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK  0x4u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u
#define     DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK  0x8u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u
#define     DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_MASK  0x10u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u
#define     DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK  0x8000u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u
#define     DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK  0x2000000u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__)  (((__reg__) & 0x2000000) >> 25u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__)  (((__val__) << 25u) & 0x2000000u)
#define     DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u
#define     DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK  0x4000000u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__)  (((__reg__) & 0x4000000) >> 26u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__)  (((__val__) << 26u) & 0x4000000u)
#define     DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u
#define     DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK  0x8000000u
#define GET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__)  (((__reg__) & 0x8000000) >> 27u)
#define SET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__)  (((__val__) << 27u) & 0x8000000u)

#define REG_DEVICE2_CHIP_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0063658) /*  */
#define REG_DEVICE2_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
#define REG_DEVICE2_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa0063660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
#define REG_DEVICE2_GPHY_STRAP ((volatile APE_DEVICE2_H_uint32_t*)0xa0063664) /*  */
#define     DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u
#define     DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK  0x4u
#define GET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u
#define     DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK  0x8u
#define GET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u
#define     DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK  0x10u
#define GET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__)  (((__val__) << 4u) & 0x10u)

#define REG_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa006367c) /*  */
#define     DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u
#define     DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK  0x10u
#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u
#define     DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK  0x20u
#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__)  (((__val__) << 5u) & 0x20u)

#define REG_DEVICE2_EEE_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa00636b0) /*  */
#define     DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u
#define     DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_MASK  0x1u
#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u
#define     DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_MASK  0x2u
#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u
#define     DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK  0x4u
#define GET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u
#define     DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK  0x8u
#define GET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u
#define     DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK  0x10u
#define GET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u
#define     DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK  0x20u
#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u
#define     DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK  0x40u
#define GET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u
#define     DEVICE2_EEE_MODE_USER_LPI_ENABLE_MASK  0x80u
#define GET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u
#define     DEVICE2_EEE_MODE_TX_LPI_ENABLE_MASK  0x100u
#define GET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u
#define     DEVICE2_EEE_MODE_RX_LPI_ENABLE_MASK  0x200u
#define GET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u
#define     DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_MASK  0x400u
#define GET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_EEE_MODE_BLOCK_TIME_SHIFT 11u
#define     DEVICE2_EEE_MODE_BLOCK_TIME_MASK  0x7f800u
#define GET_DEVICE2_EEE_MODE_BLOCK_TIME(__reg__)  (((__reg__) & 0x7f800) >> 11u)
#define SET_DEVICE2_EEE_MODE_BLOCK_TIME(__val__)  (((__val__) << 11u) & 0x7f800u)
#define     DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u
#define     DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK  0x80000u
#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__)  (((__reg__) & 0x80000) >> 19u)
#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__)  (((__val__) << 19u) & 0x80000u)

#define REG_DEVICE2_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636bc) /*  */
#define     DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u
#define     DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK  0x4u
#define GET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__)  (((__val__) << 2u) & 0x4u)

#define REG_DEVICE2_EEE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636d0) /*  */
#define     DEVICE2_EEE_CONTROL_EXIT_TIME_SHIFT 0u
#define     DEVICE2_EEE_CONTROL_EXIT_TIME_MASK  0xffffu
#define GET_DEVICE2_EEE_CONTROL_EXIT_TIME(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_EEE_CONTROL_EXIT_TIME(__val__)  (((__val__) << 0u) & 0xffffu)
#define     DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u
#define     DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_MASK  0xffff0000u
#define GET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__reg__)  (((__reg__) & 0xffff0000) >> 16u)
#define SET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__val__)  (((__val__) << 16u) & 0xffff0000u)

#define REG_DEVICE2_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f0) /*  */
#define REG_DEVICE2_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f4) /*  */
#define REG_DEVICE2_MEMORY_ARBITER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064000) /*  */
#define     DEVICE2_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u
#define     DEVICE2_MEMORY_ARBITER_MODE_ENABLE_MASK  0x2u
#define GET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__val__)  (((__val__) << 1u) & 0x2u)

#define REG_DEVICE2_BUFFER_MANAGER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064400) /*  */
#define     DEVICE2_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u
#define     DEVICE2_BUFFER_MANAGER_MODE_ENABLE_MASK  0x2u
#define GET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u
#define     DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK  0x4u
#define GET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u
#define     DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK  0x20u
#define GET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__)  (((__val__) << 5u) & 0x20u)

#define REG_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0064910) /*  */
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK  0x30000u
#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__)  (((__reg__) & 0x30000) >> 16u)
#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__)  (((__val__) << 16u) & 0x30000u)
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u

#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK  0xc0000u
#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__)  (((__reg__) & 0xc0000) >> 18u)
#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__)  (((__val__) << 18u) & 0xc0000u)
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u
#define     DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u


#define REG_DEVICE2_RX_RISC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0065000) /*  */
#define     DEVICE2_RX_RISC_MODE_RESET_SHIFT 0u
#define     DEVICE2_RX_RISC_MODE_RESET_MASK  0x1u
#define GET_DEVICE2_RX_RISC_MODE_RESET(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_RX_RISC_MODE_RESET(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u
#define     DEVICE2_RX_RISC_MODE_SINGLE_STEP_MASK  0x2u
#define GET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u
#define     DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK  0x4u
#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u
#define     DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK  0x8u
#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u
#define     DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK  0x20u
#define GET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_RX_RISC_MODE_ROM_FAIL_SHIFT 6u
#define     DEVICE2_RX_RISC_MODE_ROM_FAIL_MASK  0x40u
#define GET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u
#define     DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_MASK  0x80u
#define GET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u
#define     DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK  0x100u
#define GET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u
#define     DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK  0x200u
#define GET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_RX_RISC_MODE_HALT_SHIFT 10u
#define     DEVICE2_RX_RISC_MODE_HALT_MASK  0x400u
#define GET_DEVICE2_RX_RISC_MODE_HALT(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_RX_RISC_MODE_HALT(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u
#define     DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK  0x800u
#define GET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__)  (((__reg__) & 0x800) >> 11u)
#define SET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__)  (((__val__) << 11u) & 0x800u)
#define     DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u
#define     DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK  0x1000u
#define GET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__)  (((__reg__) & 0x1000) >> 12u)
#define SET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__)  (((__val__) << 12u) & 0x1000u)
#define     DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u
#define     DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK  0x2000u
#define GET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u
#define     DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK  0x4000u
#define GET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__)  (((__val__) << 14u) & 0x4000u)

#define REG_DEVICE2_RX_RISC_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0065004) /*  */
#define     DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u
#define     DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK  0x1u
#define GET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__)  (((__reg__) & 0x1) >> 0u)
#define SET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__)  (((__val__) << 0u) & 0x1u)
#define     DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u
#define     DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK  0x2u
#define GET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u
#define     DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK  0x4u
#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__)  (((__reg__) & 0x4) >> 2u)
#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__)  (((__val__) << 2u) & 0x4u)
#define     DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u
#define     DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK  0x8u
#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__)  (((__reg__) & 0x8) >> 3u)
#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__)  (((__val__) << 3u) & 0x8u)
#define     DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u
#define     DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK  0x10u
#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__)  (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__)  (((__val__) << 4u) & 0x10u)
#define     DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u
#define     DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK  0x20u
#define GET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__)  (((__reg__) & 0x20) >> 5u)
#define SET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__)  (((__val__) << 5u) & 0x20u)
#define     DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u
#define     DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK  0x40u
#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__)  (((__reg__) & 0x40) >> 6u)
#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__)  (((__val__) << 6u) & 0x40u)
#define     DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u
#define     DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK  0x80u
#define GET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__)  (((__reg__) & 0x80) >> 7u)
#define SET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__)  (((__val__) << 7u) & 0x80u)
#define     DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u
#define     DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK  0x100u
#define GET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u
#define     DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK  0x200u
#define GET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_RX_RISC_STATUS_HALTED_SHIFT 10u
#define     DEVICE2_RX_RISC_STATUS_HALTED_MASK  0x400u
#define GET_DEVICE2_RX_RISC_STATUS_HALTED(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_RX_RISC_STATUS_HALTED(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_RX_RISC_STATUS_UNKNOWN_SHIFT 11u
#define     DEVICE2_RX_RISC_STATUS_UNKNOWN_MASK  0x800u
#define GET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__reg__)  (((__reg__) & 0x800) >> 11u)
#define SET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__val__)  (((__val__) << 11u) & 0x800u)
#define     DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u
#define     DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK  0x4000u
#define GET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u
#define     DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK  0x8000u
#define GET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u
#define     DEVICE2_RX_RISC_STATUS_BLOCKING_READ_MASK  0x80000000u
#define GET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__reg__)  (((__reg__) & 0x80000000) >> 31u)
#define SET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__val__)  (((__val__) << 31u) & 0x80000000u)

#define REG_DEVICE2_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa006501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */
#define REG_DEVICE2_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE2_H_uint32_t*)0xa0065020) /* This undocumented register contains the current word located at the program counter address loaded in  */
#define REG_DEVICE2_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE2_H_uint32_t*)0xa0065034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */
#define REG_DEVICE2_RX_RISC_REGISTER_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065200) /* $zero (R0) */
#define REG_DEVICE2_RX_RISC_REGISTER_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065204) /* $at (R1) */
#define REG_DEVICE2_RX_RISC_REGISTER_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065208) /* $v0 (R2) */
#define REG_DEVICE2_RX_RISC_REGISTER_3 ((volatile APE_DEVICE2_H_uint32_t*)0xa006520c) /* $v1 (R3) */
#define REG_DEVICE2_RX_RISC_REGISTER_4 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065210) /* $a0 (R4) */
#define REG_DEVICE2_RX_RISC_REGISTER_5 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065214) /* $a1 (R5) */
#define REG_DEVICE2_RX_RISC_REGISTER_6 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065218) /* $a2 (R6) */
#define REG_DEVICE2_RX_RISC_REGISTER_7 ((volatile APE_DEVICE2_H_uint32_t*)0xa006521c) /* $a3 (R7) */
#define REG_DEVICE2_RX_RISC_REGISTER_8 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065220) /* $t0 (R8) */
#define REG_DEVICE2_RX_RISC_REGISTER_9 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065224) /* $t1 (R9) */
#define REG_DEVICE2_RX_RISC_REGISTER_10 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065228) /* $t2 (R10) */
#define REG_DEVICE2_RX_RISC_REGISTER_11 ((volatile APE_DEVICE2_H_uint32_t*)0xa006522c) /* $t3 (R11) */
#define REG_DEVICE2_RX_RISC_REGISTER_12 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065230) /* $t4 (R12) */
#define REG_DEVICE2_RX_RISC_REGISTER_13 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065234) /* $t5 (R13) */
#define REG_DEVICE2_RX_RISC_REGISTER_14 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065238) /* $t6 (R14) */
#define REG_DEVICE2_RX_RISC_REGISTER_15 ((volatile APE_DEVICE2_H_uint32_t*)0xa006523c) /* $t7 (R15) */
#define REG_DEVICE2_RX_RISC_REGISTER_16 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065240) /* $s0 (R16) */
#define REG_DEVICE2_RX_RISC_REGISTER_17 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065244) /* $s1 (R17) */
#define REG_DEVICE2_RX_RISC_REGISTER_18 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065248) /* $s2 (R18) */
#define REG_DEVICE2_RX_RISC_REGISTER_19 ((volatile APE_DEVICE2_H_uint32_t*)0xa006524c) /* $s3 (R19) */
#define REG_DEVICE2_RX_RISC_REGISTER_20 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065250) /* $s4 (R20) */
#define REG_DEVICE2_RX_RISC_REGISTER_21 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065254) /* $s5 (R21) */
#define REG_DEVICE2_RX_RISC_REGISTER_22 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065258) /* $s6 (R22) */
#define REG_DEVICE2_RX_RISC_REGISTER_23 ((volatile APE_DEVICE2_H_uint32_t*)0xa006525c) /* $s7 (R23) */
#define REG_DEVICE2_RX_RISC_REGISTER_24 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065260) /* $t8 (R24) */
#define REG_DEVICE2_RX_RISC_REGISTER_25 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065264) /* $t9 (R25) */
#define REG_DEVICE2_RX_RISC_REGISTER_26 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065268) /* $k0 (R26) */
#define REG_DEVICE2_RX_RISC_REGISTER_27 ((volatile APE_DEVICE2_H_uint32_t*)0xa006526c) /* $k1 (R27) */
#define REG_DEVICE2_RX_RISC_REGISTER_28 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065270) /* $gp (R28) */
#define REG_DEVICE2_RX_RISC_REGISTER_29 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065274) /* $sp (R29) */
#define REG_DEVICE2_RX_RISC_REGISTER_30 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065278) /* $fp (R30) */
#define REG_DEVICE2_RX_RISC_REGISTER_31 ((volatile APE_DEVICE2_H_uint32_t*)0xa006527c) /* $ra (R31) */
#define REG_DEVICE2_6408 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066408) /*  */
#define REG_DEVICE2_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */
#define REG_DEVICE2_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */
#define REG_DEVICE2_PCI_VPD_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */
#define     DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u
#define     DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK  0x7fff0000u
#define GET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__)  (((__reg__) & 0x7fff0000) >> 16u)
#define SET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__)  (((__val__) << 16u) & 0x7fff0000u)

#define REG_DEVICE2_PCI_VPD_RESPONSE ((volatile APE_DEVICE2_H_uint32_t*)0xa0066430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by  */
#define REG_DEVICE2_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */
#define     DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u
#define     DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK  0xffffu
#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__)  (((__val__) << 0u) & 0xffffu)
#define     DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u
#define     DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK  0xffff0000u
#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__)  (((__reg__) & 0xffff0000) >> 16u)
#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__)  (((__val__) << 16u) & 0xffff0000u)

#define REG_DEVICE2_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */
#define     DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u
#define     DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK  0xffffu
#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__)  (((__reg__) & 0xffff) >> 0u)
#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__)  (((__val__) << 0u) & 0xffffu)
#define     DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u
#define     DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK  0xffff0000u
#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__)  (((__reg__) & 0xffff0000) >> 16u)
#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__)  (((__val__) << 16u) & 0xffff0000u)

#define REG_DEVICE2_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE2_H_uint32_t*)0xa006643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */
#define REG_DEVICE2_64C0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c0) /*  */
#define REG_DEVICE2_64C8 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c8) /*  */
#define REG_DEVICE2_64DC ((volatile APE_DEVICE2_H_uint32_t*)0xa00664dc) /*  */
#define REG_DEVICE2_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0066504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */
#define REG_DEVICE2_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0066508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */
#define REG_DEVICE2_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified.  */
#define     DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066514) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066518) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE2_H_uint32_t*)0xa006651c) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066520) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066524) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066528) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE2_H_uint32_t*)0xa006652c) /* See  */
#define     DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u
#define     DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_MASK  0xffu
#define GET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__reg__)  (((__reg__) & 0xff) >> 0u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__val__)  (((__val__) << 0u) & 0xffu)
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_MASK  0x300u
#define GET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__)  (((__reg__) & 0x300) >> 8u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__val__)  (((__val__) << 8u) & 0x300u)
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK  0x1c00u
#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__)  (((__reg__) & 0x1c00) >> 10u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__)  (((__val__) << 10u) & 0x1c00u)
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_MASK  0x6000u
#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__reg__)  (((__reg__) & 0x6000) >> 13u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__val__)  (((__val__) << 13u) & 0x6000u)
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u

#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_MASK  0x38000u
#define GET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__reg__)  (((__reg__) & 0x38000) >> 15u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__val__)  (((__val__) << 15u) & 0x38000u)
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u
#define     DEVICE2_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u

#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u
#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_MASK  0x1c0000u
#define GET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u
#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u
#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u
#define     DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u


#define REG_DEVICE2_6530 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066530) /*  */
#define REG_DEVICE2_6550 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */
#define REG_DEVICE2_65F4 ((volatile APE_DEVICE2_H_uint32_t*)0xa00665f4) /*  */
#define REG_DEVICE2_GRC_MODE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066800) /*  */
#define     DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u
#define     DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK  0x80000u
#define GET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__)  (((__reg__) & 0x80000) >> 19u)
#define SET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__)  (((__val__) << 19u) & 0x80000u)
#define     DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u
#define     DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK  0x200000u
#define GET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__)  (((__reg__) & 0x200000) >> 21u)
#define SET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__)  (((__val__) << 21u) & 0x200000u)
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK  0x400000u
#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__)  (((__reg__) & 0x400000) >> 22u)
#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__)  (((__val__) << 22u) & 0x400000u)
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK  0x20000000u
#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__)  (((__reg__) & 0x20000000) >> 29u)
#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__)  (((__val__) << 29u) & 0x20000000u)
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u
#define     DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK  0x80000000u
#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__)  (((__reg__) & 0x80000000) >> 31u)
#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__)  (((__val__) << 31u) & 0x80000000u)

#define REG_DEVICE2_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE2_H_uint32_t*)0xa0066804) /*  */
#define     DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u
#define     DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_MASK  0x2u
#define GET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__)  (((__reg__) & 0x2) >> 1u)
#define SET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__val__)  (((__val__) << 1u) & 0x2u)
#define     DEVICE2_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u
#define     DEVICE2_MISCELLANEOUS_CONFIG_ALL_MASK  0xfffffffeu
#define GET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__reg__)  (((__reg__) & 0xfffffffe) >> 1u)
#define SET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__val__)  (((__val__) << 1u) & 0xfffffffeu)

#define REG_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066808) /*  */
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK  0x100u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__)  (((__reg__) & 0x100) >> 8u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__)  (((__val__) << 8u) & 0x100u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK  0x200u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__)  (((__reg__) & 0x200) >> 9u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__)  (((__val__) << 9u) & 0x200u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK  0x400u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__)  (((__reg__) & 0x400) >> 10u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__)  (((__val__) << 10u) & 0x400u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK  0x800u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__)  (((__reg__) & 0x800) >> 11u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__)  (((__val__) << 11u) & 0x800u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK  0x1000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__)  (((__reg__) & 0x1000) >> 12u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__)  (((__val__) << 12u) & 0x1000u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK  0x2000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__)  (((__reg__) & 0x2000) >> 13u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__)  (((__val__) << 13u) & 0x2000u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK  0x4000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__)  (((__reg__) & 0x4000) >> 14u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__)  (((__val__) << 14u) & 0x4000u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK  0x8000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__)  (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__)  (((__val__) << 15u) & 0x8000u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK  0x10000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__)  (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__)  (((__val__) << 16u) & 0x10000u)
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u
#define     DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK  0x1000000u
#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__)  (((__reg__) & 0x1000000) >> 24u)
#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__)  (((__val__) << 24u) & 0x1000000u)

#define REG_DEVICE2_TIMER ((volatile APE_DEVICE2_H_uint32_t*)0xa006680c) /* 32-bit free-running counter */
#define REG_DEVICE2_RX_CPU_EVENT ((volatile APE_DEVICE2_H_uint32_t*)0xa0066810) /*  */
#define     DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u
#define     DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_MASK  0x2000000u
#define GET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__reg__)  (((__reg__) & 0x2000000) >> 25u)
#define SET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__val__)  (((__val__) << 25u) & 0x2000000u)
#define     DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u
#define     DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK  0x4000000u
#define GET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__)  (((__reg__) & 0x4000000) >> 26u)
#define SET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__)  (((__val__) << 26u) & 0x4000000u)
#define     DEVICE2_RX_CPU_EVENT_TIMER_SHIFT 29u
#define     DEVICE2_RX_CPU_EVENT_TIMER_MASK  0x20000000u
#define GET_DEVICE2_RX_CPU_EVENT_TIMER(__reg__)  (((__reg__) & 0x20000000) >> 29u)
#define SET_DEVICE2_RX_CPU_EVENT_TIMER(__val__)  (((__val__) << 29u) & 0x20000000u)
#define     DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u
#define     DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_MASK  0x40000000u
#define GET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__reg__)  (((__reg__) & 0x40000000) >> 30u)
#define SET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__val__)  (((__val__) << 30u) & 0x40000000u)

#define REG_DEVICE2_6838 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066838) /* Unknown. Used by PXE agent. */
#define REG_DEVICE2_MDI_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */
#define REG_DEVICE2_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE2_H_uint32_t*)0xa006684c) /*  */
#define     DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u
#define     DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK  0x40000000u
#define GET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__)  (((__reg__) & 0x40000000) >> 30u)
#define SET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__)  (((__val__) << 30u) & 0x40000000u)

#define REG_DEVICE2_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0066894) /*  */
#define     DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u
#define     DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK  0x7fffffffu
#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__)  (((__reg__) & 0x7fffffff) >> 0u)
#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__)  (((__val__) << 0u) & 0x7fffffffu)
#define     DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u
#define     DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK  0x80000000u
#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__)  (((__val__) << 31u) & 0x80000000u)

#define REG_DEVICE2_EXPANSION_ROM_ADDR ((volatile APE_DEVICE2_H_uint32_t*)0xa00668ec) /* Expansion ROM base address, expect to be d- word aligned. */
#define REG_DEVICE2_68F0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00668f0) /*  */
#define REG_DEVICE2_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066908) /*  */
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK  0x30000u
#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__)  (((__reg__) & 0x30000) >> 16u)
#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__)  (((__val__) << 16u) & 0x30000u)
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u

#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK  0x1c0000u
#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__)  (((__reg__) & 0x1c0000) >> 18u)
#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__)  (((__val__) << 18u) & 0x1c0000u)
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u

#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK  0xe00000u
#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__)  (((__reg__) & 0xe00000) >> 21u)
#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__)  (((__val__) << 21u) & 0xe00000u)
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u

#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK  0x7000000u
#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__)  (((__reg__) & 0x7000000) >> 24u)
#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__)  (((__val__) << 24u) & 0x7000000u)
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u

#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK  0x38000000u
#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__)  (((__reg__) & 0x38000000) >> 27u)
#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__)  (((__val__) << 27u) & 0x38000000u)
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u
#define     DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u


#define REG_DEVICE2_7C04 ((volatile APE_DEVICE2_H_uint32_t*)0xa0067c04) /* PCIe-related. tg3 driver calls this  */
/** @brief Device Registers, function 2 */
extern volatile DEVICE_t DEVICE2;



#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */
#undef volatile
#endif /* CXX_SIMULATOR */

#undef register_container
#undef BITFIELD_BEGIN
#undef BITFIELD_MEMBER
#undef BITFIELD_END

#endif /* !APE_DEVICE2_H */

/** @} */