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* Split APE SHM out of the APE register area. Instantiate 4x in the APE, one pe...Evan Lojewski2019-03-231-18/+19
* Allow spaces in the build path.Evan Lojewski2019-03-181-2/+1
* Update stage1 to perform all required init. Remove stage2 folder.Evan Lojewski2019-03-162-57/+98
* Add missing DEVICE.EavRefClockControl initialization.Evan Lojewski2019-03-111-7/+15
* Update staage1 to properly crc stage2. Update to report the correct magic.Evan Lojewski2019-02-281-2/+7
* Aquire the APE lock before configuring the MII ports.Evan Lojewski2019-02-262-2/+5
* Ensure MII Port0 init only runs on function 0. Als fix mac addr loading.Evan Lojewski2019-02-261-48/+51
* Add some additional debugging to stage1 init code.Evan Lojewski2019-02-241-32/+48
* Update stage1 code to latest implimentation. Zero out bss during early init.Evan Lojewski2019-02-234-10/+59
* Update stage1 to load stage2 and report the status.Evan Lojewski2019-02-231-3/+81
* Add additional init-from-nvm codeEvan Lojewski2019-02-191-19/+67
* Add additional nvm configuration handling.Evan Lojewski2019-02-191-27/+66
* Add additional init-from-NVM code.Evan Lojewski2019-02-191-3/+97
* Add additional hw initialization.Evan Lojewski2019-02-181-3/+54
* Run stage1 init_hw.c through clang-format.Evan Lojewski2019-02-181-6/+3
* Update MII init code to match latest description for port 0.Evan Lojewski2019-02-181-6/+13
* Impliment mii initialization routines for stage 1.Evan Lojewski2019-02-163-7/+53
* Update nvrma format to more closely match ortega spec.Evan Lojewski2019-02-113-4/+4
* Add an iniital WIP version of stage1 main.Evan Lojewski2019-02-114-5/+159
* Add an initial linker script and crt file for stage1Evan Lojewski2019-02-103-2/+75
* Do a manual clang-format runEvan Lojewski2019-02-091-18/+29
* Rename stage0 to stage1, matching https://github.com/hlandau/ortega/blob/mast...Evan Lojewski2019-02-093-0/+175
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