Commit message (Expand) | Author | Age | Files | Lines | |
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* | stage1: Ensure PciConfig is initialized to enable APE writes from the host. (... | Evan Lojewski | 2021-05-15 | 1 | -1/+1 |
* | stage1: Cleanup trivial linting warnings. (#166) | Evan Lojewski | 2020-11-08 | 1 | -3/+3 |
* | stage1: Enable spi printouts when running from the RX CPU. (#9) | Evan Lojewski | 2019-12-28 | 1 | -4/+8 |
* | MII: Add a device parameter to enable the APE to use different registers base... | Evan Lojewski | 2019-08-07 | 1 | -2/+8 |
* | More cleanup - headers. | Evan Lojewski | 2019-05-05 | 1 | -2/+1 |
* | Update stage1 code to latest implimentation. Zero out bss during early init. | Evan Lojewski | 2019-02-23 | 1 | -0/+12 |
* | Impliment mii initialization routines for stage 1. | Evan Lojewski | 2019-02-16 | 1 | -0/+2 |
* | Update nvrma format to more closely match ortega spec. | Evan Lojewski | 2019-02-11 | 1 | -1/+1 |
* | Add an iniital WIP version of stage1 main. | Evan Lojewski | 2019-02-11 | 1 | -0/+52 |