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-rw-r--r--libs/MII/include/MII.h23
-rw-r--r--libs/MII/mii.c92
-rw-r--r--libs/NCSI/ncsi.c12
-rw-r--r--stage1/init_hw.c58
-rw-r--r--stage1/main.c8
-rw-r--r--stage1/stage1.h10
6 files changed, 120 insertions, 83 deletions
diff --git a/libs/MII/include/MII.h b/libs/MII/include/MII.h
index 2eda373..f8405e5 100644
--- a/libs/MII/include/MII.h
+++ b/libs/MII/include/MII.h
@@ -44,10 +44,17 @@
#ifndef MII_H
#define MII_H
+#if __mips__
+#include <bcm5719_DEVICE.h>
+#else
+#include <APE_DEVICE.h>
+#endif
+
#include <bcm5719_MII.h>
#include <types.h>
#ifdef CXX_SIMULATOR
+#define volatile
typedef uint64_t mii_reg_t;
#else
typedef uint8_t mii_reg_t;
@@ -60,31 +67,35 @@ typedef uint8_t mii_reg_t;
*
* @returns The PHY address
*/
-uint8_t MII_getPhy(void);
+uint8_t MII_getPhy(volatile DEVICE_t* device);
/**
* @fn uint16_t MII_readRegister(uint8_t PHY, uint8_t reg);
*/
-uint16_t MII_readRegister(uint8_t phy, mii_reg_t reg);
+uint16_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg);
/**
* @fn void MII_writeRegister(uint8_t PHY, uint8_t reg, uint16_t data);
*/
-void MII_writeRegister(uint8_t phy, mii_reg_t reg, uint16_t data);
+void MII_writeRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data);
/**
* @fn void MII_selectBlock(uint8_t phy, uint16_t block);
*/
-void MII_selectBlock(uint8_t phy, uint16_t block);
+void MII_selectBlock(volatile DEVICE_t* device, uint8_t phy, uint16_t block);
/**
* @fn uint16_t MII_getBlock(uint8_t phy);
*/
-uint16_t MII_getBlock(uint8_t phy);
+uint16_t MII_getBlock(volatile DEVICE_t* device, uint8_t phy);
/**
* @fn void MII_reset(uint8_t phy);
*/
-void MII_reset(uint8_t phy);
+void MII_reset(volatile DEVICE_t* device, uint8_t phy);
+
+#ifdef CXX_SIMULATOR
+#undef volatile
+#endif
#endif /* MII_H */
diff --git a/libs/MII/mii.c b/libs/MII/mii.c
index 5725a3f..b070fe6 100644
--- a/libs/MII/mii.c
+++ b/libs/MII/mii.c
@@ -42,32 +42,40 @@
/// @endcond
////////////////////////////////////////////////////////////////////////////////
#include <MII.h>
+#if __mips__
#include <bcm5719_DEVICE.h>
+#else
+#include <APE_DEVICE.h>
+#endif
-static void __attribute__((noinline)) MII_wait(void)
+#ifdef CXX_SIMULATOR
+#define volatile
+#endif
+
+static void __attribute__((noinline)) MII_wait(volatile DEVICE_t* device)
{
// Wait for the status bit to be clear.
- while (DEVICE.MiiCommunication.bits.Start_DIV_Busy)
+ while (device->MiiCommunication.bits.Start_DIV_Busy)
{
// Waiting...
}
}
-uint8_t MII_getPhy(void)
+uint8_t MII_getPhy(volatile DEVICE_t* device)
{
- if (DEVICE.SgmiiStatus.bits.MediaSelectionMode)
+ if (device->SgmiiStatus.bits.MediaSelectionMode)
{
// SERDES platform
- return DEVICE.Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0;
+ return device->Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0;
}
else
{
// GPHY platform
- return DEVICE.Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0;
+ return device->Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0;
}
}
-static uint16_t MII_readRegisterInternal(uint8_t phy, mii_reg_t reg)
+static uint16_t MII_readRegisterInternal(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg)
{
union
{
@@ -84,18 +92,18 @@ static uint16_t MII_readRegisterInternal(uint8_t phy, mii_reg_t reg)
regcontents.bits.RegisterAddress = caster.addr;
// Ensure there are no active transactions
- MII_wait();
+ MII_wait(device);
// Start the transaction
- DEVICE.MiiCommunication = regcontents;
+ device->MiiCommunication = regcontents;
// Wait for transaction to complete.
- MII_wait();
+ MII_wait(device);
- return DEVICE.MiiCommunication.bits.TransactionData;
+ return device->MiiCommunication.bits.TransactionData;
}
-static void MII_writeRegisterInternal(uint8_t phy, mii_reg_t reg, uint16_t data)
+static void MII_writeRegisterInternal(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data)
{
RegDEVICEMiiCommunication_t regcontents;
regcontents.r32 = 0;
@@ -106,16 +114,16 @@ static void MII_writeRegisterInternal(uint8_t phy, mii_reg_t reg, uint16_t data)
regcontents.bits.TransactionData = data;
// Ensure there are no active transactions
- MII_wait();
+ MII_wait(device);
// Start the transaction
- DEVICE.MiiCommunication = regcontents;
+ device->MiiCommunication = regcontents;
// Wait for transaction to complete (not strictly required for writes).
- MII_wait();
+ MII_wait(device);
}
-static uint16_t MII_readShadowRegister18(uint8_t phy, mii_reg_t reg)
+static uint16_t MII_readShadowRegister18(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg)
{
// Write register 18h, bits [2:0] = 111 This selects the Miscellaneous
// Control register, shadow 7h. All reads must be performed through the
@@ -138,12 +146,12 @@ static uint16_t MII_readShadowRegister18(uint8_t phy, mii_reg_t reg)
shadow_select.r16 = 0;
shadow_select.bits.ShadowRegisterReadSelector = shadow_reg;
shadow_select.bits.ShadowRegisterSelector = 7;
- MII_writeRegisterInternal(phy, (mii_reg_t)0x18, shadow_select.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)0x18, shadow_select.r16);
- return MII_readRegisterInternal(phy, (mii_reg_t)0x18);
+ return MII_readRegisterInternal(device, phy, (mii_reg_t)0x18);
}
-static uint16_t MII_readShadowRegister1C(uint8_t phy, mii_reg_t reg)
+static uint16_t MII_readShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg)
{
// --------------------------------------------
// PHY 0x1C Shadow 0x1 register read Procedure
@@ -157,28 +165,28 @@ static uint16_t MII_readShadowRegister1C(uint8_t phy, mii_reg_t reg)
RegMIICabletronLed_t shadow_select;
shadow_select.r16 = 0;
shadow_select.bits.ShadowRegisterSelector = shadow_reg;
- MII_writeRegisterInternal(phy, (mii_reg_t)0x1C, shadow_select.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)0x1C, shadow_select.r16);
- return MII_readRegisterInternal(phy, (mii_reg_t)0x1C);
+ return MII_readRegisterInternal(device, phy, (mii_reg_t)0x1C);
}
-uint16_t MII_readRegister(uint8_t phy, mii_reg_t reg)
+uint16_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg)
{
if ((reg & 0xFF) == 0x1C)
{
- return MII_readShadowRegister1C(phy, reg);
+ return MII_readShadowRegister1C(device, phy, reg);
}
else if ((reg & 0xFF) == 0x18)
{
- return MII_readShadowRegister18(phy, reg);
+ return MII_readShadowRegister18(device, phy, reg);
}
else
{
- return MII_readRegisterInternal(phy, reg);
+ return MII_readRegisterInternal(device, phy, reg);
}
}
-static void MII_writeShadowRegister18(uint8_t phy, mii_reg_t reg, uint16_t data)
+static void MII_writeShadowRegister18(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data)
{
// Set Bits [15:3] = Preferred write values Bits [15:3] contain the desired
// bits to be written to. Set Bits [2:0] = yyy This enables shadow register
@@ -196,15 +204,15 @@ static void MII_writeShadowRegister18(uint8_t phy, mii_reg_t reg, uint16_t data)
shadow_select.r16 = 0;
shadow_select.bits.ShadowRegisterReadSelector = shadow_reg;
shadow_select.bits.ShadowRegisterSelector = 7;
- MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, shadow_select.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, shadow_select.r16);
RegMIIMiscellaneousControl_t write_data;
write_data.r16 = data;
write_data.bits.ShadowRegisterSelector = shadow_reg;
- MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, write_data.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, write_data.r16);
}
-static void MII_writeShadowRegister1C(uint8_t phy, mii_reg_t reg, uint16_t data)
+static void MII_writeShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data)
{
// --------------------------------------------
// PHY 0x1C Shadow 0x2 register write Procedure
@@ -217,51 +225,51 @@ static void MII_writeShadowRegister1C(uint8_t phy, mii_reg_t reg, uint16_t data)
RegMIICabletronLed_t shadow_select;
shadow_select.r16 = 0;
shadow_select.bits.ShadowRegisterSelector = shadow_reg;
- MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, shadow_select.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, shadow_select.r16);
RegMIICabletronLed_t write_data;
write_data.r16 = data;
write_data.bits.ShadowRegisterSelector = shadow_reg;
write_data.bits.WriteEnable = 1;
- MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, write_data.r16);
+ MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, write_data.r16);
}
-void MII_writeRegister(uint8_t phy, mii_reg_t reg, uint16_t data)
+void MII_writeRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data)
{
if ((reg & 0xFF) == 0x1C)
{
- MII_writeShadowRegister1C(phy, reg, data);
+ MII_writeShadowRegister1C(device, phy, reg, data);
}
else if ((reg & 0xFF) == 0x18)
{
- MII_writeShadowRegister18(phy, reg, data);
+ MII_writeShadowRegister18(device, phy, reg, data);
}
else
{
- MII_writeRegisterInternal(phy, reg, data);
+ MII_writeRegisterInternal(device, phy, reg, data);
}
}
-void MII_selectBlock(uint8_t phy, uint16_t block)
+void MII_selectBlock(volatile DEVICE_t* device, uint8_t phy, uint16_t block)
{
// Write register 0x1f with the block.
- MII_writeRegister(phy, (mii_reg_t)REG_MII_BLOCK_SELECT, block);
+ MII_writeRegister(device, phy, (mii_reg_t)REG_MII_BLOCK_SELECT, block);
}
-uint16_t MII_getBlock(uint8_t phy)
+uint16_t MII_getBlock(volatile DEVICE_t* device, uint8_t phy)
{
// Write register 0x1f with the block.
- return MII_readRegister(phy, (mii_reg_t)REG_MII_BLOCK_SELECT);
+ return MII_readRegister(device, phy, (mii_reg_t)REG_MII_BLOCK_SELECT);
}
-void MII_reset(uint8_t phy)
+void MII_reset(volatile DEVICE_t* device, uint8_t phy)
{
// Set MII_REG_CONTROL to RESET; wait until RESET bit clears.
- MII_writeRegister(phy, (mii_reg_t)REG_MII_CONTROL, MII_CONTROL_RESET_MASK);
+ MII_writeRegister(device, phy, (mii_reg_t)REG_MII_CONTROL, MII_CONTROL_RESET_MASK);
do
{
// Spin
- } while ((MII_readRegister(phy, (mii_reg_t)REG_MII_CONTROL) & MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK);
+ } while ((MII_readRegister(device, phy, (mii_reg_t)REG_MII_CONTROL) & MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK);
}
diff --git a/libs/NCSI/ncsi.c b/libs/NCSI/ncsi.c
index ebf44da..5529cc0 100644
--- a/libs/NCSI/ncsi.c
+++ b/libs/NCSI/ncsi.c
@@ -430,13 +430,15 @@ static void getLinkStatusHandler(NetworkFrame_t *frame)
RegMIIIeeeExtendedStatus_t ext_stat;
ext_stat.r16 = 0;
- uint8_t phy = DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0; // MII_getPhy();
+ int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK;
+ channel_state_t *channel = &(gPackageState.channel[ch]);
+ uint8_t phy = MII_getPhy(channel->port->device);
APE_aquireLock();
- uint16_t status_value = MII_readRegister(phy, (mii_reg_t)REG_MII_STATUS);
+ uint16_t status_value = MII_readRegister(channel->port->device, phy, (mii_reg_t)REG_MII_STATUS);
stat.r16 = status_value;
if (stat.bits.ExtendedStatusSupported)
{
- uint16_t ext_status_value = MII_readRegister(phy, (mii_reg_t)REG_MII_IEEE_EXTENDED_STATUS);
+ uint16_t ext_status_value = MII_readRegister(channel->port->device, phy, (mii_reg_t)REG_MII_IEEE_EXTENDED_STATUS);
ext_stat.r16 = ext_status_value;
}
@@ -458,8 +460,6 @@ static void getLinkStatusHandler(NetworkFrame_t *frame)
linkStatus.bits.LinkSpeed10M_TFullDuplexCapable = stat.bits._10BASE_TFullDuplexCapable;
linkStatus.bits.LinkSpeed10M_THalfDuplexCapable = stat.bits._10BASE_THalfDuplexCapable;
- int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK;
- channel_state_t *channel = &(gPackageState.channel[ch]);
channel->shm->NcsiChannelStatus = linkStatus;
uint32_t LinkStatus = linkStatus.r32;
@@ -689,7 +689,7 @@ void resetChannel(int ch)
APE_aquireLock();
uint8_t phy = DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 + ch;
- MII_writeRegister(phy, (mii_reg_t)0, 0x8000);
+ MII_writeRegister(channel->port->device, phy, (mii_reg_t)0, 0x8000);
APE_releaseLock();
diff --git a/stage1/init_hw.c b/stage1/init_hw.c
index 68f6348..fd7dafc 100644
--- a/stage1/init_hw.c
+++ b/stage1/init_hw.c
@@ -46,13 +46,21 @@
#include <MII.h>
#include <APE.h>
+#if CXX_SIMULATOR
+#include <APE_DEVICE.h>
+#else
#include <bcm5719_DEVICE.h>
+#endif
#include <bcm5719_GEN.h>
#include <bcm5719_RXMBUF.h>
#include <bcm5719_TXMBUF.h>
#include <bcm5719_SDBCACHE.h>
#include <types.h>
+#if CXX_SIMULATOR
+#define volatile
+#endif
+
void *memset(void *s, int c, size_t n)
{
#if CXX_SIMULATOR
@@ -75,17 +83,17 @@ static inline bool is_nic(void)
return (1 == DEVICE.Status.bits.VMAINPowerStatus);
}
-void init_mii_function0(void)
+void init_mii_function0(volatile DEVICE_t* device)
{
if(0 == DEVICE.Status.bits.FunctionNumber)
{
reportStatus(STATUS_INIT_HW, 0xf1);
// MIIPORT 0 (0x8010):0x1A |= 0x4000
- MII_selectBlock(0, 0x8010);
- uint16_t r1Ah_value = MII_readRegister(0, (mii_reg_t)0x1A);
+ MII_selectBlock(device, 0, 0x8010);
+ uint16_t r1Ah_value = MII_readRegister(device, 0, (mii_reg_t)0x1A);
r1Ah_value |= 0x4000;
- MII_writeRegister(0, (mii_reg_t)0x1A, r1Ah_value);
+ MII_writeRegister(device, 0, (mii_reg_t)0x1A, r1Ah_value);
reportStatus(STATUS_INIT_HW, 0xf2);
@@ -93,16 +101,16 @@ void init_mii_function0(void)
// reading 0x1F and confirming it reads 0x8610
do
{
- MII_selectBlock(0, 0x8610);
- } while (0x8610 != MII_getBlock(0));
+ MII_selectBlock(device, 0, 0x8610);
+ } while (0x8610 != MII_getBlock(device, 0));
reportStatus(STATUS_INIT_HW, 0xf3);
// MIIPORT 0 (0x8610):0x15, set bits 0:1 to 2.
- uint16_t r15h_value = MII_readRegister(0, (mii_reg_t)0x15);
+ uint16_t r15h_value = MII_readRegister(device, 0, (mii_reg_t)0x15);
r15h_value &= ~0x3;
r15h_value |= 0x2;
- MII_writeRegister(0, (mii_reg_t)0x15, r15h_value);
+ MII_writeRegister(device, 0, (mii_reg_t)0x15, r15h_value);
reportStatus(STATUS_INIT_HW, 0xf4);
@@ -112,33 +120,33 @@ void init_mii_function0(void)
// these unknown MII registers.)
do
{
- r15h_value = MII_readRegister(0, (mii_reg_t)0x15);
+ r15h_value = MII_readRegister(device, 0, (mii_reg_t)0x15);
} while (2 != (r15h_value & 0x3));
reportStatus(STATUS_INIT_HW, 0xf5);
// (0x8010):0x1A, mask 0x4000.
- MII_selectBlock(0, 0x8010);
+ MII_selectBlock(device, 0, 0x8010);
r1Ah_value &= ~0x4000;
- MII_writeRegister(0, (mii_reg_t)0x1A, r1Ah_value);
+ MII_writeRegister(device, 0, (mii_reg_t)0x1A, r1Ah_value);
reportStatus(STATUS_INIT_HW, 0xf6);
- MII_selectBlock(0, 0);
+ MII_selectBlock(device, 0, 0);
reportStatus(STATUS_INIT_HW, 0xf7);
}
}
-void init_mii(void)
+void init_mii(volatile DEVICE_t* device)
{
// MII init for all functions (MIIPORT determined by function/PHY type):
// Set MII_REG_CONTROL to AUTO_NEGOTIATION_ENABLE.
- uint8_t phy = MII_getPhy();
+ uint8_t phy = MII_getPhy(device);
RegMIIControl_t control;
- control.r16 = MII_readRegister(phy, (mii_reg_t)REG_MII_CONTROL);
+ control.r16 = MII_readRegister(device, phy, (mii_reg_t)REG_MII_CONTROL);
control.bits.AutoNegotiationEnable = 1;
- MII_writeRegister(phy, (mii_reg_t)REG_MII_CONTROL, control.r16);
+ MII_writeRegister(device, phy, (mii_reg_t)REG_MII_CONTROL, control.r16);
}
void __attribute__((noinline)) zero_bss(void)
@@ -274,9 +282,9 @@ void init_power(NVRAMContents_t *nvram)
DEVICE.PciPowerBudget7.r32 = translate_power_budget(pb_raw7);
}
-uint16_t nvm_get_subsystem_device(NVRAMContents_t* nvram)
+uint16_t nvm_get_subsystem_device(volatile DEVICE_t *device, NVRAMContents_t* nvram)
{
- switch(MII_getPhy())
+ switch(MII_getPhy(device))
{
/* SERDES */
case DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0:
@@ -304,7 +312,7 @@ uint16_t nvm_get_subsystem_device(NVRAMContents_t* nvram)
}
}
-void init_pci(NVRAMContents_t* nvram)
+void init_pci(volatile DEVICE_t *device, NVRAMContents_t* nvram)
{
// PCI Device / Vendor ID.
RegDEVICEPciVendorDeviceId_t vendor_device;
@@ -317,7 +325,7 @@ void init_pci(NVRAMContents_t* nvram)
RegDEVICEPciSubsystemId_t subsystem;
subsystem.r32 = 0;
subsystem.bits.SubsystemVendorID = nvram->info.subsystemVendorID;
- subsystem.bits.SubsystemID = nvm_get_subsystem_device(nvram);
+ subsystem.bits.SubsystemID = nvm_get_subsystem_device(device, nvram);
DEVICE.PciSubsystemId = subsystem;
// RegDEVICEPciClassCodeRevision_t partially from REG_CHIP_ID
@@ -365,7 +373,7 @@ void init_gen(NVRAMContents_t* nvram)
GEN.GenCfg5.r32 = nvram->info2.cfg5;
}
-void load_nvm_config(NVRAMContents_t *nvram)
+void load_nvm_config(volatile DEVICE_t* device, NVRAMContents_t *nvram)
{
// Load information from NVM, set various registers + mem
@@ -380,12 +388,12 @@ void load_nvm_config(NVRAMContents_t *nvram)
init_power(nvram);
// REG_PCI_SUBSYSTEM_ID, vendor, class, rev
- init_pci(nvram);
+ init_pci(device, nvram);
init_gen(nvram);
}
-void init_hw(NVRAMContents_t *nvram)
+void init_hw(volatile DEVICE_t* device, NVRAMContents_t *nvram)
{
reportStatus(STATUS_INIT_HW, 0);
// Misc regs init
@@ -473,11 +481,11 @@ void init_hw(NVRAMContents_t *nvram)
// Perform MII init.
APE_aquireLock();
- init_mii_function0();
+ init_mii_function0(device);
reportStatus(STATUS_INIT_HW, 0xfe);
- init_mii();
+ init_mii(device);
APE_releaseLock();
diff --git a/stage1/main.c b/stage1/main.c
index 10fe0be..c1cd296 100644
--- a/stage1/main.c
+++ b/stage1/main.c
@@ -58,7 +58,11 @@
#include <NVRam.h>
#include <bcm5719_APE.h>
#include <bcm5719_BOOTCODE.h>
+#if CXX_SIMULATOR
+#include <APE_DEVICE.h>
+#else
#include <bcm5719_DEVICE.h>
+#endif
#include <bcm5719_GEN.h>
#include <bcm5719_SHM.h>
@@ -87,10 +91,10 @@ int main()
NVRam_releaseLock();
#if !CXX_SIMULATOR
- load_nvm_config(&gNVMContents);
+ load_nvm_config(&DEVICE, &gNVMContents);
// Initialize the hardware.
- init_hw(&gNVMContents);
+ init_hw(&DEVICE, &gNVMContents);
#endif
// Send configuration information to APE SHM.
diff --git a/stage1/stage1.h b/stage1/stage1.h
index dac77aa..75fa147 100644
--- a/stage1/stage1.h
+++ b/stage1/stage1.h
@@ -47,10 +47,16 @@
#include <bcm5719_GEN.h>
#include <bcm5719_eeprom.h>
+#if CXX_SIMULATOR
+#include <APE_DEVICE.h>
+#define volatile
+#else
+#include <bcm5719_DEVICE.h>
+#endif
void early_init_hw(void);
-void load_nvm_config(NVRAMContents_t *nvram);
-void init_hw(NVRAMContents_t *nvram);
+void load_nvm_config(volatile DEVICE_t* device, NVRAMContents_t *nvram);
+void init_hw(volatile DEVICE_t* device, NVRAMContents_t *nvram);
#define STATUS_MAIN (0x8234700u)
#define STATUS_EARLY_INIT (0x8234800u)
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