diff options
| -rw-r--r-- | include/APE_DEVICE.h | 209 | ||||
| -rw-r--r-- | include/APE_DEVICE1.h | 6 | ||||
| -rw-r--r-- | include/APE_DEVICE2.h | 6 | ||||
| -rw-r--r-- | include/APE_DEVICE3.h | 6 | ||||
| -rw-r--r-- | include/bcm5719_DEVICE.h | 207 | ||||
| -rw-r--r-- | ipxact/DEVICE.xml | 60 | ||||
| -rw-r--r-- | simulator/APE_DEVICE.cpp | 10 | ||||
| -rw-r--r-- | simulator/APE_DEVICE1.cpp | 10 | ||||
| -rw-r--r-- | simulator/APE_DEVICE1_sim.cpp | 18 | ||||
| -rw-r--r-- | simulator/APE_DEVICE2.cpp | 10 | ||||
| -rw-r--r-- | simulator/APE_DEVICE2_sim.cpp | 18 | ||||
| -rw-r--r-- | simulator/APE_DEVICE3.cpp | 10 | ||||
| -rw-r--r-- | simulator/APE_DEVICE3_sim.cpp | 18 | ||||
| -rw-r--r-- | simulator/APE_DEVICE_sim.cpp | 18 | ||||
| -rw-r--r-- | simulator/bcm5719_DEVICE.cpp | 10 | ||||
| -rw-r--r-- | simulator/bcm5719_DEVICE_sim.cpp | 38 |
16 files changed, 608 insertions, 46 deletions
diff --git a/include/APE_DEVICE.h b/include/APE_DEVICE.h index 54096bf..59c30ea 100644 --- a/include/APE_DEVICE.h +++ b/include/APE_DEVICE.h @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -5602,6 +5602,31 @@ typedef register_container RegDEVICERxRiscStatus_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscStatus_t; +#define REG_DEVICE_RX_RISC_EVENT_MASK ((volatile APE_DEVICE_H_uint32_t*)0xa0045008) /* */ +/** @brief Register definition for @ref DEVICE_t.RxRiscEventMask. */ +typedef register_container RegDEVICERxRiscEventMask_t { + /** @brief 32bit direct register access. */ + APE_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscEventMask"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscEventMask_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscEventMask. */ + r32.setName("RxRiscEventMask"); + } + RegDEVICERxRiscEventMask_t& operator=(const RegDEVICERxRiscEventMask_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscEventMask_t; + #define REG_DEVICE_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE_H_uint32_t*)0xa004501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ /** @brief Register definition for @ref DEVICE_t.RxRiscProgramCounter. */ typedef register_container RegDEVICERxRiscProgramCounter_t { @@ -5627,7 +5652,7 @@ typedef register_container RegDEVICERxRiscProgramCounter_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscProgramCounter_t; -#define REG_DEVICE_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE_H_uint32_t*)0xa0045020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE_H_uint32_t*)0xa0045020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ /** @brief Register definition for @ref DEVICE_t.RxRiscCurrentInstruction. */ typedef register_container RegDEVICERxRiscCurrentInstruction_t { /** @brief 32bit direct register access. */ @@ -5652,6 +5677,56 @@ typedef register_container RegDEVICERxRiscCurrentInstruction_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscCurrentInstruction_t; +#define REG_DEVICE_RX_RISC_INTERRUPT_ENABLE ((volatile APE_DEVICE_H_uint32_t*)0xa0045028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ +/** @brief Register definition for @ref DEVICE_t.RxRiscInterruptEnable. */ +typedef register_container RegDEVICERxRiscInterruptEnable_t { + /** @brief 32bit direct register access. */ + APE_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscInterruptEnable"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscInterruptEnable_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscInterruptEnable. */ + r32.setName("RxRiscInterruptEnable"); + } + RegDEVICERxRiscInterruptEnable_t& operator=(const RegDEVICERxRiscInterruptEnable_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscInterruptEnable_t; + +#define REG_DEVICE_RX_RISC_INTERRUPT_VECTOR ((volatile APE_DEVICE_H_uint32_t*)0xa004502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ +/** @brief Register definition for @ref DEVICE_t.RxRiscInterruptVector. */ +typedef register_container RegDEVICERxRiscInterruptVector_t { + /** @brief 32bit direct register access. */ + APE_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscInterruptVector"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscInterruptVector_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscInterruptVector. */ + r32.setName("RxRiscInterruptVector"); + } + RegDEVICERxRiscInterruptVector_t& operator=(const RegDEVICERxRiscInterruptVector_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscInterruptVector_t; + #define REG_DEVICE_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE_H_uint32_t*)0xa0045034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ /** @brief Register definition for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ typedef register_container RegDEVICERxRiscHardwareBreakpoint_t { @@ -5677,6 +5752,70 @@ typedef register_container RegDEVICERxRiscHardwareBreakpoint_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscHardwareBreakpoint_t; +#define REG_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS ((volatile APE_DEVICE_H_uint32_t*)0xa0045048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_SHIFT 1u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_MASK 0x2u +#define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_JUMP 0x0u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_BRANCH 0x1u + +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_SHIFT 2u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_MASK 0xfffffffcu +#define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__reg__) (((__reg__) & 0xfffffffc) >> 2u) +#define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__val__) (((__val__) << 2u) & 0xfffffffcu) + +/** @brief Register definition for @ref DEVICE_t.RxRiscLastBranchAddress. */ +typedef register_container RegDEVICERxRiscLastBranchAddress_t { + /** @brief 32bit direct register access. */ + APE_DEVICE_H_uint32_t r32; + + BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) + /** @brief This indicates the jump or branch type. */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 1, 1) + /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) +#elif defined(__BIG_ENDIAN__) + /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) + /** @brief This indicates the jump or branch type. */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Type, 1, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) +#else +#error Unknown Endian +#endif + BITFIELD_END(APE_DEVICE_H_uint32_t, bits) +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscLastBranchAddress"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscLastBranchAddress_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscLastBranchAddress. */ + r32.setName("RxRiscLastBranchAddress"); + bits.Type.setBaseRegister(&r32); + bits.Type.setName("Type"); + bits.Type.addEnum("Jump", 0x0); + bits.Type.addEnum("Branch", 0x1); + + bits.LastBranchAddress.setBaseRegister(&r32); + bits.LastBranchAddress.setName("LastBranchAddress"); + } + RegDEVICERxRiscLastBranchAddress_t& operator=(const RegDEVICERxRiscLastBranchAddress_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscLastBranchAddress_t; + #define REG_DEVICE_RX_RISC_REGISTER_0 ((volatile APE_DEVICE_H_uint32_t*)0xa0045200) /* $zero (R0) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister0. */ typedef register_container RegDEVICERxRiscRegister0_t { @@ -9326,23 +9465,41 @@ typedef struct DEVICE_t { /** @brief */ RegDEVICERxRiscStatus_t RxRiscStatus; + /** @brief */ + RegDEVICERxRiscEventMask_t RxRiscEventMask; + /** @brief Reserved bytes to pad out data structure. */ - APE_DEVICE_H_uint32_t reserved_20488[5]; + APE_DEVICE_H_uint32_t reserved_20492[4]; /** @brief The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ RegDEVICERxRiscProgramCounter_t RxRiscProgramCounter; - /** @brief This undocumented register contains the current word located at the program counter address loaded in */ + /** @brief This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ RegDEVICERxRiscCurrentInstruction_t RxRiscCurrentInstruction; /** @brief Reserved bytes to pad out data structure. */ - APE_DEVICE_H_uint32_t reserved_20516[4]; + APE_DEVICE_H_uint32_t reserved_20516[1]; + + /** @brief Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ + RegDEVICERxRiscInterruptEnable_t RxRiscInterruptEnable; + + /** @brief This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ + RegDEVICERxRiscInterruptVector_t RxRiscInterruptVector; + + /** @brief Reserved bytes to pad out data structure. */ + APE_DEVICE_H_uint32_t reserved_20528[1]; /** @brief This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ RegDEVICERxRiscHardwareBreakpoint_t RxRiscHardwareBreakpoint; /** @brief Reserved bytes to pad out data structure. */ - APE_DEVICE_H_uint32_t reserved_20536[114]; + APE_DEVICE_H_uint32_t reserved_20536[4]; + + /** @brief This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ + RegDEVICERxRiscLastBranchAddress_t RxRiscLastBranchAddress; + + /** @brief Reserved bytes to pad out data structure. */ + APE_DEVICE_H_uint32_t reserved_20556[109]; /** @brief $zero (R0) */ RegDEVICERxRiscRegister0_t RxRiscRegister0; @@ -9802,21 +9959,33 @@ typedef struct DEVICE_t { } RxRiscMode.r32.setComponentOffset(0x5000); RxRiscStatus.r32.setComponentOffset(0x5004); - for(int i = 0; i < 5; i++) + RxRiscEventMask.r32.setComponentOffset(0x5008); + for(int i = 0; i < 4; i++) { - reserved_20488[i].setComponentOffset(0x5008 + (i * 4)); + reserved_20492[i].setComponentOffset(0x500c + (i * 4)); } RxRiscProgramCounter.r32.setComponentOffset(0x501c); RxRiscCurrentInstruction.r32.setComponentOffset(0x5020); - for(int i = 0; i < 4; i++) + for(int i = 0; i < 1; i++) { reserved_20516[i].setComponentOffset(0x5024 + (i * 4)); } + RxRiscInterruptEnable.r32.setComponentOffset(0x5028); + RxRiscInterruptVector.r32.setComponentOffset(0x502c); + for(int i = 0; i < 1; i++) + { + reserved_20528[i].setComponentOffset(0x5030 + (i * 4)); + } RxRiscHardwareBreakpoint.r32.setComponentOffset(0x5034); - for(int i = 0; i < 114; i++) + for(int i = 0; i < 4; i++) { reserved_20536[i].setComponentOffset(0x5038 + (i * 4)); } + RxRiscLastBranchAddress.r32.setComponentOffset(0x5048); + for(int i = 0; i < 109; i++) + { + reserved_20556[i].setComponentOffset(0x504c + (i * 4)); + } RxRiscRegister0.r32.setComponentOffset(0x5200); RxRiscRegister1.r32.setComponentOffset(0x5204); RxRiscRegister2.r32.setComponentOffset(0x5208); @@ -10152,21 +10321,33 @@ typedef struct DEVICE_t { } RxRiscMode.print(); RxRiscStatus.print(); - for(int i = 0; i < 5; i++) + RxRiscEventMask.print(); + for(int i = 0; i < 4; i++) { - reserved_20488[i].print(); + reserved_20492[i].print(); } RxRiscProgramCounter.print(); RxRiscCurrentInstruction.print(); - for(int i = 0; i < 4; i++) + for(int i = 0; i < 1; i++) { reserved_20516[i].print(); } + RxRiscInterruptEnable.print(); + RxRiscInterruptVector.print(); + for(int i = 0; i < 1; i++) + { + reserved_20528[i].print(); + } RxRiscHardwareBreakpoint.print(); - for(int i = 0; i < 114; i++) + for(int i = 0; i < 4; i++) { reserved_20536[i].print(); } + RxRiscLastBranchAddress.print(); + for(int i = 0; i < 109; i++) + { + reserved_20556[i].print(); + } RxRiscRegister0.print(); RxRiscRegister1.print(); RxRiscRegister2.print(); diff --git a/include/APE_DEVICE1.h b/include/APE_DEVICE1.h index 475c8ef..68b4c24 100644 --- a/include/APE_DEVICE1.h +++ b/include/APE_DEVICE1.h @@ -152,9 +152,13 @@ typedef uint32_t APE_DEVICE1_H_uint32_t; #define REG_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0054910) /* */ #define REG_DEVICE1_RX_RISC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0055000) /* */ #define REG_DEVICE1_RX_RISC_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0055004) /* */ +#define REG_DEVICE1_RX_RISC_EVENT_MASK ((volatile APE_DEVICE1_H_uint32_t*)0xa0055008) /* */ #define REG_DEVICE1_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE1_H_uint32_t*)0xa005501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ -#define REG_DEVICE1_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE1_H_uint32_t*)0xa0055020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE1_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE1_H_uint32_t*)0xa0055020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ +#define REG_DEVICE1_RX_RISC_INTERRUPT_ENABLE ((volatile APE_DEVICE1_H_uint32_t*)0xa0055028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ +#define REG_DEVICE1_RX_RISC_INTERRUPT_VECTOR ((volatile APE_DEVICE1_H_uint32_t*)0xa005502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ #define REG_DEVICE1_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE1_H_uint32_t*)0xa0055034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE1_RX_RISC_LAST_BRANCH_ADDRESS ((volatile APE_DEVICE1_H_uint32_t*)0xa0055048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ #define REG_DEVICE1_RX_RISC_REGISTER_0 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055200) /* $zero (R0) */ #define REG_DEVICE1_RX_RISC_REGISTER_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055204) /* $at (R1) */ #define REG_DEVICE1_RX_RISC_REGISTER_2 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055208) /* $v0 (R2) */ diff --git a/include/APE_DEVICE2.h b/include/APE_DEVICE2.h index af3c53a..07063c6 100644 --- a/include/APE_DEVICE2.h +++ b/include/APE_DEVICE2.h @@ -152,9 +152,13 @@ typedef uint32_t APE_DEVICE2_H_uint32_t; #define REG_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0064910) /* */ #define REG_DEVICE2_RX_RISC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0065000) /* */ #define REG_DEVICE2_RX_RISC_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0065004) /* */ +#define REG_DEVICE2_RX_RISC_EVENT_MASK ((volatile APE_DEVICE2_H_uint32_t*)0xa0065008) /* */ #define REG_DEVICE2_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa006501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ -#define REG_DEVICE2_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE2_H_uint32_t*)0xa0065020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE2_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE2_H_uint32_t*)0xa0065020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ +#define REG_DEVICE2_RX_RISC_INTERRUPT_ENABLE ((volatile APE_DEVICE2_H_uint32_t*)0xa0065028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ +#define REG_DEVICE2_RX_RISC_INTERRUPT_VECTOR ((volatile APE_DEVICE2_H_uint32_t*)0xa006502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ #define REG_DEVICE2_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE2_H_uint32_t*)0xa0065034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE2_RX_RISC_LAST_BRANCH_ADDRESS ((volatile APE_DEVICE2_H_uint32_t*)0xa0065048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ #define REG_DEVICE2_RX_RISC_REGISTER_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065200) /* $zero (R0) */ #define REG_DEVICE2_RX_RISC_REGISTER_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065204) /* $at (R1) */ #define REG_DEVICE2_RX_RISC_REGISTER_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065208) /* $v0 (R2) */ diff --git a/include/APE_DEVICE3.h b/include/APE_DEVICE3.h index 48f7162..95f9e3e 100644 --- a/include/APE_DEVICE3.h +++ b/include/APE_DEVICE3.h @@ -152,9 +152,13 @@ typedef uint32_t APE_DEVICE3_H_uint32_t; #define REG_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0074910) /* */ #define REG_DEVICE3_RX_RISC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0075000) /* */ #define REG_DEVICE3_RX_RISC_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0075004) /* */ +#define REG_DEVICE3_RX_RISC_EVENT_MASK ((volatile APE_DEVICE3_H_uint32_t*)0xa0075008) /* */ #define REG_DEVICE3_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE3_H_uint32_t*)0xa007501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ -#define REG_DEVICE3_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE3_H_uint32_t*)0xa0075020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE3_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE3_H_uint32_t*)0xa0075020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ +#define REG_DEVICE3_RX_RISC_INTERRUPT_ENABLE ((volatile APE_DEVICE3_H_uint32_t*)0xa0075028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ +#define REG_DEVICE3_RX_RISC_INTERRUPT_VECTOR ((volatile APE_DEVICE3_H_uint32_t*)0xa007502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ #define REG_DEVICE3_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE3_H_uint32_t*)0xa0075034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE3_RX_RISC_LAST_BRANCH_ADDRESS ((volatile APE_DEVICE3_H_uint32_t*)0xa0075048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ #define REG_DEVICE3_RX_RISC_REGISTER_0 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075200) /* $zero (R0) */ #define REG_DEVICE3_RX_RISC_REGISTER_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075204) /* $at (R1) */ #define REG_DEVICE3_RX_RISC_REGISTER_2 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075208) /* $v0 (R2) */ diff --git a/include/bcm5719_DEVICE.h b/include/bcm5719_DEVICE.h index 724375a..28d6930 100644 --- a/include/bcm5719_DEVICE.h +++ b/include/bcm5719_DEVICE.h @@ -5602,6 +5602,31 @@ typedef register_container RegDEVICERxRiscStatus_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscStatus_t; +#define REG_DEVICE_RX_RISC_EVENT_MASK ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005008) /* */ +/** @brief Register definition for @ref DEVICE_t.RxRiscEventMask. */ +typedef register_container RegDEVICERxRiscEventMask_t { + /** @brief 32bit direct register access. */ + BCM5719_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscEventMask"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscEventMask_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscEventMask. */ + r32.setName("RxRiscEventMask"); + } + RegDEVICERxRiscEventMask_t& operator=(const RegDEVICERxRiscEventMask_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscEventMask_t; + #define REG_DEVICE_RX_RISC_PROGRAM_COUNTER ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ /** @brief Register definition for @ref DEVICE_t.RxRiscProgramCounter. */ typedef register_container RegDEVICERxRiscProgramCounter_t { @@ -5627,7 +5652,7 @@ typedef register_container RegDEVICERxRiscProgramCounter_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscProgramCounter_t; -#define REG_DEVICE_RX_RISC_CURRENT_INSTRUCTION ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE_RX_RISC_CURRENT_INSTRUCTION ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005020) /* This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ /** @brief Register definition for @ref DEVICE_t.RxRiscCurrentInstruction. */ typedef register_container RegDEVICERxRiscCurrentInstruction_t { /** @brief 32bit direct register access. */ @@ -5652,6 +5677,56 @@ typedef register_container RegDEVICERxRiscCurrentInstruction_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscCurrentInstruction_t; +#define REG_DEVICE_RX_RISC_INTERRUPT_ENABLE ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005028) /* Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ +/** @brief Register definition for @ref DEVICE_t.RxRiscInterruptEnable. */ +typedef register_container RegDEVICERxRiscInterruptEnable_t { + /** @brief 32bit direct register access. */ + BCM5719_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscInterruptEnable"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscInterruptEnable_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscInterruptEnable. */ + r32.setName("RxRiscInterruptEnable"); + } + RegDEVICERxRiscInterruptEnable_t& operator=(const RegDEVICERxRiscInterruptEnable_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscInterruptEnable_t; + +#define REG_DEVICE_RX_RISC_INTERRUPT_VECTOR ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000502c) /* This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ +/** @brief Register definition for @ref DEVICE_t.RxRiscInterruptVector. */ +typedef register_container RegDEVICERxRiscInterruptVector_t { + /** @brief 32bit direct register access. */ + BCM5719_DEVICE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscInterruptVector"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscInterruptVector_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscInterruptVector. */ + r32.setName("RxRiscInterruptVector"); + } + RegDEVICERxRiscInterruptVector_t& operator=(const RegDEVICERxRiscInterruptVector_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscInterruptVector_t; + #define REG_DEVICE_RX_RISC_HARDWARE_BREAKPOINT ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ /** @brief Register definition for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ typedef register_container RegDEVICERxRiscHardwareBreakpoint_t { @@ -5677,6 +5752,70 @@ typedef register_container RegDEVICERxRiscHardwareBreakpoint_t { #endif /* CXX_SIMULATOR */ } RegDEVICERxRiscHardwareBreakpoint_t; +#define REG_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005048) /* This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_SHIFT 1u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_MASK 0x2u +#define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_JUMP 0x0u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_TYPE_BRANCH 0x1u + +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_SHIFT 2u +#define DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS_MASK 0xfffffffcu +#define GET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__reg__) (((__reg__) & 0xfffffffc) >> 2u) +#define SET_DEVICE_RX_RISC_LAST_BRANCH_ADDRESS_LAST_BRANCH_ADDRESS(__val__) (((__val__) << 2u) & 0xfffffffcu) + +/** @brief Register definition for @ref DEVICE_t.RxRiscLastBranchAddress. */ +typedef register_container RegDEVICERxRiscLastBranchAddress_t { + /** @brief 32bit direct register access. */ + BCM5719_DEVICE_H_uint32_t r32; + + BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1) + /** @brief This indicates the jump or branch type. */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Type, 1, 1) + /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) +#elif defined(__BIG_ENDIAN__) + /** @brief This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value. */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, LastBranchAddress, 2, 30) + /** @brief This indicates the jump or branch type. */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Type, 1, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1) +#else +#error Unknown Endian +#endif + BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits) +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "RxRiscLastBranchAddress"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegDEVICERxRiscLastBranchAddress_t() + { + /** @brief constructor for @ref DEVICE_t.RxRiscLastBranchAddress. */ + r32.setName("RxRiscLastBranchAddress"); + bits.Type.setBaseRegister(&r32); + bits.Type.setName("Type"); + bits.Type.addEnum("Jump", 0x0); + bits.Type.addEnum("Branch", 0x1); + + bits.LastBranchAddress.setBaseRegister(&r32); + bits.LastBranchAddress.setName("LastBranchAddress"); + } + RegDEVICERxRiscLastBranchAddress_t& operator=(const RegDEVICERxRiscLastBranchAddress_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegDEVICERxRiscLastBranchAddress_t; + #define REG_DEVICE_RX_RISC_REGISTER_0 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0005200) /* $zero (R0) */ /** @brief Register definition for @ref DEVICE_t.RxRiscRegister0. */ typedef register_container RegDEVICERxRiscRegister0_t { @@ -9326,23 +9465,41 @@ typedef struct DEVICE_t { /** @brief */ RegDEVICERxRiscStatus_t RxRiscStatus; + /** @brief */ + RegDEVICERxRiscEventMask_t RxRiscEventMask; + /** @brief Reserved bytes to pad out data structure. */ - BCM5719_DEVICE_H_uint32_t reserved_20488[5]; + BCM5719_DEVICE_H_uint32_t reserved_20492[4]; /** @brief The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ RegDEVICERxRiscProgramCounter_t RxRiscProgramCounter; - /** @brief This undocumented register contains the current word located at the program counter address loaded in */ + /** @brief This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed. */ RegDEVICERxRiscCurrentInstruction_t RxRiscCurrentInstruction; /** @brief Reserved bytes to pad out data structure. */ - BCM5719_DEVICE_H_uint32_t reserved_20516[4]; + BCM5719_DEVICE_H_uint32_t reserved_20516[1]; + + /** @brief Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero. */ + RegDEVICERxRiscInterruptEnable_t RxRiscInterruptEnable; + + /** @brief This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input. */ + RegDEVICERxRiscInterruptVector_t RxRiscInterruptVector; + + /** @brief Reserved bytes to pad out data structure. */ + BCM5719_DEVICE_H_uint32_t reserved_20528[1]; /** @brief This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ RegDEVICERxRiscHardwareBreakpoint_t RxRiscHardwareBreakpoint; /** @brief Reserved bytes to pad out data structure. */ - BCM5719_DEVICE_H_uint32_t reserved_20536[114]; + BCM5719_DEVICE_H_uint32_t reserved_20536[4]; + + /** @brief This register indicates that address and branch type of the last branch that was taken. This register is for debug use only. */ + RegDEVICERxRiscLastBranchAddress_t RxRiscLastBranchAddress; + + /** @brief Reserved bytes to pad out data structure. */ + BCM5719_DEVICE_H_uint32_t reserved_20556[109]; /** @brief $zero (R0) */ RegDEVICERxRiscRegister0_t RxRiscRegister0; @@ -9802,21 +9959,33 @@ typedef struct DEVICE_t { } RxRiscMode.r32.setComponentOffset(0x5000); RxRiscStatus.r32.setComponentOffset(0x5004); - for(int i = 0; i < 5; i++) + RxRiscEventMask.r32.setComponentOffset(0x5008); + for(int i = 0; i < 4; i++) { - reserved_20488[i].setComponentOffset(0x5008 + (i * 4)); + reserved_20492[i].setComponentOffset(0x500c + (i * 4)); } RxRiscProgramCounter.r32.setComponentOffset(0x501c); RxRiscCurrentInstruction.r32.setComponentOffset(0x5020); - for(int i = 0; i < 4; i++) + for(int i = 0; i < 1; i++) { reserved_20516[i].setComponentOffset(0x5024 + (i * 4)); } + RxRiscInterruptEnable.r32.setComponentOffset(0x5028); + RxRiscInterruptVector.r32.setComponentOffset(0x502c); + for(int i = 0; i < 1; i++) + { + reserved_20528[i].setComponentOffset(0x5030 + (i * 4)); + } RxRiscHardwareBreakpoint.r32.setComponentOffset(0x5034); - for(int i = 0; i < 114; i++) + for(int i = 0; i < 4; i++) { reserved_20536[i].setComponentOffset(0x5038 + (i * 4)); } + RxRiscLastBranchAddress.r32.setComponentOffset(0x5048); + for(int i = 0; i < 109; i++) + { + reserved_20556[i].setComponentOffset(0x504c + (i * 4)); + } RxRiscRegister0.r32.setComponentOffset(0x5200); RxRiscRegister1.r32.setComponentOffset(0x5204); RxRiscRegister2.r32.setComponentOffset(0x5208); @@ -10152,21 +10321,33 @@ typedef struct DEVICE_t { } RxRiscMode.print(); RxRiscStatus.print(); - for(int i = 0; i < 5; i++) + RxRiscEventMask.print(); + for(int i = 0; i < 4; i++) { - reserved_20488[i].print(); + reserved_20492[i].print(); } RxRiscProgramCounter.print(); RxRiscCurrentInstruction.print(); - for(int i = 0; i < 4; i++) + for(int i = 0; i < 1; i++) { reserved_20516[i].print(); } + RxRiscInterruptEnable.print(); + RxRiscInterruptVector.print(); + for(int i = 0; i < 1; i++) + { + reserved_20528[i].print(); + } RxRiscHardwareBreakpoint.print(); - for(int i = 0; i < 114; i++) + for(int i = 0; i < 4; i++) { reserved_20536[i].print(); } + RxRiscLastBranchAddress.print(); + for(int i = 0; i < 109; i++) + { + reserved_20556[i].print(); + } RxRiscRegister0.print(); RxRiscRegister1.print(); RxRiscRegister2.print(); diff --git a/ipxact/DEVICE.xml b/ipxact/DEVICE.xml index f6134c2..f47ea9a 100644 --- a/ipxact/DEVICE.xml +++ b/ipxact/DEVICE.xml @@ -2911,6 +2911,14 @@ </ipxact:field> </ipxact:register> <ipxact:register> + <ipxact:name>RX_RISC_EVENT_MASK</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x5008</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> <ipxact:name>RX_RISC_PROGRAM_COUNTER</ipxact:name> <ipxact:description>The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored.</ipxact:description> <ipxact:addressOffset>0x501c</ipxact:addressOffset> @@ -2920,13 +2928,29 @@ </ipxact:register> <ipxact:register> <ipxact:name>RX_RISC_CURRENT_INSTRUCTION</ipxact:name> - <ipxact:description>This undocumented register contains the current word located at the program counter address loaded in </ipxact:description> + <ipxact:description>This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed.</ipxact:description> <ipxact:addressOffset>0x5020</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> <ipxact:size>32</ipxact:size> <ipxact:volatile>true</ipxact:volatile> </ipxact:register> <ipxact:register> + <ipxact:name>RX_RISC_INTERRUPT_ENABLE</ipxact:name> + <ipxact:description>Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero.</ipxact:description> + <ipxact:addressOffset>0x5028</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RX_RISC_INTERRUPT_VECTOR</ipxact:name> + <ipxact:description>This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input.</ipxact:description> + <ipxact:addressOffset>0x502c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> <ipxact:name>RX_RISC_HARDWARE_BREAKPOINT</ipxact:name> <ipxact:description>This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit.</ipxact:description> <ipxact:addressOffset>0x5034</ipxact:addressOffset> @@ -2935,6 +2959,40 @@ <ipxact:volatile>true</ipxact:volatile> </ipxact:register> <ipxact:register> + <ipxact:name>RX_RISC_LAST_BRANCH_ADDRESS</ipxact:name> + <ipxact:description>This register indicates that address and branch type of the last branch that was taken. This register is for debug use only.</ipxact:description> + <ipxact:addressOffset>0x5048</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Type</ipxact:name> + <ipxact:description>This indicates the jump or branch type.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + <ipxact:enumeratedValues> + <ipxact:enumeratedValue> + <ipxact:name>Jump</ipxact:name> + <ipxact:description>4 bytes must be subtracted from the LBA value to determine the actual address of the branch instruction that caused this register to load.</ipxact:description> + <ipxact:value>0</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Branch</ipxact:name> + <ipxact:value>1</ipxact:value> + <ipxact:description>8 bytes must be subtracted from the LBA value to determine the actual address of the branch instruction that caused this register to load.</ipxact:description> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + <ipxact:field> + <ipxact:name>Last Branch Address</ipxact:name> + <ipxact:description>This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value.</ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>30</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> <ipxact:name>RX_RISC_REGISTER_0</ipxact:name> <ipxact:description>$zero (R0)</ipxact:description> <ipxact:addressOffset>0x5200</ipxact:addressOffset> diff --git a/simulator/APE_DEVICE.cpp b/simulator/APE_DEVICE.cpp index 5a03f5a..8d6318b 100644 --- a/simulator/APE_DEVICE.cpp +++ b/simulator/APE_DEVICE.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -189,12 +189,20 @@ void init_APE_DEVICE(void) /** @brief Bitmap for @ref DEVICE_t.RxRiscStatus. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscEventMask. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ /** @brief Bitmap for @ref DEVICE_t.RxRiscCurrentInstruction. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptEnable. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptVector. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscLastBranchAddress. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister1. */ diff --git a/simulator/APE_DEVICE1.cpp b/simulator/APE_DEVICE1.cpp index 55b9fe9..13b1873 100644 --- a/simulator/APE_DEVICE1.cpp +++ b/simulator/APE_DEVICE1.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -189,12 +189,20 @@ void init_APE_DEVICE1(void) /** @brief Bitmap for @ref DEVICE1_t.RxRiscStatus. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscEventMask. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscProgramCounter. */ /** @brief Bitmap for @ref DEVICE1_t.RxRiscCurrentInstruction. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscInterruptEnable. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscInterruptVector. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscHardwareBreakpoint. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscLastBranchAddress. */ + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister0. */ /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister1. */ diff --git a/simulator/APE_DEVICE1_sim.cpp b/simulator/APE_DEVICE1_sim.cpp index 0754d43..21256d1 100644 --- a/simulator/APE_DEVICE1_sim.cpp +++ b/simulator/APE_DEVICE1_sim.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -368,6 +368,10 @@ void init_APE_DEVICE1_sim(void *arg0) DEVICE1.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE1.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscEventMask. */ + DEVICE1.RxRiscEventMask.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscEventMask.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscProgramCounter. */ DEVICE1.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE1.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); @@ -376,10 +380,22 @@ void init_APE_DEVICE1_sim(void *arg0) DEVICE1.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE1.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscInterruptEnable. */ + DEVICE1.RxRiscInterruptEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscInterruptEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscInterruptVector. */ + DEVICE1.RxRiscInterruptVector.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscInterruptVector.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscHardwareBreakpoint. */ DEVICE1.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE1.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscLastBranchAddress. */ + DEVICE1.RxRiscLastBranchAddress.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscLastBranchAddress.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister0. */ DEVICE1.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE1.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); diff --git a/simulator/APE_DEVICE2.cpp b/simulator/APE_DEVICE2.cpp index 7568372..34786f9 100644 --- a/simulator/APE_DEVICE2.cpp +++ b/simulator/APE_DEVICE2.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -189,12 +189,20 @@ void init_APE_DEVICE2(void) /** @brief Bitmap for @ref DEVICE2_t.RxRiscStatus. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscEventMask. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscProgramCounter. */ /** @brief Bitmap for @ref DEVICE2_t.RxRiscCurrentInstruction. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscInterruptEnable. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscInterruptVector. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscHardwareBreakpoint. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscLastBranchAddress. */ + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister0. */ /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister1. */ diff --git a/simulator/APE_DEVICE2_sim.cpp b/simulator/APE_DEVICE2_sim.cpp index c1e7143..68e137c 100644 --- a/simulator/APE_DEVICE2_sim.cpp +++ b/simulator/APE_DEVICE2_sim.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -368,6 +368,10 @@ void init_APE_DEVICE2_sim(void *arg0) DEVICE2.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE2.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscEventMask. */ + DEVICE2.RxRiscEventMask.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscEventMask.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscProgramCounter. */ DEVICE2.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE2.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); @@ -376,10 +380,22 @@ void init_APE_DEVICE2_sim(void *arg0) DEVICE2.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE2.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscInterruptEnable. */ + DEVICE2.RxRiscInterruptEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscInterruptEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscInterruptVector. */ + DEVICE2.RxRiscInterruptVector.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscInterruptVector.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscHardwareBreakpoint. */ DEVICE2.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE2.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscLastBranchAddress. */ + DEVICE2.RxRiscLastBranchAddress.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscLastBranchAddress.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister0. */ DEVICE2.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE2.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); diff --git a/simulator/APE_DEVICE3.cpp b/simulator/APE_DEVICE3.cpp index 5523447..1835503 100644 --- a/simulator/APE_DEVICE3.cpp +++ b/simulator/APE_DEVICE3.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -189,12 +189,20 @@ void init_APE_DEVICE3(void) /** @brief Bitmap for @ref DEVICE3_t.RxRiscStatus. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscEventMask. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscProgramCounter. */ /** @brief Bitmap for @ref DEVICE3_t.RxRiscCurrentInstruction. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscInterruptEnable. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscInterruptVector. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscHardwareBreakpoint. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscLastBranchAddress. */ + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister0. */ /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister1. */ diff --git a/simulator/APE_DEVICE3_sim.cpp b/simulator/APE_DEVICE3_sim.cpp index ba003f2..28d9492 100644 --- a/simulator/APE_DEVICE3_sim.cpp +++ b/simulator/APE_DEVICE3_sim.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -368,6 +368,10 @@ void init_APE_DEVICE3_sim(void *arg0) DEVICE3.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE3.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscEventMask. */ + DEVICE3.RxRiscEventMask.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscEventMask.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscProgramCounter. */ DEVICE3.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE3.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); @@ -376,10 +380,22 @@ void init_APE_DEVICE3_sim(void *arg0) DEVICE3.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE3.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscInterruptEnable. */ + DEVICE3.RxRiscInterruptEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscInterruptEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscInterruptVector. */ + DEVICE3.RxRiscInterruptVector.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscInterruptVector.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscHardwareBreakpoint. */ DEVICE3.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE3.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscLastBranchAddress. */ + DEVICE3.RxRiscLastBranchAddress.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscLastBranchAddress.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister0. */ DEVICE3.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE3.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); diff --git a/simulator/APE_DEVICE_sim.cpp b/simulator/APE_DEVICE_sim.cpp index 7593ccd..bbc715c 100644 --- a/simulator/APE_DEVICE_sim.cpp +++ b/simulator/APE_DEVICE_sim.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -368,6 +368,10 @@ void init_APE_DEVICE_sim(void *arg0) DEVICE.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscEventMask. */ + DEVICE.RxRiscEventMask.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscEventMask.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ DEVICE.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); @@ -376,10 +380,22 @@ void init_APE_DEVICE_sim(void *arg0) DEVICE.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptEnable. */ + DEVICE.RxRiscInterruptEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscInterruptEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptVector. */ + DEVICE.RxRiscInterruptVector.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscInterruptVector.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ DEVICE.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscLastBranchAddress. */ + DEVICE.RxRiscLastBranchAddress.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscLastBranchAddress.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ DEVICE.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); DEVICE.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); diff --git a/simulator/bcm5719_DEVICE.cpp b/simulator/bcm5719_DEVICE.cpp index ad09748..9f5f0c1 100644 --- a/simulator/bcm5719_DEVICE.cpp +++ b/simulator/bcm5719_DEVICE.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -189,12 +189,20 @@ void init_bcm5719_DEVICE(void) /** @brief Bitmap for @ref DEVICE_t.RxRiscStatus. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscEventMask. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ /** @brief Bitmap for @ref DEVICE_t.RxRiscCurrentInstruction. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptEnable. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptVector. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscLastBranchAddress. */ + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister1. */ diff --git a/simulator/bcm5719_DEVICE_sim.cpp b/simulator/bcm5719_DEVICE_sim.cpp index 05aa189..e23bb24 100644 --- a/simulator/bcm5719_DEVICE_sim.cpp +++ b/simulator/bcm5719_DEVICE_sim.cpp @@ -10,7 +10,7 @@ /// //////////////////////////////////////////////////////////////////////////////// /// -/// @copyright Copyright (c) 2018, Evan Lojewski +/// @copyright Copyright (c) 2020, Evan Lojewski /// @cond /// /// All rights reserved. @@ -516,10 +516,14 @@ void init_bcm5719_DEVICE_sim(void *base) DEVICE.RxRiscStatus.r32.installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.RxRiscStatus.r32.installWriteCallback(write_to_ram, (uint8_t *)base); - for(int i = 0; i < 5; i++) + /** @brief Bitmap for @ref DEVICE_t.RxRiscEventMask. */ + DEVICE.RxRiscEventMask.r32.installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.RxRiscEventMask.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + + for(int i = 0; i < 4; i++) { - DEVICE.reserved_20488[i].installReadCallback(read_from_ram, (uint8_t *)base); - DEVICE.reserved_20488[i].installWriteCallback(write_to_ram, (uint8_t *)base); + DEVICE.reserved_20492[i].installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.reserved_20492[i].installWriteCallback(write_to_ram, (uint8_t *)base); } /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ DEVICE.RxRiscProgramCounter.r32.installReadCallback(read_from_ram, (uint8_t *)base); @@ -529,20 +533,42 @@ void init_bcm5719_DEVICE_sim(void *base) DEVICE.RxRiscCurrentInstruction.r32.installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.RxRiscCurrentInstruction.r32.installWriteCallback(write_to_ram, (uint8_t *)base); - for(int i = 0; i < 4; i++) + for(int i = 0; i < 1; i++) { DEVICE.reserved_20516[i].installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.reserved_20516[i].installWriteCallback(write_to_ram, (uint8_t *)base); } + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptEnable. */ + DEVICE.RxRiscInterruptEnable.r32.installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.RxRiscInterruptEnable.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscInterruptVector. */ + DEVICE.RxRiscInterruptVector.r32.installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.RxRiscInterruptVector.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + + for(int i = 0; i < 1; i++) + { + DEVICE.reserved_20528[i].installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.reserved_20528[i].installWriteCallback(write_to_ram, (uint8_t *)base); + } /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ DEVICE.RxRiscHardwareBreakpoint.r32.installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.RxRiscHardwareBreakpoint.r32.installWriteCallback(write_to_ram, (uint8_t *)base); - for(int i = 0; i < 114; i++) + for(int i = 0; i < 4; i++) { DEVICE.reserved_20536[i].installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.reserved_20536[i].installWriteCallback(write_to_ram, (uint8_t *)base); } + /** @brief Bitmap for @ref DEVICE_t.RxRiscLastBranchAddress. */ + DEVICE.RxRiscLastBranchAddress.r32.installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.RxRiscLastBranchAddress.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + + for(int i = 0; i < 109; i++) + { + DEVICE.reserved_20556[i].installReadCallback(read_from_ram, (uint8_t *)base); + DEVICE.reserved_20556[i].installWriteCallback(write_to_ram, (uint8_t *)base); + } /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ DEVICE.RxRiscRegister0.r32.installReadCallback(read_from_ram, (uint8_t *)base); DEVICE.RxRiscRegister0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); |
