diff options
91 files changed, 14642 insertions, 828 deletions
diff --git a/ape/CMakeLists.txt b/ape/CMakeLists.txt index fe68622..0159e1d 100644 --- a/ape/CMakeLists.txt +++ b/ape/CMakeLists.txt @@ -50,16 +50,14 @@ set(LINKER_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/ape.ld") arm_add_executable(${PROJECT_NAME} main.c vectors.c - rx_from_network.c rmu.c ) arm_linker_script(${PROJECT_NAME} ${LINKER_SCRIPT}) -target_link_libraries(${PROJECT_NAME} NVRam-arm MII-arm APE-arm ) +target_link_libraries(${PROJECT_NAME} NVRam-arm MII-arm APE-arm Network-arm NCSI-arm) target_link_libraries(${PROJECT_NAME} bcm5719-arm) target_compile_options(${PROJECT_NAME} PRIVATE -nodefaultlibs) - # Simulator add_executable # simulator_add_executable(sim-${PROJECT_NAME} # init_hw.c @@ -45,8 +45,6 @@ #ifndef APE_H #define APE_H -void initRxFromNetwork(void); void initRMU(void); - #endif /* APE_H */ @@ -27,7 +27,7 @@ SECTIONS .stack . (NOLOAD) : ALIGN(4) SUBALIGN(4) { _fstack = .; - _estack = 00118000; + _estack = 0x00118000; } @@ -44,58 +44,123 @@ #include "ape.h" +#include <APE_APE.h> +#include <APE_APE_PERI.h> +#include <APE_RX_PORT.h> #include <APE_SHM.h> +#include <Ethernet.h> +#include <NCSI.h> +#include <Network.h> +#include <types.h> -void __attribute__((noreturn)) loaderLoop(void) +void handleCommand(void) { - // Update SHM.Sig to signal ready. - SHM.SegSig.bits.Sig = SHM_SEG_SIG_SIG_LOADER; - SHM.FwStatus.bits.Ready = 1; - - for(;;) + uint32_t command = SHM.LoaderCommand.bits.Command; + if (!command) { - uint32_t command = SHM.LoaderCommand.bits.Command; - if(!command) continue; + return; + } + + uint32_t arg0 = SHM.LoaderArg0.r32; + uint32_t arg1 = SHM.LoaderArg1.r32; - uint32_t arg0 = SHM.LoaderArg0.r32; - uint32_t arg1 = SHM.LoaderArg1.r32; + switch (command) + { + default: + break; - switch(command) + case SHM_LOADER_COMMAND_COMMAND_READ_MEM: + { + // Read word address specified in arg0 + uint32_t *addr = ((void *)arg0); + SHM.LoaderArg0.r32 = *addr; + break; + } + case SHM_LOADER_COMMAND_COMMAND_WRITE_MEM: + { + // Write word address specified in arg0 with arg1 + uint32_t *addr = ((void *)arg0); + *addr = arg1; + break; + } + case SHM_LOADER_COMMAND_COMMAND_CALL: { - default: - break; + // call address specified in arg0. + void (*function)(uint32_t) = ((void *)arg0); + function(arg1); + break; + } + } + + // Mark command as handled. + SHM.LoaderCommand.bits.Command = 0; +} + +void handleBMCPacket(void) +{ + uint32_t buffer[1024]; - case SHM_LOADER_COMMAND_COMMAND_READ_MEM: + RegAPE_PERIBmcToNcRxStatus_t stat; + stat.r32 = APE_PERI.BmcToNcRxStatus.r32; + + if (stat.bits.New) + { + if (stat.bits.Bad) + { + // TODO: ACK bad packet. + APE_PERI.BmcToNcRxControl.bits.ResetBad = 1; + while (APE_PERI.BmcToNcRxControl.bits.ResetBad) { - // Read word address specified in arg0 - uint32_t* addr = ((void*)arg0); - SHM.LoaderArg0.r32 = *addr; - break; + // Wait } - case SHM_LOADER_COMMAND_COMMAND_WRITE_MEM: + } + else + { + int32_t bytes = stat.bits.PacketLength; + if (!stat.bits.Passthru) { - // Write word address specified in arg0 with arg1 - uint32_t* addr = ((void*)arg0); - *addr = arg1; - break; + // stat.print(); + int32_t words = DIVIDE_RND_UP(bytes, sizeof(uint32_t)); + int i = 0; + while (words--) + { + uint32_t word = (APE_PERI.BmcToNcReadBuffer.r32); + buffer[i] = word; + i++; + } + + NetworkFrame_t *frame = ((NetworkFrame_t *)buffer); + + handleNCSIFrame(frame); } - case SHM_LOADER_COMMAND_COMMAND_CALL: + else { - // call address specified in arg0. - void (*function)(uint32_t) = ((void*)arg0); - function(arg1); - break; + // Pass through to network + Network_TX_transmitPassthroughPacket(bytes); } } + } +} - // Mark command as handled. - SHM.LoaderCommand.bits.Command = 0; +void __attribute__((noreturn)) loaderLoop(void) +{ + // Update SHM.Sig to signal ready. + SHM.SegSig.bits.Sig = SHM_SEG_SIG_SIG_LOADER; + SHM.FwStatus.bits.Ready = 1; + + for (;;) + { + handleBMCPacket(); + Network_PassthroughRxPatcket(); + handleCommand(); } } void __attribute__((noreturn)) __start() { - initRxFromNetwork(); + NCSI_init(); + Network_InitTxRx(); initRMU(); + loaderLoop(); }
\ No newline at end of file @@ -46,6 +46,8 @@ #include <APE_APE.h> #include <APE_APE_PERI.h> +#include <APE_DEVICE.h> +#include <Network.h> void initRMU(void) { @@ -57,14 +59,17 @@ void initRMU(void) mode.bits.ICodePIPRdDisable = 1; APE.Mode = mode; - // Optionally, set REG_APE__RMU_CONTROL to RST_RX|RST_TX. This can help unwedge the state machines if you wedged them previously due to a bug in your code. + // Optionally, set REG_APE__RMU_CONTROL to RST_RX|RST_TX. This can help + // unwedge the state machines if you wedged them previously due to a bug in + // your code. RegAPE_PERIRmuControl_t rmuControl; rmuControl.r32 = 0; rmuControl.bits.ResetTX = 1; rmuControl.bits.ResetRX = 1; APE_PERI.RmuControl = rmuControl; - // Now set REG_APE__RMU_CONTROL to AUTO_DRV|RX|TX. Also set bits 19 and 20 (meaning unknown). + // Now set REG_APE__RMU_CONTROL to AUTO_DRV|RX|TX. Also set bits 19 and 20 + // (meaning unknown). rmuControl.r32 = 0; rmuControl.bits.AutoDrv = 1; rmuControl.bits.RX = 1; @@ -72,13 +77,16 @@ void initRMU(void) rmuControl.r32 |= (1 << 19) | (1 << 20); APE_PERI.RmuControl = rmuControl; - // Set REG_APE__BMC_NC_RX_CONTROL to FLOW_CONTROL=0 or 1, HWM=0x240, XON_THRESHOLD=0x201F. - // Note: FLOW_CONTROL=1 enables the hardware to automatically send PAUSE frames to the BMC. tcpdump can detect these, so keeping flow control on gives you a way to detect when the RX state machine has gotten wedged. + // Set REG_APE__BMC_NC_RX_CONTROL to FLOW_CONTROL=0 or 1, HWM=0x240, + // XON_THRESHOLD=0x201F. Note: FLOW_CONTROL=1 enables the hardware to + // automatically send PAUSE frames to the BMC. tcpdump can detect these, so + // keeping flow control on gives you a way to detect when the RX state + // machine has gotten wedged. RegAPE_PERIBmcToNcRxControl_t rxControl; rxControl.r32 = 0; rxControl.bits.FlowControl = 1; rxControl.bits.HWM = 0x240; - rxControl.r32 |= (0x201F << 11) ; /* XON_THRESHOLD */ + rxControl.r32 |= (0x201F << 11); /* XON_THRESHOLD */ APE_PERI.BmcToNcRxControl = rxControl; // Set REG_APE__NC_BMC_TX_CONTROL to 0. @@ -87,27 +95,14 @@ void initRMU(void) APE_PERI.BmcToNcTxControl = txControl; // Set all eight REG_APE__BMC_NC_RX_SRC_MAC_MATCHN_{HIGH,LOW} to zero. - APE_PERI.BmcToNcSourceMacMatch0High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch0Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch1High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch1Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch2High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch2Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch3High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch3Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch4High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch4Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch5High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch5Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch6High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch6Low.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch7High.r32 = 0; - APE_PERI.BmcToNcSourceMacMatch7Low.r32 = 0; + Network_SetMACAddr(0, 0, 1, true); - // Set REG_APE__ARB_CONTROL as desired. Suggest PACKAGE_ID=0, TKNREL=0x14, START, and setting unknown bit 26 to 1. + // Set REG_APE__ARB_CONTROL as desired. Suggest PACKAGE_ID=0, TKNREL=0x14, + // START, and setting unknown bit 26 to 1. RegAPE_PERIArbControl_t arbControl; arbControl.r32 = (1 << 26); - arbControl.bits.PackageID = 0; /* TODO: allow to be configured as per NC-SI spec. */ + arbControl.bits.PackageID = + 0; /* TODO: allow to be configured as per NC-SI spec. */ arbControl.bits.Start = 1; arbControl.bits.TKNREL = 0x14; APE_PERI.ArbControl = arbControl; diff --git a/cmake/arm.cmake b/cmake/arm.cmake index b27e1cf..8e360bc 100644 --- a/cmake/arm.cmake +++ b/cmake/arm.cmake @@ -42,7 +42,7 @@ ### @endcond ################################################################################ -SET(ARM_COMPILE_OPTIONS -nostdlib -nodefaultlibs -fomit-frame-pointer -target thumbv7-none-eabi -mcpu=cortex-m3 -mfloat-abi=soft ) +SET(ARM_COMPILE_OPTIONS -nostdlib -nodefaultlibs -fomit-frame-pointer -target thumbv7-none-eabi -mcpu=cortex-m3 -mfloat-abi=soft -fno-builtin) SET(ARM_LINK_OPTIONS --gc-sections) # SET(CMAKE_EXE_LINKER_FLAGS -static) diff --git a/include/APE_APE.h b/include/APE_APE.h index 65f9ef3..b1e4238 100644 --- a/include/APE_APE.h +++ b/include/APE_APE.h @@ -118,6 +118,14 @@ typedef uint32_t APE_APE_H_uint32_t; #define APE_MODE_SWAP_ARB_DWORD_MASK 0x800u #define GET_APE_MODE_SWAP_ARB_DWORD(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_APE_MODE_SWAP_ARB_DWORD(__val__) (((__val__) << 11u) & 0x800u) +#define APE_MODE_CHANNEL_0_ENABLE_SHIFT 14u +#define APE_MODE_CHANNEL_0_ENABLE_MASK 0x4000u +#define GET_APE_MODE_CHANNEL_0_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_APE_MODE_CHANNEL_0_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) +#define APE_MODE_CHANNEL_2_ENABLE_SHIFT 15u +#define APE_MODE_CHANNEL_2_ENABLE_MASK 0x8000u +#define GET_APE_MODE_CHANNEL_2_ENABLE(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_APE_MODE_CHANNEL_2_ENABLE(__val__) (((__val__) << 15u) & 0x8000u) #define APE_MODE_MEMORY_ECC_SHIFT 18u #define APE_MODE_MEMORY_ECC_MASK 0x40000u #define GET_APE_MODE_MEMORY_ECC(__reg__) (((__reg__) & 0x40000) >> 18u) @@ -126,6 +134,14 @@ typedef uint32_t APE_APE_H_uint32_t; #define APE_MODE_ICODE_PIP_RD_DISABLE_MASK 0x80000u #define GET_APE_MODE_ICODE_PIP_RD_DISABLE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_APE_MODE_ICODE_PIP_RD_DISABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define APE_MODE_CHANNEL_1_ENABLE_SHIFT 30u +#define APE_MODE_CHANNEL_1_ENABLE_MASK 0x40000000u +#define GET_APE_MODE_CHANNEL_1_ENABLE(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_APE_MODE_CHANNEL_1_ENABLE(__val__) (((__val__) << 30u) & 0x40000000u) +#define APE_MODE_CHANNEL_3_ENABLE_SHIFT 31u +#define APE_MODE_CHANNEL_3_ENABLE_MASK 0x80000000u +#define GET_APE_MODE_CHANNEL_3_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_APE_MODE_CHANNEL_3_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.Mode. */ typedef register_container RegAPEMode_t { @@ -159,22 +175,42 @@ typedef register_container RegAPEMode_t { /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, SwapARBdword, 11, 1) /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_17_12, 12, 6) + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_13_12, 12, 2) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel0Enable, 14, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel2Enable, 15, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_17_16, 16, 2) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, MemoryECC, 18, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, ICodePIPRdDisable, 19, 1) /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_20, 20, 12) + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_29_20, 20, 10) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel1Enable, 30, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel3Enable, 31, 1) #elif defined(__BIG_ENDIAN__) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel3Enable, 31, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel1Enable, 30, 1) /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_20, 20, 12) + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_29_20, 20, 10) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, ICodePIPRdDisable, 19, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, MemoryECC, 18, 1) /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_17_12, 12, 6) + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_17_16, 16, 2) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel2Enable, 15, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Channel0Enable, 14, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_13_12, 12, 2) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, SwapARBdword, 11, 1) /** @brief Padding */ @@ -232,10 +268,18 @@ typedef register_container RegAPEMode_t { bits.SwapATBdword.setName("SwapATBdword"); bits.SwapARBdword.setBaseRegister(&r32); bits.SwapARBdword.setName("SwapARBdword"); + bits.Channel0Enable.setBaseRegister(&r32); + bits.Channel0Enable.setName("Channel0Enable"); + bits.Channel2Enable.setBaseRegister(&r32); + bits.Channel2Enable.setName("Channel2Enable"); bits.MemoryECC.setBaseRegister(&r32); bits.MemoryECC.setName("MemoryECC"); bits.ICodePIPRdDisable.setBaseRegister(&r32); bits.ICodePIPRdDisable.setName("ICodePIPRdDisable"); + bits.Channel1Enable.setBaseRegister(&r32); + bits.Channel1Enable.setName("Channel1Enable"); + bits.Channel3Enable.setBaseRegister(&r32); + bits.Channel3Enable.setName("Channel3Enable"); } RegAPEMode_t& operator=(const RegAPEMode_t& other) { @@ -489,6 +533,10 @@ typedef register_container RegAPEEvent_t { #define APE_RXBUFOFFSET_FUNC0_VALID_MASK 0x40000000u #define GET_APE_RXBUFOFFSET_FUNC0_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_APE_RXBUFOFFSET_FUNC0_VALID(__val__) (((__val__) << 30u) & 0x40000000u) +#define APE_RXBUFOFFSET_FUNC0_FINISHED_SHIFT 31u +#define APE_RXBUFOFFSET_FUNC0_FINISHED_MASK 0x80000000u +#define GET_APE_RXBUFOFFSET_FUNC0_FINISHED(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_APE_RXBUFOFFSET_FUNC0_FINISHED(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.RxbufoffsetFunc0. */ typedef register_container RegAPERxbufoffsetFunc0_t { @@ -509,11 +557,11 @@ typedef register_container RegAPERxbufoffsetFunc0_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Finished, 31, 1) #elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Finished, 31, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) /** @brief */ @@ -553,6 +601,8 @@ typedef register_container RegAPERxbufoffsetFunc0_t { bits.Count.setName("Count"); bits.Valid.setBaseRegister(&r32); bits.Valid.setName("Valid"); + bits.Finished.setBaseRegister(&r32); + bits.Finished.setName("Finished"); } RegAPERxbufoffsetFunc0_t& operator=(const RegAPERxbufoffsetFunc0_t& other) { @@ -670,9 +720,13 @@ typedef register_container RegAPERxbufoffsetFunc1_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc0. */ typedef register_container RegAPETxToNetDoorbellFunc0_t { @@ -686,10 +740,18 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -715,6 +777,8 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc0_t& operator=(const RegAPETxToNetDoorbellFunc0_t& other) { @@ -724,6 +788,84 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { #endif /* CXX_SIMULATOR */ } RegAPETxToNetDoorbellFunc0_t; +#define REG_APE_TX_STATE0 ((volatile APE_APE_H_uint32_t*)0x60200020) /* APE TX Status. */ +#define APE_TX_STATE0_TAIL_SHIFT 0u +#define APE_TX_STATE0_TAIL_MASK 0xfffu +#define GET_APE_TX_STATE0_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) +#define SET_APE_TX_STATE0_TAIL(__val__) (((__val__) << 0u) & 0xfffu) +#define APE_TX_STATE0_HEAD_SHIFT 12u +#define APE_TX_STATE0_HEAD_MASK 0xfff000u +#define GET_APE_TX_STATE0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) +#define SET_APE_TX_STATE0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_TX_STATE0_TXERROR_SHIFT 24u +#define APE_TX_STATE0_TXERROR_MASK 0x1000000u +#define GET_APE_TX_STATE0_TXERROR(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_TX_STATE0_TXERROR(__val__) (((__val__) << 24u) & 0x1000000u) +#define APE_TX_STATE0_ERROR_CODE_SHIFT 25u +#define APE_TX_STATE0_ERROR_CODE_MASK 0xe000000u +#define GET_APE_TX_STATE0_ERROR_CODE(__reg__) (((__reg__) & 0xe000000) >> 25u) +#define SET_APE_TX_STATE0_ERROR_CODE(__val__) (((__val__) << 25u) & 0xe000000u) + +/** @brief Register definition for @ref APE_t.TxState0. */ +typedef register_container RegAPETxState0_t { + /** @brief 32bit direct register access. */ + APE_APE_H_uint32_t r32; + + BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXError, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, ErrorCode, 25, 3) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_28, 28, 4) +#elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_28, 28, 4) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, ErrorCode, 25, 3) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXError, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) +#else +#error Unknown Endian +#endif + BITFIELD_END(APE_APE_H_uint32_t, bits) +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxState0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxState0_t() + { + /** @brief constructor for @ref APE_t.TxState0. */ + r32.setName("TxState0"); + bits.Tail.setBaseRegister(&r32); + bits.Tail.setName("Tail"); + bits.Head.setBaseRegister(&r32); + bits.Head.setName("Head"); + bits.TXError.setBaseRegister(&r32); + bits.TXError.setName("TXError"); + bits.ErrorCode.setBaseRegister(&r32); + bits.ErrorCode.setName("ErrorCode"); + } + RegAPETxState0_t& operator=(const RegAPETxState0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxState0_t; + #define REG_APE_MODE_2 ((volatile APE_APE_H_uint32_t*)0x6020002c) /* Expansion for MODE */ /** @brief Register definition for @ref APE_t.Mode2. */ typedef register_container RegAPEMode2_t { @@ -1040,6 +1182,10 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define APE_RX_POOL_RETIRE_0_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_0_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_0_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_0_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_0_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_0_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_0_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_0_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -1065,8 +1211,8 @@ typedef register_container RegAPERxPoolRetire0_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -1080,8 +1226,8 @@ typedef register_container RegAPERxPoolRetire0_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -1105,6 +1251,8 @@ typedef register_container RegAPERxPoolRetire0_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -1127,6 +1275,10 @@ typedef register_container RegAPERxPoolRetire0_t { #define APE_RX_POOL_RETIRE_1_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_1_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_1_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_1_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_1_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_1_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_1_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_1_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -1152,8 +1304,8 @@ typedef register_container RegAPERxPoolRetire1_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -1167,8 +1319,8 @@ typedef register_container RegAPERxPoolRetire1_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -1192,6 +1344,8 @@ typedef register_container RegAPERxPoolRetire1_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -1396,6 +1550,56 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { #endif /* CXX_SIMULATOR */ } RegAPETxToNetBufferAllocator0_t; +#define REG_APE_TX_TO_NET_BUFFER_RETURN_0 ((volatile APE_APE_H_uint32_t*)0x60200094) /* */ +/** @brief Register definition for @ref APE_t.TxToNetBufferReturn0. */ +typedef register_container RegAPETxToNetBufferReturn0_t { + /** @brief 32bit direct register access. */ + APE_APE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxToNetBufferReturn0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxToNetBufferReturn0_t() + { + /** @brief constructor for @ref APE_t.TxToNetBufferReturn0. */ + r32.setName("TxToNetBufferReturn0"); + } + RegAPETxToNetBufferReturn0_t& operator=(const RegAPETxToNetBufferReturn0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxToNetBufferReturn0_t; + +#define REG_APE_TX_TO_NET_BUFFER_RING_0 ((volatile APE_APE_H_uint32_t*)0x60200098) /* */ +/** @brief Register definition for @ref APE_t.TxToNetBufferRing0. */ +typedef register_container RegAPETxToNetBufferRing0_t { + /** @brief 32bit direct register access. */ + APE_APE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxToNetBufferRing0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxToNetBufferRing0_t() + { + /** @brief constructor for @ref APE_t.TxToNetBufferRing0. */ + r32.setName("TxToNetBufferRing0"); + } + RegAPETxToNetBufferRing0_t& operator=(const RegAPETxToNetBufferRing0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxToNetBufferRing0_t; + #define REG_APE_TICK_1MHZ ((volatile APE_APE_H_uint32_t*)0x602000a8) /* Unknown, monotonically increasing value. Increases at a rate of 1MHz. */ /** @brief Register definition for @ref APE_t.Tick1mhz. */ typedef register_container RegAPETick1mhz_t { @@ -2120,9 +2324,13 @@ typedef register_container RegAPETxToNetBufferAllocator1_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc1. */ typedef register_container RegAPETxToNetDoorbellFunc1_t { @@ -2136,10 +2344,18 @@ typedef register_container RegAPETxToNetDoorbellFunc1_t { /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2165,6 +2381,8 @@ typedef register_container RegAPETxToNetDoorbellFunc1_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc1_t& operator=(const RegAPETxToNetDoorbellFunc1_t& other) { @@ -2282,9 +2500,13 @@ typedef register_container RegAPERxbufoffsetFunc2_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc2. */ typedef register_container RegAPETxToNetDoorbellFunc2_t { @@ -2298,10 +2520,18 @@ typedef register_container RegAPETxToNetDoorbellFunc2_t { /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2327,6 +2557,8 @@ typedef register_container RegAPETxToNetDoorbellFunc2_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc2_t& operator=(const RegAPETxToNetDoorbellFunc2_t& other) { @@ -2461,6 +2693,10 @@ typedef register_container RegAPERxPoolModeStatus2_t { #define APE_RX_POOL_RETIRE_2_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_2_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_2_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_2_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_2_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_2_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_2_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_2_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -2486,8 +2722,8 @@ typedef register_container RegAPERxPoolRetire2_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -2501,8 +2737,8 @@ typedef register_container RegAPERxPoolRetire2_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2526,6 +2762,8 @@ typedef register_container RegAPERxPoolRetire2_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -2838,9 +3076,13 @@ typedef register_container RegAPERxbufoffsetFunc3_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc3. */ typedef register_container RegAPETxToNetDoorbellFunc3_t { @@ -2854,10 +3096,18 @@ typedef register_container RegAPETxToNetDoorbellFunc3_t { /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2883,6 +3133,8 @@ typedef register_container RegAPETxToNetDoorbellFunc3_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc3_t& operator=(const RegAPETxToNetDoorbellFunc3_t& other) { @@ -3017,6 +3269,10 @@ typedef register_container RegAPERxPoolModeStatus3_t { #define APE_RX_POOL_RETIRE_3_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_3_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_3_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_3_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_3_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_3_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_3_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_3_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -3042,8 +3298,8 @@ typedef register_container RegAPERxPoolRetire3_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -3057,8 +3313,8 @@ typedef register_container RegAPERxPoolRetire3_t { BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -3082,6 +3338,8 @@ typedef register_container RegAPERxPoolRetire3_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -3312,8 +3570,11 @@ typedef struct APE_t { /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ RegAPETxToNetDoorbellFunc0_t TxToNetDoorbellFunc0; + /** @brief APE TX Status. */ + RegAPETxState0_t TxState0; + /** @brief Reserved bytes to pad out data structure. */ - APE_APE_H_uint32_t reserved_32[3]; + APE_APE_H_uint32_t reserved_36[2]; /** @brief Expansion for MODE */ RegAPEMode2_t Mode2; @@ -3351,8 +3612,14 @@ typedef struct APE_t { /** @brief */ RegAPETxToNetBufferAllocator0_t TxToNetBufferAllocator0; + /** @brief */ + RegAPETxToNetBufferReturn0_t TxToNetBufferReturn0; + + /** @brief */ + RegAPETxToNetBufferRing0_t TxToNetBufferRing0; + /** @brief Reserved bytes to pad out data structure. */ - APE_APE_H_uint32_t reserved_148[5]; + APE_APE_H_uint32_t reserved_156[3]; /** @brief Unknown, monotonically increasing value. Increases at a rate of 1MHz. */ RegAPETick1mhz_t Tick1mhz; @@ -3475,6 +3742,7 @@ typedef struct APE_t { RxbufoffsetFunc0.r32.setComponentOffset(0x14); RxbufoffsetFunc1.r32.setComponentOffset(0x18); TxToNetDoorbellFunc0.r32.setComponentOffset(0x1c); + TxState0.r32.setComponentOffset(0x20); Mode2.r32.setComponentOffset(0x2c); Status2.r32.setComponentOffset(0x30); LockGrantObsolete.r32.setComponentOffset(0x4c); @@ -3484,6 +3752,8 @@ typedef struct APE_t { RxPoolRetire1.r32.setComponentOffset(0x88); TxToNetPoolModeStatus0.r32.setComponentOffset(0x8c); TxToNetBufferAllocator0.r32.setComponentOffset(0x90); + TxToNetBufferReturn0.r32.setComponentOffset(0x94); + TxToNetBufferRing0.r32.setComponentOffset(0x98); Tick1mhz.r32.setComponentOffset(0xa8); Tick1khz.r32.setComponentOffset(0xac); Tick10hz.r32.setComponentOffset(0xb0); diff --git a/include/APE_APE_PERI.h b/include/APE_APE_PERI.h index bd90ffb..0330dc4 100644 --- a/include/APE_APE_PERI.h +++ b/include/APE_APE_PERI.h @@ -980,10 +980,27 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch6Low_t { } RegAPE_PERIBmcToNcSourceMacMatch6Low_t; #define REG_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH ((volatile APE_APE_PERI_H_uint32_t*)0x60240344) /* Upper four bytes of the MAC */ +#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH_SHIFT 0u +#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH_MASK 0xffffffffu +#define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffffffu) + /** @brief Register definition for @ref APE_PERI_t.BmcToNcSourceMacMatch7High. */ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { /** @brief 32bit direct register access. */ APE_APE_PERI_H_uint32_t r32; + + BITFIELD_BEGIN(APE_APE_PERI_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief Upper four bytes of the MAC */ + BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, High, 0, 32) +#elif defined(__BIG_ENDIAN__) + /** @brief Upper four bytes of the MAC */ + BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, High, 0, 32) +#else +#error Unknown Endian +#endif + BITFIELD_END(APE_APE_PERI_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "BmcToNcSourceMacMatch7High"; } @@ -995,6 +1012,8 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { { /** @brief constructor for @ref APE_PERI_t.BmcToNcSourceMacMatch7High. */ r32.setName("BmcToNcSourceMacMatch7High"); + bits.High.setBaseRegister(&r32); + bits.High.setName("High"); } RegAPE_PERIBmcToNcSourceMacMatch7High_t& operator=(const RegAPE_PERIBmcToNcSourceMacMatch7High_t& other) { @@ -1009,10 +1028,6 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { #define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW_MASK 0xffff0000u #define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW(__val__) (((__val__) << 16u) & 0xffff0000u) -#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH_SHIFT 0u -#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH_MASK 0xffffffffu -#define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref APE_PERI_t.BmcToNcSourceMacMatch7Low. */ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { @@ -1025,11 +1040,7 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, reserved_15_0, 0, 16) /** @brief Lower two bytes of the MAC */ BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, Low, 16, 16) - /** @brief Upper four bytes of the MAC */ - BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, High, 0, 32) #elif defined(__BIG_ENDIAN__) - /** @brief Upper four bytes of the MAC */ - BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, High, 0, 32) /** @brief Lower two bytes of the MAC */ BITFIELD_MEMBER(APE_APE_PERI_H_uint32_t, Low, 16, 16) /** @brief Padding */ @@ -1051,8 +1062,6 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { r32.setName("BmcToNcSourceMacMatch7Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); - bits.High.setBaseRegister(&r32); - bits.High.setName("High"); } RegAPE_PERIBmcToNcSourceMacMatch7Low_t& operator=(const RegAPE_PERIBmcToNcSourceMacMatch7Low_t& other) { diff --git a/include/APE_DEVICE.h b/include/APE_DEVICE.h index 1f4c82b..28835d0 100644 --- a/include/APE_DEVICE.h +++ b/include/APE_DEVICE.h @@ -6636,10 +6636,14 @@ typedef register_container RegDEVICEGrcModeControl_t { } RegDEVICEGrcModeControl_t; #define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE_H_uint32_t*)0xa0046804) /* */ -#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 0u -#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xffffffffu -#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u +#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u +#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u +#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu +#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) +#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) /** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */ typedef register_container RegDEVICEMiscellaneousConfig_t { @@ -6648,11 +6652,19 @@ typedef register_container RegDEVICEMiscellaneousConfig_t { BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) + /** @brief */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 1, 1) /** @brief */ - BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 1, 31) #elif defined(__BIG_ENDIAN__) /** @brief */ - BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 1, 31) + /** @brief */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 1, 1) + /** @brief Padding */ + BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1) #else #error Unknown Endian #endif @@ -6668,6 +6680,8 @@ typedef register_container RegDEVICEMiscellaneousConfig_t { { /** @brief constructor for @ref DEVICE_t.MiscellaneousConfig. */ r32.setName("MiscellaneousConfig"); + bits.GRCReset.setBaseRegister(&r32); + bits.GRCReset.setName("GRCReset"); bits.all.setBaseRegister(&r32); bits.all.setName("all"); } diff --git a/include/APE_DEVICE1.h b/include/APE_DEVICE1.h new file mode 100644 index 0000000..589828c --- /dev/null +++ b/include/APE_DEVICE1.h @@ -0,0 +1,1720 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE1.h +/// +/// @project ape +/// +/// @brief APE_DEVICE1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_DEVICE1_H APE_DEVICE1 */ +/** @addtogroup APE_DEVICE1_H + * @{ + */ +#ifndef APE_DEVICE1_H +#define APE_DEVICE1_H + +#include <stdint.h> +#include "APE_DEVICE.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_DEVICE1_sim(void* base); +void init_APE_DEVICE1(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_DEVICE1_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_DEVICE1_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_DEVICE1_H_uint32_t; +#define APE_DEVICE1_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_DEVICE1_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_DEVICE1_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_DEVICE1_H_uint8_t; +typedef uint16_t APE_DEVICE1_H_uint16_t; +typedef uint32_t APE_DEVICE1_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_DEVICE1_BASE ((volatile void*)0xa0050000) /* Device Registers, function 1 */ +#define REG_DEVICE1_SIZE (sizeof(DEVICE_t)) + +#define REG_DEVICE1_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0050068) /* */ +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u + +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u + +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u +#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) +#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu + + +#define REG_DEVICE1_PCI_STATE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050070) /* */ +#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u +#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u +#define GET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u +#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u +#define GET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_PCI_STATE_VPD_AVAILABLE_SHIFT 7u +#define DEVICE1_PCI_STATE_VPD_AVAILABLE_MASK 0x80u +#define GET_DEVICE1_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_PCI_STATE_FLAT_VIEW_SHIFT 8u +#define DEVICE1_PCI_STATE_FLAT_VIEW_MASK 0x100u +#define GET_DEVICE1_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u +#define DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u +#define GET_DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) +#define SET_DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) +#define DEVICE1_PCI_STATE_CONFIG_RETRY_SHIFT 15u +#define DEVICE1_PCI_STATE_CONFIG_RETRY_MASK 0x8000u +#define GET_DEVICE1_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u +#define DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u +#define GET_DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u +#define DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u +#define GET_DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u +#define DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u +#define GET_DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE1_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u +#define DEVICE1_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u +#define GET_DEVICE1_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE1_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE1_REGISTER_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ +#define REG_DEVICE1_MEMORY_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa005007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ +#define REG_DEVICE1_REGISTER_DATA ((volatile APE_DEVICE1_H_uint32_t*)0xa0050080) /* Register Data at the location pointed by the Register Base Register. */ +#define REG_DEVICE1_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE1_H_uint32_t*)0xa0050088) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE1_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE1_LINK_STATUS_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00500bc) /* PCIe standard register. */ +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u +#define GET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) +#define SET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u + +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u +#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u +#define GET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) +#define SET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) + +#define REG_DEVICE1_APE_MEMORY_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa00500f8) /* APE Memory address to read/write using the APE Memory Data register.. */ +#define REG_DEVICE1_APE_MEMORY_DATA ((volatile APE_DEVICE1_H_uint32_t*)0xa00500fc) /* APE Memory value at the location pointed by the Memory Base Register. */ +#define REG_DEVICE1_EMAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050400) /* */ +#define DEVICE1_EMAC_MODE_GLOBAL_RESET_SHIFT 0u +#define DEVICE1_EMAC_MODE_GLOBAL_RESET_MASK 0x1u +#define GET_DEVICE1_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_EMAC_MODE_HALF_DUPLEX_SHIFT 1u +#define DEVICE1_EMAC_MODE_HALF_DUPLEX_MASK 0x2u +#define GET_DEVICE1_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_EMAC_MODE_PORT_MODE_SHIFT 2u +#define DEVICE1_EMAC_MODE_PORT_MODE_MASK 0xcu +#define GET_DEVICE1_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) +#define SET_DEVICE1_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) +#define DEVICE1_EMAC_MODE_PORT_MODE_NONE 0x0u +#define DEVICE1_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u +#define DEVICE1_EMAC_MODE_PORT_MODE_1000 0x2u +#define DEVICE1_EMAC_MODE_PORT_MODE_TBI 0x3u + +#define DEVICE1_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u +#define DEVICE1_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u +#define GET_DEVICE1_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u +#define DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u +#define GET_DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u +#define DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u +#define GET_DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_EMAC_MODE_MAX_DEFER_SHIFT 9u +#define DEVICE1_EMAC_MODE_MAX_DEFER_MASK 0x200u +#define GET_DEVICE1_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u +#define DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u +#define GET_DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u +#define DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u +#define GET_DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u +#define DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u +#define GET_DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u +#define DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u +#define DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u +#define GET_DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u +#define DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u +#define GET_DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u +#define DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u +#define GET_DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u +#define DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u +#define GET_DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u +#define DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u +#define GET_DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE1_EMAC_MODE_ENABLE_TCE_SHIFT 21u +#define DEVICE1_EMAC_MODE_ENABLE_TCE_MASK 0x200000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE1_EMAC_MODE_ENABLE_RDE_SHIFT 22u +#define DEVICE1_EMAC_MODE_ENABLE_RDE_MASK 0x400000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE1_EMAC_MODE_ENABLE_FHDE_SHIFT 23u +#define DEVICE1_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) +#define DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u +#define DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u +#define GET_DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) +#define DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u +#define DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u +#define GET_DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u +#define DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u +#define GET_DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u +#define DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) +#define DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u +#define DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u +#define GET_DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u +#define DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u +#define GET_DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE1_LED_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa005040c) /* */ +#define DEVICE1_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u +#define DEVICE1_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u +#define GET_DEVICE1_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_LED_CONTROL_LED_1000_SHIFT 1u +#define DEVICE1_LED_CONTROL_LED_1000_MASK 0x2u +#define GET_DEVICE1_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_LED_CONTROL_LED_100_SHIFT 2u +#define DEVICE1_LED_CONTROL_LED_100_MASK 0x4u +#define GET_DEVICE1_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_LED_CONTROL_LED_10_SHIFT 3u +#define DEVICE1_LED_CONTROL_LED_10_MASK 0x8u +#define GET_DEVICE1_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u +#define DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u +#define GET_DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u +#define DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u +#define GET_DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_LED_CONTROL_LED_TRAFFIC_SHIFT 6u +#define DEVICE1_LED_CONTROL_LED_TRAFFIC_MASK 0x40u +#define GET_DEVICE1_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_LED_CONTROL_LED_STATUS_1000_SHIFT 7u +#define DEVICE1_LED_CONTROL_LED_STATUS_1000_MASK 0x80u +#define GET_DEVICE1_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_LED_CONTROL_LED_STATUS_100_SHIFT 8u +#define DEVICE1_LED_CONTROL_LED_STATUS_100_MASK 0x100u +#define GET_DEVICE1_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_LED_CONTROL_LED_STATUS_10_SHIFT 9u +#define DEVICE1_LED_CONTROL_LED_STATUS_10_MASK 0x200u +#define GET_DEVICE1_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u +#define DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u +#define GET_DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_LED_CONTROL_LED_MODE_SHIFT 11u +#define DEVICE1_LED_CONTROL_LED_MODE_MASK 0x1800u +#define GET_DEVICE1_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) +#define SET_DEVICE1_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) +#define DEVICE1_LED_CONTROL_LED_MODE_MAC 0x0u +#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u +#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u +#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u + +#define DEVICE1_LED_CONTROL_MAC_MODE_SHIFT 13u +#define DEVICE1_LED_CONTROL_MAC_MODE_MASK 0x2000u +#define GET_DEVICE1_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u +#define DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u +#define GET_DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_LED_CONTROL_BLINK_PERIOD_SHIFT 19u +#define DEVICE1_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u +#define GET_DEVICE1_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) +#define SET_DEVICE1_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) +#define DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u +#define DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u +#define GET_DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050410) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050414) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050418) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_1_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005041c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_2_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050420) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_2_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050424) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_3_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050428) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE1_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005042c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE1_WOL_PATTERN_POINTER ((volatile APE_DEVICE1_H_uint32_t*)0xa0050430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ +#define REG_DEVICE1_WOL_PATTERN_CFG ((volatile APE_DEVICE1_H_uint32_t*)0xa0050434) /* */ +#define REG_DEVICE1_MTU_SIZE ((volatile APE_DEVICE1_H_uint32_t*)0xa005043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ +#define DEVICE1_MTU_SIZE_MTU_SHIFT 0u +#define DEVICE1_MTU_SIZE_MTU_MASK 0xffffu +#define GET_DEVICE1_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE1_MII_COMMUNICATION ((volatile APE_DEVICE1_H_uint32_t*)0xa005044c) /* */ +#define DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u +#define DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu +#define GET_DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u +#define DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u +#define GET_DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u +#define GET_DEVICE1_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) +#define SET_DEVICE1_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau +#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu + +#define DEVICE1_MII_COMMUNICATION_COMMAND_SHIFT 26u +#define DEVICE1_MII_COMMUNICATION_COMMAND_MASK 0xc000000u +#define GET_DEVICE1_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) +#define SET_DEVICE1_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) +#define DEVICE1_MII_COMMUNICATION_COMMAND_WRITE 0x1u +#define DEVICE1_MII_COMMUNICATION_COMMAND_READ 0x2u + +#define DEVICE1_MII_COMMUNICATION_READ_FAILED_SHIFT 28u +#define DEVICE1_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u +#define GET_DEVICE1_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE1_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE1_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u +#define DEVICE1_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u +#define GET_DEVICE1_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE1_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE1_MII_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050454) /* */ +#define DEVICE1_MII_MODE_PHY_ADDRESS_SHIFT 5u +#define DEVICE1_MII_MODE_PHY_ADDRESS_MASK 0x3e0u +#define GET_DEVICE1_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) +#define SET_DEVICE1_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) +#define DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u +#define DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u +#define GET_DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u +#define DEVICE1_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u +#define GET_DEVICE1_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE1_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) + +#define REG_DEVICE1_TRANSMIT_MAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa005045c) /* */ +#define DEVICE1_TRANSMIT_MAC_MODE_RESET_SHIFT 0u +#define DEVICE1_TRANSMIT_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u +#define DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u +#define DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u +#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u +#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) + +#define REG_DEVICE1_RECEIVE_MAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050468) /* */ +#define DEVICE1_RECEIVE_MAC_MODE_RESET_SHIFT 0u +#define DEVICE1_RECEIVE_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE1_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u +#define DEVICE1_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE1_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u +#define DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u +#define GET_DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u +#define DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u +#define GET_DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) + +#define REG_DEVICE1_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050540) /* */ +#define DEVICE1_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u +#define DEVICE1_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE1_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE1_PERFECT_MATCH1_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050544) /* */ +#define DEVICE1_PERFECT_MATCH1_LOW_LOW_SHIFT 0u +#define DEVICE1_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE1_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE1_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050548) /* */ +#define DEVICE1_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u +#define DEVICE1_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE1_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE1_PERFECT_MATCH2_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005054c) /* */ +#define DEVICE1_PERFECT_MATCH2_LOW_LOW_SHIFT 0u +#define DEVICE1_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE1_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE1_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050550) /* */ +#define DEVICE1_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u +#define DEVICE1_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE1_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE1_PERFECT_MATCH3_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050554) /* */ +#define DEVICE1_PERFECT_MATCH3_LOW_LOW_SHIFT 0u +#define DEVICE1_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE1_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE1_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050558) /* */ +#define DEVICE1_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u +#define DEVICE1_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE1_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE1_PERFECT_MATCH4_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005055c) /* */ +#define DEVICE1_PERFECT_MATCH4_LOW_LOW_SHIFT 0u +#define DEVICE1_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE1_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE1_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE1_SGMII_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa00505b4) /* This register reflects various status of the respective SGMII port when enabled. */ +#define DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u +#define DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u +#define GET_DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_SGMII_STATUS_LINK_STATUS_SHIFT 1u +#define DEVICE1_SGMII_STATUS_LINK_STATUS_MASK 0x2u +#define GET_DEVICE1_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u +#define DEVICE1_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u +#define GET_DEVICE1_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_SGMII_STATUS_SPEED_1000_SHIFT 3u +#define DEVICE1_SGMII_STATUS_SPEED_1000_MASK 0x8u +#define GET_DEVICE1_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_SGMII_STATUS_SPEED_100_SHIFT 4u +#define DEVICE1_SGMII_STATUS_SPEED_100_MASK 0x10u +#define GET_DEVICE1_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u +#define DEVICE1_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u +#define GET_DEVICE1_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_SGMII_STATUS_PAUSE_RX_SHIFT 6u +#define DEVICE1_SGMII_STATUS_PAUSE_RX_MASK 0x40u +#define GET_DEVICE1_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_SGMII_STATUS_PAUSE_TX_SHIFT 7u +#define DEVICE1_SGMII_STATUS_PAUSE_TX_MASK 0x80u +#define GET_DEVICE1_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u +#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u +#define GET_DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u +#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u + +#define DEVICE1_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u +#define DEVICE1_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u +#define GET_DEVICE1_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u +#define DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u +#define GET_DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u +#define DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u +#define GET_DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE1_CPMU_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0053600) /* */ +#define DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u +#define DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u +#define GET_DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u +#define DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u +#define GET_DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_CPMU_CONTROL_POWER_DOWN_SHIFT 2u +#define DEVICE1_CPMU_CONTROL_POWER_DOWN_MASK 0x4u +#define GET_DEVICE1_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u +#define DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u +#define GET_DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u +#define DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u +#define GET_DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u +#define DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u +#define GET_DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u +#define DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u +#define GET_DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u +#define DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u +#define GET_DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u +#define DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u +#define GET_DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u +#define DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u +#define GET_DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u +#define DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u +#define GET_DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u +#define DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u +#define GET_DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) + +#define REG_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053610) /* */ +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u +#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu + + +#define REG_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053624) /* */ +#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u +#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u +#define GET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE1_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa005362c) /* */ +#define DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u +#define DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu +#define GET_DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) +#define SET_DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) +#define DEVICE1_STATUS_CPMU_POWER_STATE_SHIFT 4u +#define DEVICE1_STATUS_CPMU_POWER_STATE_MASK 0x70u +#define GET_DEVICE1_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) +#define SET_DEVICE1_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) +#define DEVICE1_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u +#define DEVICE1_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u +#define GET_DEVICE1_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_STATUS_POWER_STATE_SHIFT 8u +#define DEVICE1_STATUS_POWER_STATE_MASK 0x300u +#define GET_DEVICE1_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_STATUS_VMAIN_POWER_STATUS_SHIFT 13u +#define DEVICE1_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u +#define GET_DEVICE1_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u +#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u +#define GET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u +#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u +#define GET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u +#define DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u +#define GET_DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u +#define DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u +#define GET_DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE1_STATUS_LINK_IDLE_STATUS_SHIFT 18u +#define DEVICE1_STATUS_LINK_IDLE_STATUS_MASK 0x40000u +#define GET_DEVICE1_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE1_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u +#define GET_DEVICE1_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) +#define SET_DEVICE1_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u +#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u + +#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u +#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u +#define GET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u +#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u +#define GET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE1_STATUS_APE_STATUS_SHIFT 23u +#define DEVICE1_STATUS_APE_STATUS_MASK 0x1800000u +#define GET_DEVICE1_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) +#define SET_DEVICE1_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) +#define DEVICE1_STATUS_APE_STATUS_ACTIVE 0x0u +#define DEVICE1_STATUS_APE_STATUS_SLEEP 0x1u +#define DEVICE1_STATUS_APE_STATUS_DEEP_SLEEP 0x2u + +#define DEVICE1_STATUS_FUNCTION_ENABLE_SHIFT 25u +#define DEVICE1_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u +#define GET_DEVICE1_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) +#define SET_DEVICE1_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) +#define DEVICE1_STATUS_FUNCTION_NUMBER_SHIFT 30u +#define DEVICE1_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u +#define GET_DEVICE1_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) +#define SET_DEVICE1_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) + +#define REG_DEVICE1_CLOCK_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0053630) /* */ +#define REG_DEVICE1_GPHY_CONTROL_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0053638) /* */ +#define DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u +#define DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u +#define DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u +#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u +#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u +#define DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u +#define DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u +#define DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u +#define DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u +#define DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u +#define GET_DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) + +#define REG_DEVICE1_CHIP_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0053658) /* */ +#define REG_DEVICE1_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa005365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ +#define REG_DEVICE1_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa0053660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ +#define REG_DEVICE1_GPHY_STRAP ((volatile APE_DEVICE1_H_uint32_t*)0xa0053664) /* */ +#define DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u +#define DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u +#define GET_DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u +#define DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u +#define GET_DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u +#define DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u +#define GET_DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) + +#define REG_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa005367c) /* */ +#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u +#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u +#define GET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u +#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u +#define GET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE1_EEE_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa00536b0) /* */ +#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u +#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u +#define GET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u +#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u +#define GET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u +#define DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u +#define GET_DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u +#define DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u +#define GET_DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u +#define DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u +#define GET_DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u +#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u +#define GET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u +#define DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u +#define GET_DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u +#define DEVICE1_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u +#define GET_DEVICE1_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u +#define DEVICE1_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u +#define GET_DEVICE1_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u +#define DEVICE1_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u +#define GET_DEVICE1_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u +#define DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u +#define GET_DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_EEE_MODE_BLOCK_TIME_SHIFT 11u +#define DEVICE1_EEE_MODE_BLOCK_TIME_MASK 0x7f800u +#define GET_DEVICE1_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) +#define SET_DEVICE1_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) +#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u +#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u +#define GET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE1_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536bc) /* */ +#define DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u +#define DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u +#define GET_DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) + +#define REG_DEVICE1_EEE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536d0) /* */ +#define DEVICE1_EEE_CONTROL_EXIT_TIME_SHIFT 0u +#define DEVICE1_EEE_CONTROL_EXIT_TIME_MASK 0xffffu +#define GET_DEVICE1_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE1_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u +#define DEVICE1_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u +#define GET_DEVICE1_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE1_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE1_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f0) /* */ +#define REG_DEVICE1_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f4) /* */ +#define REG_DEVICE1_MEMORY_ARBITER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054000) /* */ +#define DEVICE1_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u +#define DEVICE1_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE1_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_DEVICE1_BUFFER_MANAGER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054400) /* */ +#define DEVICE1_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u +#define DEVICE1_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE1_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u +#define DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u +#define GET_DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u +#define DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u +#define GET_DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0054910) /* */ +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u +#define GET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u + +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u +#define GET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) +#define SET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u +#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u + + +#define REG_DEVICE1_RX_RISC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0055000) /* */ +#define DEVICE1_RX_RISC_MODE_RESET_SHIFT 0u +#define DEVICE1_RX_RISC_MODE_RESET_MASK 0x1u +#define GET_DEVICE1_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u +#define DEVICE1_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u +#define GET_DEVICE1_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u +#define DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u +#define GET_DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u +#define DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u +#define GET_DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u +#define DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u +#define GET_DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_RX_RISC_MODE_ROM_FAIL_SHIFT 6u +#define DEVICE1_RX_RISC_MODE_ROM_FAIL_MASK 0x40u +#define GET_DEVICE1_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u +#define DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u +#define GET_DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u +#define DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u +#define GET_DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u +#define DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u +#define GET_DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_RX_RISC_MODE_HALT_SHIFT 10u +#define DEVICE1_RX_RISC_MODE_HALT_MASK 0x400u +#define GET_DEVICE1_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u +#define DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u +#define GET_DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u +#define DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u +#define GET_DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u +#define DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u +#define GET_DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u +#define DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u +#define GET_DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) + +#define REG_DEVICE1_RX_RISC_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0055004) /* */ +#define DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u +#define DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u +#define GET_DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u +#define DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u +#define GET_DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u +#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u +#define GET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u +#define DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u +#define GET_DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u +#define DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u +#define GET_DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u +#define DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u +#define GET_DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u +#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u +#define GET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u +#define DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u +#define GET_DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u +#define DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u +#define GET_DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u +#define DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u +#define GET_DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_RX_RISC_STATUS_HALTED_SHIFT 10u +#define DEVICE1_RX_RISC_STATUS_HALTED_MASK 0x400u +#define GET_DEVICE1_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_RX_RISC_STATUS_UNKNOWN_SHIFT 11u +#define DEVICE1_RX_RISC_STATUS_UNKNOWN_MASK 0x800u +#define GET_DEVICE1_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE1_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u +#define DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u +#define GET_DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u +#define DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u +#define GET_DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u +#define DEVICE1_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u +#define GET_DEVICE1_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE1_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE1_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE1_H_uint32_t*)0xa005501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ +#define REG_DEVICE1_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE1_H_uint32_t*)0xa0055020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE1_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE1_H_uint32_t*)0xa0055034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE1_RX_RISC_REGISTER_0 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055200) /* $zero (R0) */ +#define REG_DEVICE1_RX_RISC_REGISTER_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055204) /* $at (R1) */ +#define REG_DEVICE1_RX_RISC_REGISTER_2 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055208) /* $v0 (R2) */ +#define REG_DEVICE1_RX_RISC_REGISTER_3 ((volatile APE_DEVICE1_H_uint32_t*)0xa005520c) /* $v1 (R3) */ +#define REG_DEVICE1_RX_RISC_REGISTER_4 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055210) /* $a0 (R4) */ +#define REG_DEVICE1_RX_RISC_REGISTER_5 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055214) /* $a1 (R5) */ +#define REG_DEVICE1_RX_RISC_REGISTER_6 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055218) /* $a2 (R6) */ +#define REG_DEVICE1_RX_RISC_REGISTER_7 ((volatile APE_DEVICE1_H_uint32_t*)0xa005521c) /* $a3 (R7) */ +#define REG_DEVICE1_RX_RISC_REGISTER_8 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055220) /* $t0 (R8) */ +#define REG_DEVICE1_RX_RISC_REGISTER_9 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055224) /* $t1 (R9) */ +#define REG_DEVICE1_RX_RISC_REGISTER_10 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055228) /* $t2 (R10) */ +#define REG_DEVICE1_RX_RISC_REGISTER_11 ((volatile APE_DEVICE1_H_uint32_t*)0xa005522c) /* $t3 (R11) */ +#define REG_DEVICE1_RX_RISC_REGISTER_12 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055230) /* $t4 (R12) */ +#define REG_DEVICE1_RX_RISC_REGISTER_13 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055234) /* $t5 (R13) */ +#define REG_DEVICE1_RX_RISC_REGISTER_14 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055238) /* $t6 (R14) */ +#define REG_DEVICE1_RX_RISC_REGISTER_15 ((volatile APE_DEVICE1_H_uint32_t*)0xa005523c) /* $t7 (R15) */ +#define REG_DEVICE1_RX_RISC_REGISTER_16 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055240) /* $s0 (R16) */ +#define REG_DEVICE1_RX_RISC_REGISTER_17 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055244) /* $s1 (R17) */ +#define REG_DEVICE1_RX_RISC_REGISTER_18 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055248) /* $s2 (R18) */ +#define REG_DEVICE1_RX_RISC_REGISTER_19 ((volatile APE_DEVICE1_H_uint32_t*)0xa005524c) /* $s3 (R19) */ +#define REG_DEVICE1_RX_RISC_REGISTER_20 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055250) /* $s4 (R20) */ +#define REG_DEVICE1_RX_RISC_REGISTER_21 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055254) /* $s5 (R21) */ +#define REG_DEVICE1_RX_RISC_REGISTER_22 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055258) /* $s6 (R22) */ +#define REG_DEVICE1_RX_RISC_REGISTER_23 ((volatile APE_DEVICE1_H_uint32_t*)0xa005525c) /* $s7 (R23) */ +#define REG_DEVICE1_RX_RISC_REGISTER_24 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055260) /* $t8 (R24) */ +#define REG_DEVICE1_RX_RISC_REGISTER_25 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055264) /* $t9 (R25) */ +#define REG_DEVICE1_RX_RISC_REGISTER_26 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055268) /* $k0 (R26) */ +#define REG_DEVICE1_RX_RISC_REGISTER_27 ((volatile APE_DEVICE1_H_uint32_t*)0xa005526c) /* $k1 (R27) */ +#define REG_DEVICE1_RX_RISC_REGISTER_28 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055270) /* $gp (R28) */ +#define REG_DEVICE1_RX_RISC_REGISTER_29 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055274) /* $sp (R29) */ +#define REG_DEVICE1_RX_RISC_REGISTER_30 ((volatile APE_DEVICE1_H_uint32_t*)0xa0055278) /* $fp (R30) */ +#define REG_DEVICE1_RX_RISC_REGISTER_31 ((volatile APE_DEVICE1_H_uint32_t*)0xa005527c) /* $ra (R31) */ +#define REG_DEVICE1_6408 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056408) /* */ +#define REG_DEVICE1_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE1_H_uint32_t*)0xa0056410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE1_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE1_H_uint32_t*)0xa0056414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE1_PCI_VPD_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa005642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ +#define DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u +#define DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u +#define GET_DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) +#define SET_DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) + +#define REG_DEVICE1_PCI_VPD_RESPONSE ((volatile APE_DEVICE1_H_uint32_t*)0xa0056430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ +#define REG_DEVICE1_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0056434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ +#define DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u +#define DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu +#define GET_DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u +#define DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u +#define GET_DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE1_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0056438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ +#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u +#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu +#define GET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u +#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u +#define GET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE1_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE1_H_uint32_t*)0xa005643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ +#define REG_DEVICE1_64C0 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c0) /* */ +#define REG_DEVICE1_64C8 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c8) /* */ +#define REG_DEVICE1_64DC ((volatile APE_DEVICE1_H_uint32_t*)0xa00564dc) /* */ +#define REG_DEVICE1_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0056504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE1_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0056508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE1_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ +#define DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056514) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056518) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE1_H_uint32_t*)0xa005651c) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056520) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056524) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056528) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE1_H_uint32_t*)0xa005652c) /* See */ +#define DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u +#define DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu +#define GET_DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u +#define GET_DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u +#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u +#define DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u +#define GET_DEVICE1_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u +#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u + +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u +#define GET_DEVICE1_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u +#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u + +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE1_6530 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056530) /* */ +#define REG_DEVICE1_6550 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ +#define REG_DEVICE1_65F4 ((volatile APE_DEVICE1_H_uint32_t*)0xa00565f4) /* */ +#define REG_DEVICE1_GRC_MODE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056800) /* */ +#define DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u +#define DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u +#define GET_DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u +#define DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u +#define GET_DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u +#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u +#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u +#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u +#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE1_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE1_H_uint32_t*)0xa0056804) /* */ +#define DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u +#define DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u +#define GET_DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE1_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u +#define DEVICE1_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu +#define GET_DEVICE1_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) +#define SET_DEVICE1_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) + +#define REG_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056808) /* */ +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u +#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u +#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) + +#define REG_DEVICE1_TIMER ((volatile APE_DEVICE1_H_uint32_t*)0xa005680c) /* 32-bit free-running counter */ +#define REG_DEVICE1_RX_CPU_EVENT ((volatile APE_DEVICE1_H_uint32_t*)0xa0056810) /* */ +#define DEVICE1_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u +#define DEVICE1_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u +#define GET_DEVICE1_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE1_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u +#define DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u +#define GET_DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE1_RX_CPU_EVENT_TIMER_SHIFT 29u +#define DEVICE1_RX_CPU_EVENT_TIMER_MASK 0x20000000u +#define GET_DEVICE1_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE1_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE1_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u +#define DEVICE1_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE1_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE1_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE1_6838 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056838) /* Unknown. Used by PXE agent. */ +#define REG_DEVICE1_MDI_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ +#define REG_DEVICE1_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE1_H_uint32_t*)0xa005684c) /* */ +#define DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u +#define DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE1_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE1_H_uint32_t*)0xa0056894) /* */ +#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u +#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu +#define GET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) +#define SET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) +#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u +#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u +#define GET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE1_EXPANSION_ROM_ADDR ((volatile APE_DEVICE1_H_uint32_t*)0xa00568ec) /* Expansion ROM base address, expect to be d- word aligned. */ +#define REG_DEVICE1_68F0 ((volatile APE_DEVICE1_H_uint32_t*)0xa00568f0) /* */ +#define REG_DEVICE1_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056908) /* */ +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u +#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u + +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u +#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u +#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) +#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u +#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) +#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u +#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) +#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u + + +#define REG_DEVICE1_7C04 ((volatile APE_DEVICE1_H_uint32_t*)0xa0057c04) /* PCIe-related. tg3 driver calls this */ +/** @brief Device Registers, function 1 */ +extern volatile DEVICE_t DEVICE1; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_DEVICE1_H */ + +/** @} */ diff --git a/include/APE_DEVICE2.h b/include/APE_DEVICE2.h new file mode 100644 index 0000000..8a35530 --- /dev/null +++ b/include/APE_DEVICE2.h @@ -0,0 +1,1720 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE2.h +/// +/// @project ape +/// +/// @brief APE_DEVICE2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_DEVICE2_H APE_DEVICE2 */ +/** @addtogroup APE_DEVICE2_H + * @{ + */ +#ifndef APE_DEVICE2_H +#define APE_DEVICE2_H + +#include <stdint.h> +#include "APE_DEVICE.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_DEVICE2_sim(void* base); +void init_APE_DEVICE2(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_DEVICE2_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_DEVICE2_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_DEVICE2_H_uint32_t; +#define APE_DEVICE2_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_DEVICE2_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_DEVICE2_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_DEVICE2_H_uint8_t; +typedef uint16_t APE_DEVICE2_H_uint16_t; +typedef uint32_t APE_DEVICE2_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_DEVICE2_BASE ((volatile void*)0xa0060000) /* Device Registers, function 2 */ +#define REG_DEVICE2_SIZE (sizeof(DEVICE_t)) + +#define REG_DEVICE2_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0060068) /* */ +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u + +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u + +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u +#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) +#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu + + +#define REG_DEVICE2_PCI_STATE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060070) /* */ +#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u +#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u +#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u +#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u +#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_PCI_STATE_VPD_AVAILABLE_SHIFT 7u +#define DEVICE2_PCI_STATE_VPD_AVAILABLE_MASK 0x80u +#define GET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_PCI_STATE_FLAT_VIEW_SHIFT 8u +#define DEVICE2_PCI_STATE_FLAT_VIEW_MASK 0x100u +#define GET_DEVICE2_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u +#define DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u +#define GET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) +#define SET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) +#define DEVICE2_PCI_STATE_CONFIG_RETRY_SHIFT 15u +#define DEVICE2_PCI_STATE_CONFIG_RETRY_MASK 0x8000u +#define GET_DEVICE2_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u +#define DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u +#define GET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u +#define DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u +#define GET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u +#define DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u +#define GET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u +#define DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u +#define GET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE2_REGISTER_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ +#define REG_DEVICE2_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa006007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ +#define REG_DEVICE2_REGISTER_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa0060080) /* Register Data at the location pointed by the Register Base Register. */ +#define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE2_H_uint32_t*)0xa0060088) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE2_LINK_STATUS_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00600bc) /* PCIe standard register. */ +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u +#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) +#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u + +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u +#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u +#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) +#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) + +#define REG_DEVICE2_APE_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa00600f8) /* APE Memory address to read/write using the APE Memory Data register.. */ +#define REG_DEVICE2_APE_MEMORY_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa00600fc) /* APE Memory value at the location pointed by the Memory Base Register. */ +#define REG_DEVICE2_EMAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060400) /* */ +#define DEVICE2_EMAC_MODE_GLOBAL_RESET_SHIFT 0u +#define DEVICE2_EMAC_MODE_GLOBAL_RESET_MASK 0x1u +#define GET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_EMAC_MODE_HALF_DUPLEX_SHIFT 1u +#define DEVICE2_EMAC_MODE_HALF_DUPLEX_MASK 0x2u +#define GET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_EMAC_MODE_PORT_MODE_SHIFT 2u +#define DEVICE2_EMAC_MODE_PORT_MODE_MASK 0xcu +#define GET_DEVICE2_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) +#define SET_DEVICE2_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) +#define DEVICE2_EMAC_MODE_PORT_MODE_NONE 0x0u +#define DEVICE2_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u +#define DEVICE2_EMAC_MODE_PORT_MODE_1000 0x2u +#define DEVICE2_EMAC_MODE_PORT_MODE_TBI 0x3u + +#define DEVICE2_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u +#define DEVICE2_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u +#define GET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u +#define DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u +#define GET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u +#define DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u +#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_EMAC_MODE_MAX_DEFER_SHIFT 9u +#define DEVICE2_EMAC_MODE_MAX_DEFER_MASK 0x200u +#define GET_DEVICE2_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u +#define DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u +#define GET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u +#define DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u +#define GET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u +#define DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u +#define GET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u +#define DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u +#define DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u +#define GET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u +#define DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u +#define GET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u +#define DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u +#define GET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u +#define DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u +#define GET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u +#define DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u +#define GET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE2_EMAC_MODE_ENABLE_TCE_SHIFT 21u +#define DEVICE2_EMAC_MODE_ENABLE_TCE_MASK 0x200000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE2_EMAC_MODE_ENABLE_RDE_SHIFT 22u +#define DEVICE2_EMAC_MODE_ENABLE_RDE_MASK 0x400000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE2_EMAC_MODE_ENABLE_FHDE_SHIFT 23u +#define DEVICE2_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) +#define DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u +#define DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u +#define GET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) +#define DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u +#define DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u +#define GET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u +#define DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u +#define GET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u +#define DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) +#define DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u +#define DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u +#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u +#define DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u +#define GET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE2_LED_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa006040c) /* */ +#define DEVICE2_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u +#define DEVICE2_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u +#define GET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_LED_CONTROL_LED_1000_SHIFT 1u +#define DEVICE2_LED_CONTROL_LED_1000_MASK 0x2u +#define GET_DEVICE2_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_LED_CONTROL_LED_100_SHIFT 2u +#define DEVICE2_LED_CONTROL_LED_100_MASK 0x4u +#define GET_DEVICE2_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_LED_CONTROL_LED_10_SHIFT 3u +#define DEVICE2_LED_CONTROL_LED_10_MASK 0x8u +#define GET_DEVICE2_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u +#define DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u +#define GET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u +#define DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u +#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_LED_CONTROL_LED_TRAFFIC_SHIFT 6u +#define DEVICE2_LED_CONTROL_LED_TRAFFIC_MASK 0x40u +#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_LED_CONTROL_LED_STATUS_1000_SHIFT 7u +#define DEVICE2_LED_CONTROL_LED_STATUS_1000_MASK 0x80u +#define GET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_LED_CONTROL_LED_STATUS_100_SHIFT 8u +#define DEVICE2_LED_CONTROL_LED_STATUS_100_MASK 0x100u +#define GET_DEVICE2_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_LED_CONTROL_LED_STATUS_10_SHIFT 9u +#define DEVICE2_LED_CONTROL_LED_STATUS_10_MASK 0x200u +#define GET_DEVICE2_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u +#define DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u +#define GET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_LED_CONTROL_LED_MODE_SHIFT 11u +#define DEVICE2_LED_CONTROL_LED_MODE_MASK 0x1800u +#define GET_DEVICE2_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) +#define SET_DEVICE2_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) +#define DEVICE2_LED_CONTROL_LED_MODE_MAC 0x0u +#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u +#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u +#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u + +#define DEVICE2_LED_CONTROL_MAC_MODE_SHIFT 13u +#define DEVICE2_LED_CONTROL_MAC_MODE_MASK 0x2000u +#define GET_DEVICE2_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u +#define DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u +#define GET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_LED_CONTROL_BLINK_PERIOD_SHIFT 19u +#define DEVICE2_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u +#define GET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) +#define SET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) +#define DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u +#define DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u +#define GET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060410) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060414) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060418) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_1_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006041c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_2_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060420) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_2_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060424) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_3_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060428) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE2_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006042c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE2_WOL_PATTERN_POINTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0060430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ +#define REG_DEVICE2_WOL_PATTERN_CFG ((volatile APE_DEVICE2_H_uint32_t*)0xa0060434) /* */ +#define REG_DEVICE2_MTU_SIZE ((volatile APE_DEVICE2_H_uint32_t*)0xa006043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ +#define DEVICE2_MTU_SIZE_MTU_SHIFT 0u +#define DEVICE2_MTU_SIZE_MTU_MASK 0xffffu +#define GET_DEVICE2_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE2_MII_COMMUNICATION ((volatile APE_DEVICE2_H_uint32_t*)0xa006044c) /* */ +#define DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u +#define DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu +#define GET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u +#define DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u +#define GET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u +#define GET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) +#define SET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau +#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu + +#define DEVICE2_MII_COMMUNICATION_COMMAND_SHIFT 26u +#define DEVICE2_MII_COMMUNICATION_COMMAND_MASK 0xc000000u +#define GET_DEVICE2_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) +#define SET_DEVICE2_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) +#define DEVICE2_MII_COMMUNICATION_COMMAND_WRITE 0x1u +#define DEVICE2_MII_COMMUNICATION_COMMAND_READ 0x2u + +#define DEVICE2_MII_COMMUNICATION_READ_FAILED_SHIFT 28u +#define DEVICE2_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u +#define GET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u +#define DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u +#define GET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE2_MII_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060454) /* */ +#define DEVICE2_MII_MODE_PHY_ADDRESS_SHIFT 5u +#define DEVICE2_MII_MODE_PHY_ADDRESS_MASK 0x3e0u +#define GET_DEVICE2_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) +#define SET_DEVICE2_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) +#define DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u +#define DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u +#define GET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u +#define DEVICE2_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u +#define GET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) + +#define REG_DEVICE2_TRANSMIT_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa006045c) /* */ +#define DEVICE2_TRANSMIT_MAC_MODE_RESET_SHIFT 0u +#define DEVICE2_TRANSMIT_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u +#define DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u +#define DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u +#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u +#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) + +#define REG_DEVICE2_RECEIVE_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060468) /* */ +#define DEVICE2_RECEIVE_MAC_MODE_RESET_SHIFT 0u +#define DEVICE2_RECEIVE_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE2_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u +#define DEVICE2_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u +#define DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u +#define GET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u +#define DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u +#define GET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) + +#define REG_DEVICE2_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060540) /* */ +#define DEVICE2_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u +#define DEVICE2_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE2_PERFECT_MATCH1_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060544) /* */ +#define DEVICE2_PERFECT_MATCH1_LOW_LOW_SHIFT 0u +#define DEVICE2_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE2_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060548) /* */ +#define DEVICE2_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u +#define DEVICE2_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE2_PERFECT_MATCH2_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006054c) /* */ +#define DEVICE2_PERFECT_MATCH2_LOW_LOW_SHIFT 0u +#define DEVICE2_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE2_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060550) /* */ +#define DEVICE2_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u +#define DEVICE2_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE2_PERFECT_MATCH3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060554) /* */ +#define DEVICE2_PERFECT_MATCH3_LOW_LOW_SHIFT 0u +#define DEVICE2_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE2_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060558) /* */ +#define DEVICE2_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u +#define DEVICE2_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE2_PERFECT_MATCH4_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006055c) /* */ +#define DEVICE2_PERFECT_MATCH4_LOW_LOW_SHIFT 0u +#define DEVICE2_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE2_SGMII_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa00605b4) /* This register reflects various status of the respective SGMII port when enabled. */ +#define DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u +#define DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u +#define GET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_SGMII_STATUS_LINK_STATUS_SHIFT 1u +#define DEVICE2_SGMII_STATUS_LINK_STATUS_MASK 0x2u +#define GET_DEVICE2_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u +#define DEVICE2_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u +#define GET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_SGMII_STATUS_SPEED_1000_SHIFT 3u +#define DEVICE2_SGMII_STATUS_SPEED_1000_MASK 0x8u +#define GET_DEVICE2_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_SGMII_STATUS_SPEED_100_SHIFT 4u +#define DEVICE2_SGMII_STATUS_SPEED_100_MASK 0x10u +#define GET_DEVICE2_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u +#define DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u +#define GET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_SGMII_STATUS_PAUSE_RX_SHIFT 6u +#define DEVICE2_SGMII_STATUS_PAUSE_RX_MASK 0x40u +#define GET_DEVICE2_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_SGMII_STATUS_PAUSE_TX_SHIFT 7u +#define DEVICE2_SGMII_STATUS_PAUSE_TX_MASK 0x80u +#define GET_DEVICE2_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u +#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u +#define GET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u +#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u + +#define DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u +#define DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u +#define GET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u +#define DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u +#define GET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u +#define DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u +#define GET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE2_CPMU_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0063600) /* */ +#define DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u +#define DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u +#define GET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u +#define DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u +#define GET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_CPMU_CONTROL_POWER_DOWN_SHIFT 2u +#define DEVICE2_CPMU_CONTROL_POWER_DOWN_MASK 0x4u +#define GET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u +#define DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u +#define GET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u +#define DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u +#define GET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u +#define DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u +#define GET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u +#define DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u +#define GET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u +#define DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u +#define GET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u +#define DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u +#define GET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u +#define DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u +#define GET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u +#define DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u +#define GET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u +#define DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u +#define GET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) + +#define REG_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063610) /* */ +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u +#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu + + +#define REG_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063624) /* */ +#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u +#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u +#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE2_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa006362c) /* */ +#define DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u +#define DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu +#define GET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) +#define SET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) +#define DEVICE2_STATUS_CPMU_POWER_STATE_SHIFT 4u +#define DEVICE2_STATUS_CPMU_POWER_STATE_MASK 0x70u +#define GET_DEVICE2_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) +#define SET_DEVICE2_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) +#define DEVICE2_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u +#define DEVICE2_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u +#define GET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_STATUS_POWER_STATE_SHIFT 8u +#define DEVICE2_STATUS_POWER_STATE_MASK 0x300u +#define GET_DEVICE2_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_STATUS_VMAIN_POWER_STATUS_SHIFT 13u +#define DEVICE2_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u +#define GET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u +#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u +#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u +#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u +#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u +#define DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u +#define GET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u +#define DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u +#define GET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE2_STATUS_LINK_IDLE_STATUS_SHIFT 18u +#define DEVICE2_STATUS_LINK_IDLE_STATUS_MASK 0x40000u +#define GET_DEVICE2_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE2_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u +#define GET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) +#define SET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u +#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u + +#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u +#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u +#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u +#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u +#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE2_STATUS_APE_STATUS_SHIFT 23u +#define DEVICE2_STATUS_APE_STATUS_MASK 0x1800000u +#define GET_DEVICE2_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) +#define SET_DEVICE2_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) +#define DEVICE2_STATUS_APE_STATUS_ACTIVE 0x0u +#define DEVICE2_STATUS_APE_STATUS_SLEEP 0x1u +#define DEVICE2_STATUS_APE_STATUS_DEEP_SLEEP 0x2u + +#define DEVICE2_STATUS_FUNCTION_ENABLE_SHIFT 25u +#define DEVICE2_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u +#define GET_DEVICE2_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) +#define SET_DEVICE2_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) +#define DEVICE2_STATUS_FUNCTION_NUMBER_SHIFT 30u +#define DEVICE2_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u +#define GET_DEVICE2_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) +#define SET_DEVICE2_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) + +#define REG_DEVICE2_CLOCK_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063630) /* */ +#define REG_DEVICE2_GPHY_CONTROL_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063638) /* */ +#define DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u +#define DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u +#define DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u +#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u +#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u +#define DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u +#define DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u +#define DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u +#define DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u +#define DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u +#define GET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) + +#define REG_DEVICE2_CHIP_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0063658) /* */ +#define REG_DEVICE2_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ +#define REG_DEVICE2_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa0063660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ +#define REG_DEVICE2_GPHY_STRAP ((volatile APE_DEVICE2_H_uint32_t*)0xa0063664) /* */ +#define DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u +#define DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u +#define GET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u +#define DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u +#define GET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u +#define DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u +#define GET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) + +#define REG_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa006367c) /* */ +#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u +#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u +#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u +#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u +#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE2_EEE_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa00636b0) /* */ +#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u +#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u +#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u +#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u +#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u +#define DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u +#define GET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u +#define DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u +#define GET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u +#define DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u +#define GET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u +#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u +#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u +#define DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u +#define GET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u +#define DEVICE2_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u +#define GET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u +#define DEVICE2_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u +#define GET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u +#define DEVICE2_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u +#define GET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u +#define DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u +#define GET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_EEE_MODE_BLOCK_TIME_SHIFT 11u +#define DEVICE2_EEE_MODE_BLOCK_TIME_MASK 0x7f800u +#define GET_DEVICE2_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) +#define SET_DEVICE2_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) +#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u +#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u +#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE2_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636bc) /* */ +#define DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u +#define DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u +#define GET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) + +#define REG_DEVICE2_EEE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636d0) /* */ +#define DEVICE2_EEE_CONTROL_EXIT_TIME_SHIFT 0u +#define DEVICE2_EEE_CONTROL_EXIT_TIME_MASK 0xffffu +#define GET_DEVICE2_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u +#define DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u +#define GET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE2_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f0) /* */ +#define REG_DEVICE2_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f4) /* */ +#define REG_DEVICE2_MEMORY_ARBITER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064000) /* */ +#define DEVICE2_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u +#define DEVICE2_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_DEVICE2_BUFFER_MANAGER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064400) /* */ +#define DEVICE2_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u +#define DEVICE2_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u +#define DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u +#define GET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u +#define DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u +#define GET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0064910) /* */ +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u +#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u + +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u +#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) +#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u +#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u + + +#define REG_DEVICE2_RX_RISC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0065000) /* */ +#define DEVICE2_RX_RISC_MODE_RESET_SHIFT 0u +#define DEVICE2_RX_RISC_MODE_RESET_MASK 0x1u +#define GET_DEVICE2_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u +#define DEVICE2_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u +#define GET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u +#define DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u +#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u +#define DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u +#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u +#define DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u +#define GET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_RX_RISC_MODE_ROM_FAIL_SHIFT 6u +#define DEVICE2_RX_RISC_MODE_ROM_FAIL_MASK 0x40u +#define GET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u +#define DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u +#define GET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u +#define DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u +#define GET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u +#define DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u +#define GET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_RX_RISC_MODE_HALT_SHIFT 10u +#define DEVICE2_RX_RISC_MODE_HALT_MASK 0x400u +#define GET_DEVICE2_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u +#define DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u +#define GET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u +#define DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u +#define GET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u +#define DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u +#define GET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u +#define DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u +#define GET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) + +#define REG_DEVICE2_RX_RISC_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0065004) /* */ +#define DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u +#define DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u +#define GET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u +#define DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u +#define GET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u +#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u +#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u +#define DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u +#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u +#define DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u +#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u +#define DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u +#define GET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u +#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u +#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u +#define DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u +#define GET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u +#define DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u +#define GET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u +#define DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u +#define GET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_RX_RISC_STATUS_HALTED_SHIFT 10u +#define DEVICE2_RX_RISC_STATUS_HALTED_MASK 0x400u +#define GET_DEVICE2_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_RX_RISC_STATUS_UNKNOWN_SHIFT 11u +#define DEVICE2_RX_RISC_STATUS_UNKNOWN_MASK 0x800u +#define GET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u +#define DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u +#define GET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u +#define DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u +#define GET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u +#define DEVICE2_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u +#define GET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE2_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa006501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ +#define REG_DEVICE2_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE2_H_uint32_t*)0xa0065020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE2_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE2_H_uint32_t*)0xa0065034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE2_RX_RISC_REGISTER_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065200) /* $zero (R0) */ +#define REG_DEVICE2_RX_RISC_REGISTER_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065204) /* $at (R1) */ +#define REG_DEVICE2_RX_RISC_REGISTER_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065208) /* $v0 (R2) */ +#define REG_DEVICE2_RX_RISC_REGISTER_3 ((volatile APE_DEVICE2_H_uint32_t*)0xa006520c) /* $v1 (R3) */ +#define REG_DEVICE2_RX_RISC_REGISTER_4 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065210) /* $a0 (R4) */ +#define REG_DEVICE2_RX_RISC_REGISTER_5 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065214) /* $a1 (R5) */ +#define REG_DEVICE2_RX_RISC_REGISTER_6 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065218) /* $a2 (R6) */ +#define REG_DEVICE2_RX_RISC_REGISTER_7 ((volatile APE_DEVICE2_H_uint32_t*)0xa006521c) /* $a3 (R7) */ +#define REG_DEVICE2_RX_RISC_REGISTER_8 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065220) /* $t0 (R8) */ +#define REG_DEVICE2_RX_RISC_REGISTER_9 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065224) /* $t1 (R9) */ +#define REG_DEVICE2_RX_RISC_REGISTER_10 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065228) /* $t2 (R10) */ +#define REG_DEVICE2_RX_RISC_REGISTER_11 ((volatile APE_DEVICE2_H_uint32_t*)0xa006522c) /* $t3 (R11) */ +#define REG_DEVICE2_RX_RISC_REGISTER_12 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065230) /* $t4 (R12) */ +#define REG_DEVICE2_RX_RISC_REGISTER_13 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065234) /* $t5 (R13) */ +#define REG_DEVICE2_RX_RISC_REGISTER_14 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065238) /* $t6 (R14) */ +#define REG_DEVICE2_RX_RISC_REGISTER_15 ((volatile APE_DEVICE2_H_uint32_t*)0xa006523c) /* $t7 (R15) */ +#define REG_DEVICE2_RX_RISC_REGISTER_16 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065240) /* $s0 (R16) */ +#define REG_DEVICE2_RX_RISC_REGISTER_17 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065244) /* $s1 (R17) */ +#define REG_DEVICE2_RX_RISC_REGISTER_18 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065248) /* $s2 (R18) */ +#define REG_DEVICE2_RX_RISC_REGISTER_19 ((volatile APE_DEVICE2_H_uint32_t*)0xa006524c) /* $s3 (R19) */ +#define REG_DEVICE2_RX_RISC_REGISTER_20 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065250) /* $s4 (R20) */ +#define REG_DEVICE2_RX_RISC_REGISTER_21 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065254) /* $s5 (R21) */ +#define REG_DEVICE2_RX_RISC_REGISTER_22 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065258) /* $s6 (R22) */ +#define REG_DEVICE2_RX_RISC_REGISTER_23 ((volatile APE_DEVICE2_H_uint32_t*)0xa006525c) /* $s7 (R23) */ +#define REG_DEVICE2_RX_RISC_REGISTER_24 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065260) /* $t8 (R24) */ +#define REG_DEVICE2_RX_RISC_REGISTER_25 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065264) /* $t9 (R25) */ +#define REG_DEVICE2_RX_RISC_REGISTER_26 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065268) /* $k0 (R26) */ +#define REG_DEVICE2_RX_RISC_REGISTER_27 ((volatile APE_DEVICE2_H_uint32_t*)0xa006526c) /* $k1 (R27) */ +#define REG_DEVICE2_RX_RISC_REGISTER_28 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065270) /* $gp (R28) */ +#define REG_DEVICE2_RX_RISC_REGISTER_29 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065274) /* $sp (R29) */ +#define REG_DEVICE2_RX_RISC_REGISTER_30 ((volatile APE_DEVICE2_H_uint32_t*)0xa0065278) /* $fp (R30) */ +#define REG_DEVICE2_RX_RISC_REGISTER_31 ((volatile APE_DEVICE2_H_uint32_t*)0xa006527c) /* $ra (R31) */ +#define REG_DEVICE2_6408 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066408) /* */ +#define REG_DEVICE2_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE2_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE2_PCI_VPD_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ +#define DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u +#define DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u +#define GET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) +#define SET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) + +#define REG_DEVICE2_PCI_VPD_RESPONSE ((volatile APE_DEVICE2_H_uint32_t*)0xa0066430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ +#define REG_DEVICE2_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ +#define DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u +#define DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu +#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u +#define DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u +#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE2_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ +#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u +#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu +#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u +#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u +#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE2_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE2_H_uint32_t*)0xa006643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ +#define REG_DEVICE2_64C0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c0) /* */ +#define REG_DEVICE2_64C8 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c8) /* */ +#define REG_DEVICE2_64DC ((volatile APE_DEVICE2_H_uint32_t*)0xa00664dc) /* */ +#define REG_DEVICE2_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0066504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE2_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0066508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE2_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ +#define DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066514) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066518) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE2_H_uint32_t*)0xa006651c) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066520) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066524) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066528) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE2_H_uint32_t*)0xa006652c) /* See */ +#define DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u +#define DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu +#define GET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u +#define GET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u +#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u +#define DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u +#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u +#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u + +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u +#define GET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u +#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u + +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE2_6530 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066530) /* */ +#define REG_DEVICE2_6550 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ +#define REG_DEVICE2_65F4 ((volatile APE_DEVICE2_H_uint32_t*)0xa00665f4) /* */ +#define REG_DEVICE2_GRC_MODE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066800) /* */ +#define DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u +#define DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u +#define GET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u +#define DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u +#define GET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u +#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u +#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u +#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u +#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE2_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE2_H_uint32_t*)0xa0066804) /* */ +#define DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u +#define DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u +#define GET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE2_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u +#define DEVICE2_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu +#define GET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) +#define SET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) + +#define REG_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066808) /* */ +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u +#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u +#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) + +#define REG_DEVICE2_TIMER ((volatile APE_DEVICE2_H_uint32_t*)0xa006680c) /* 32-bit free-running counter */ +#define REG_DEVICE2_RX_CPU_EVENT ((volatile APE_DEVICE2_H_uint32_t*)0xa0066810) /* */ +#define DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u +#define DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u +#define GET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u +#define DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u +#define GET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE2_RX_CPU_EVENT_TIMER_SHIFT 29u +#define DEVICE2_RX_CPU_EVENT_TIMER_MASK 0x20000000u +#define GET_DEVICE2_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE2_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u +#define DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE2_6838 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066838) /* Unknown. Used by PXE agent. */ +#define REG_DEVICE2_MDI_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ +#define REG_DEVICE2_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE2_H_uint32_t*)0xa006684c) /* */ +#define DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u +#define DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE2_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0066894) /* */ +#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u +#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu +#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) +#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) +#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u +#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u +#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE2_EXPANSION_ROM_ADDR ((volatile APE_DEVICE2_H_uint32_t*)0xa00668ec) /* Expansion ROM base address, expect to be d- word aligned. */ +#define REG_DEVICE2_68F0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00668f0) /* */ +#define REG_DEVICE2_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066908) /* */ +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u +#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u + +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u +#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u +#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) +#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u +#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) +#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u +#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) +#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u + + +#define REG_DEVICE2_7C04 ((volatile APE_DEVICE2_H_uint32_t*)0xa0067c04) /* PCIe-related. tg3 driver calls this */ +/** @brief Device Registers, function 2 */ +extern volatile DEVICE_t DEVICE2; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_DEVICE2_H */ + +/** @} */ diff --git a/include/APE_DEVICE3.h b/include/APE_DEVICE3.h new file mode 100644 index 0000000..a2917b6 --- /dev/null +++ b/include/APE_DEVICE3.h @@ -0,0 +1,1720 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE3.h +/// +/// @project ape +/// +/// @brief APE_DEVICE3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_DEVICE3_H APE_DEVICE3 */ +/** @addtogroup APE_DEVICE3_H + * @{ + */ +#ifndef APE_DEVICE3_H +#define APE_DEVICE3_H + +#include <stdint.h> +#include "APE_DEVICE.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_DEVICE3_sim(void* base); +void init_APE_DEVICE3(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_DEVICE3_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_DEVICE3_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_DEVICE3_H_uint32_t; +#define APE_DEVICE3_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_DEVICE3_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_DEVICE3_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_DEVICE3_H_uint8_t; +typedef uint16_t APE_DEVICE3_H_uint16_t; +typedef uint32_t APE_DEVICE3_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_DEVICE3_BASE ((volatile void*)0xa0070000) /* Device Registers, function 3 */ +#define REG_DEVICE3_SIZE (sizeof(DEVICE_t)) + +#define REG_DEVICE3_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0070068) /* */ +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u + +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u + +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u +#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) +#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu + + +#define REG_DEVICE3_PCI_STATE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070070) /* */ +#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u +#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u +#define GET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u +#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u +#define GET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_PCI_STATE_VPD_AVAILABLE_SHIFT 7u +#define DEVICE3_PCI_STATE_VPD_AVAILABLE_MASK 0x80u +#define GET_DEVICE3_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_PCI_STATE_FLAT_VIEW_SHIFT 8u +#define DEVICE3_PCI_STATE_FLAT_VIEW_MASK 0x100u +#define GET_DEVICE3_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u +#define DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u +#define GET_DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) +#define SET_DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) +#define DEVICE3_PCI_STATE_CONFIG_RETRY_SHIFT 15u +#define DEVICE3_PCI_STATE_CONFIG_RETRY_MASK 0x8000u +#define GET_DEVICE3_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u +#define DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u +#define GET_DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u +#define DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u +#define GET_DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u +#define DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u +#define GET_DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE3_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u +#define DEVICE3_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u +#define GET_DEVICE3_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE3_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE3_REGISTER_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ +#define REG_DEVICE3_MEMORY_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa007007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ +#define REG_DEVICE3_REGISTER_DATA ((volatile APE_DEVICE3_H_uint32_t*)0xa0070080) /* Register Data at the location pointed by the Register Base Register. */ +#define REG_DEVICE3_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE3_H_uint32_t*)0xa0070088) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE3_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ +#define REG_DEVICE3_LINK_STATUS_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00700bc) /* PCIe standard register. */ +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u +#define GET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) +#define SET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u + +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u +#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u +#define GET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) +#define SET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) + +#define REG_DEVICE3_APE_MEMORY_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa00700f8) /* APE Memory address to read/write using the APE Memory Data register.. */ +#define REG_DEVICE3_APE_MEMORY_DATA ((volatile APE_DEVICE3_H_uint32_t*)0xa00700fc) /* APE Memory value at the location pointed by the Memory Base Register. */ +#define REG_DEVICE3_EMAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070400) /* */ +#define DEVICE3_EMAC_MODE_GLOBAL_RESET_SHIFT 0u +#define DEVICE3_EMAC_MODE_GLOBAL_RESET_MASK 0x1u +#define GET_DEVICE3_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_EMAC_MODE_HALF_DUPLEX_SHIFT 1u +#define DEVICE3_EMAC_MODE_HALF_DUPLEX_MASK 0x2u +#define GET_DEVICE3_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_EMAC_MODE_PORT_MODE_SHIFT 2u +#define DEVICE3_EMAC_MODE_PORT_MODE_MASK 0xcu +#define GET_DEVICE3_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) +#define SET_DEVICE3_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) +#define DEVICE3_EMAC_MODE_PORT_MODE_NONE 0x0u +#define DEVICE3_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u +#define DEVICE3_EMAC_MODE_PORT_MODE_1000 0x2u +#define DEVICE3_EMAC_MODE_PORT_MODE_TBI 0x3u + +#define DEVICE3_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u +#define DEVICE3_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u +#define GET_DEVICE3_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u +#define DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u +#define GET_DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u +#define DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u +#define GET_DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_EMAC_MODE_MAX_DEFER_SHIFT 9u +#define DEVICE3_EMAC_MODE_MAX_DEFER_MASK 0x200u +#define GET_DEVICE3_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u +#define DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u +#define GET_DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u +#define DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u +#define GET_DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u +#define DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u +#define GET_DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u +#define DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u +#define DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u +#define GET_DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u +#define DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u +#define GET_DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u +#define DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u +#define GET_DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u +#define DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u +#define GET_DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u +#define DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u +#define GET_DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE3_EMAC_MODE_ENABLE_TCE_SHIFT 21u +#define DEVICE3_EMAC_MODE_ENABLE_TCE_MASK 0x200000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE3_EMAC_MODE_ENABLE_RDE_SHIFT 22u +#define DEVICE3_EMAC_MODE_ENABLE_RDE_MASK 0x400000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE3_EMAC_MODE_ENABLE_FHDE_SHIFT 23u +#define DEVICE3_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) +#define DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u +#define DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u +#define GET_DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) +#define DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u +#define DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u +#define GET_DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u +#define DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u +#define GET_DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u +#define DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) +#define DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u +#define DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u +#define GET_DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u +#define DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u +#define GET_DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE3_LED_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa007040c) /* */ +#define DEVICE3_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u +#define DEVICE3_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u +#define GET_DEVICE3_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_LED_CONTROL_LED_1000_SHIFT 1u +#define DEVICE3_LED_CONTROL_LED_1000_MASK 0x2u +#define GET_DEVICE3_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_LED_CONTROL_LED_100_SHIFT 2u +#define DEVICE3_LED_CONTROL_LED_100_MASK 0x4u +#define GET_DEVICE3_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_LED_CONTROL_LED_10_SHIFT 3u +#define DEVICE3_LED_CONTROL_LED_10_MASK 0x8u +#define GET_DEVICE3_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u +#define DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u +#define GET_DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u +#define DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u +#define GET_DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_LED_CONTROL_LED_TRAFFIC_SHIFT 6u +#define DEVICE3_LED_CONTROL_LED_TRAFFIC_MASK 0x40u +#define GET_DEVICE3_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_LED_CONTROL_LED_STATUS_1000_SHIFT 7u +#define DEVICE3_LED_CONTROL_LED_STATUS_1000_MASK 0x80u +#define GET_DEVICE3_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_LED_CONTROL_LED_STATUS_100_SHIFT 8u +#define DEVICE3_LED_CONTROL_LED_STATUS_100_MASK 0x100u +#define GET_DEVICE3_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_LED_CONTROL_LED_STATUS_10_SHIFT 9u +#define DEVICE3_LED_CONTROL_LED_STATUS_10_MASK 0x200u +#define GET_DEVICE3_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u +#define DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u +#define GET_DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_LED_CONTROL_LED_MODE_SHIFT 11u +#define DEVICE3_LED_CONTROL_LED_MODE_MASK 0x1800u +#define GET_DEVICE3_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) +#define SET_DEVICE3_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) +#define DEVICE3_LED_CONTROL_LED_MODE_MAC 0x0u +#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u +#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u +#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u + +#define DEVICE3_LED_CONTROL_MAC_MODE_SHIFT 13u +#define DEVICE3_LED_CONTROL_MAC_MODE_MASK 0x2000u +#define GET_DEVICE3_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u +#define DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u +#define GET_DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_LED_CONTROL_BLINK_PERIOD_SHIFT 19u +#define DEVICE3_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u +#define GET_DEVICE3_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) +#define SET_DEVICE3_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) +#define DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u +#define DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u +#define GET_DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070410) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070414) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070418) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_1_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007041c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_2_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070420) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_2_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070424) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_3_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070428) /* Upper 2-bytes of this node's MAC address. */ +#define REG_DEVICE3_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007042c) /* Lower 4-byte of this node's MAC address. */ +#define REG_DEVICE3_WOL_PATTERN_POINTER ((volatile APE_DEVICE3_H_uint32_t*)0xa0070430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ +#define REG_DEVICE3_WOL_PATTERN_CFG ((volatile APE_DEVICE3_H_uint32_t*)0xa0070434) /* */ +#define REG_DEVICE3_MTU_SIZE ((volatile APE_DEVICE3_H_uint32_t*)0xa007043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ +#define DEVICE3_MTU_SIZE_MTU_SHIFT 0u +#define DEVICE3_MTU_SIZE_MTU_MASK 0xffffu +#define GET_DEVICE3_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE3_MII_COMMUNICATION ((volatile APE_DEVICE3_H_uint32_t*)0xa007044c) /* */ +#define DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u +#define DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu +#define GET_DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u +#define DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u +#define GET_DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u +#define GET_DEVICE3_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) +#define SET_DEVICE3_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau +#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu + +#define DEVICE3_MII_COMMUNICATION_COMMAND_SHIFT 26u +#define DEVICE3_MII_COMMUNICATION_COMMAND_MASK 0xc000000u +#define GET_DEVICE3_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) +#define SET_DEVICE3_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) +#define DEVICE3_MII_COMMUNICATION_COMMAND_WRITE 0x1u +#define DEVICE3_MII_COMMUNICATION_COMMAND_READ 0x2u + +#define DEVICE3_MII_COMMUNICATION_READ_FAILED_SHIFT 28u +#define DEVICE3_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u +#define GET_DEVICE3_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE3_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) +#define DEVICE3_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u +#define DEVICE3_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u +#define GET_DEVICE3_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE3_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) + +#define REG_DEVICE3_MII_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070454) /* */ +#define DEVICE3_MII_MODE_PHY_ADDRESS_SHIFT 5u +#define DEVICE3_MII_MODE_PHY_ADDRESS_MASK 0x3e0u +#define GET_DEVICE3_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) +#define SET_DEVICE3_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) +#define DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u +#define DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u +#define GET_DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u +#define DEVICE3_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u +#define GET_DEVICE3_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE3_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) + +#define REG_DEVICE3_TRANSMIT_MAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa007045c) /* */ +#define DEVICE3_TRANSMIT_MAC_MODE_RESET_SHIFT 0u +#define DEVICE3_TRANSMIT_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u +#define DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u +#define DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u +#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u +#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) + +#define REG_DEVICE3_RECEIVE_MAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070468) /* */ +#define DEVICE3_RECEIVE_MAC_MODE_RESET_SHIFT 0u +#define DEVICE3_RECEIVE_MAC_MODE_RESET_MASK 0x1u +#define GET_DEVICE3_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u +#define DEVICE3_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE3_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u +#define DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u +#define GET_DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u +#define DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u +#define GET_DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) + +#define REG_DEVICE3_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070540) /* */ +#define DEVICE3_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u +#define DEVICE3_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE3_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE3_PERFECT_MATCH1_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070544) /* */ +#define DEVICE3_PERFECT_MATCH1_LOW_LOW_SHIFT 0u +#define DEVICE3_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE3_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE3_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070548) /* */ +#define DEVICE3_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u +#define DEVICE3_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE3_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE3_PERFECT_MATCH2_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007054c) /* */ +#define DEVICE3_PERFECT_MATCH2_LOW_LOW_SHIFT 0u +#define DEVICE3_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE3_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE3_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070550) /* */ +#define DEVICE3_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u +#define DEVICE3_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE3_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE3_PERFECT_MATCH3_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070554) /* */ +#define DEVICE3_PERFECT_MATCH3_LOW_LOW_SHIFT 0u +#define DEVICE3_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE3_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE3_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070558) /* */ +#define DEVICE3_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u +#define DEVICE3_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu +#define GET_DEVICE3_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) + +#define REG_DEVICE3_PERFECT_MATCH4_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007055c) /* */ +#define DEVICE3_PERFECT_MATCH4_LOW_LOW_SHIFT 0u +#define DEVICE3_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu +#define GET_DEVICE3_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_DEVICE3_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) + +#define REG_DEVICE3_SGMII_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa00705b4) /* This register reflects various status of the respective SGMII port when enabled. */ +#define DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u +#define DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u +#define GET_DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_SGMII_STATUS_LINK_STATUS_SHIFT 1u +#define DEVICE3_SGMII_STATUS_LINK_STATUS_MASK 0x2u +#define GET_DEVICE3_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u +#define DEVICE3_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u +#define GET_DEVICE3_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_SGMII_STATUS_SPEED_1000_SHIFT 3u +#define DEVICE3_SGMII_STATUS_SPEED_1000_MASK 0x8u +#define GET_DEVICE3_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_SGMII_STATUS_SPEED_100_SHIFT 4u +#define DEVICE3_SGMII_STATUS_SPEED_100_MASK 0x10u +#define GET_DEVICE3_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u +#define DEVICE3_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u +#define GET_DEVICE3_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_SGMII_STATUS_PAUSE_RX_SHIFT 6u +#define DEVICE3_SGMII_STATUS_PAUSE_RX_MASK 0x40u +#define GET_DEVICE3_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_SGMII_STATUS_PAUSE_TX_SHIFT 7u +#define DEVICE3_SGMII_STATUS_PAUSE_TX_MASK 0x80u +#define GET_DEVICE3_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u +#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u +#define GET_DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u +#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u + +#define DEVICE3_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u +#define DEVICE3_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u +#define GET_DEVICE3_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u +#define DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u +#define GET_DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u +#define DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u +#define GET_DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE3_CPMU_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0073600) /* */ +#define DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u +#define DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u +#define GET_DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u +#define DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u +#define GET_DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_CPMU_CONTROL_POWER_DOWN_SHIFT 2u +#define DEVICE3_CPMU_CONTROL_POWER_DOWN_MASK 0x4u +#define GET_DEVICE3_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u +#define DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u +#define GET_DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u +#define DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u +#define GET_DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u +#define DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u +#define GET_DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u +#define DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u +#define GET_DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u +#define DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u +#define GET_DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u +#define DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u +#define GET_DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u +#define DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u +#define GET_DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u +#define DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u +#define GET_DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u +#define DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u +#define GET_DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) + +#define REG_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073610) /* */ +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u +#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu + + +#define REG_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073624) /* */ +#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u +#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u +#define GET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) +#define SET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) +#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u +#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u +#define GET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE3_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa007362c) /* */ +#define DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u +#define DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu +#define GET_DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) +#define SET_DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) +#define DEVICE3_STATUS_CPMU_POWER_STATE_SHIFT 4u +#define DEVICE3_STATUS_CPMU_POWER_STATE_MASK 0x70u +#define GET_DEVICE3_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) +#define SET_DEVICE3_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) +#define DEVICE3_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u +#define DEVICE3_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u +#define GET_DEVICE3_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_STATUS_POWER_STATE_SHIFT 8u +#define DEVICE3_STATUS_POWER_STATE_MASK 0x300u +#define GET_DEVICE3_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_STATUS_VMAIN_POWER_STATUS_SHIFT 13u +#define DEVICE3_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u +#define GET_DEVICE3_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u +#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u +#define GET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u +#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u +#define GET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u +#define DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u +#define GET_DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u +#define DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u +#define GET_DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) +#define SET_DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) +#define DEVICE3_STATUS_LINK_IDLE_STATUS_SHIFT 18u +#define DEVICE3_STATUS_LINK_IDLE_STATUS_MASK 0x40000u +#define GET_DEVICE3_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) +#define SET_DEVICE3_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u +#define GET_DEVICE3_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) +#define SET_DEVICE3_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u +#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u + +#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u +#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u +#define GET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u +#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u +#define GET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE3_STATUS_APE_STATUS_SHIFT 23u +#define DEVICE3_STATUS_APE_STATUS_MASK 0x1800000u +#define GET_DEVICE3_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) +#define SET_DEVICE3_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) +#define DEVICE3_STATUS_APE_STATUS_ACTIVE 0x0u +#define DEVICE3_STATUS_APE_STATUS_SLEEP 0x1u +#define DEVICE3_STATUS_APE_STATUS_DEEP_SLEEP 0x2u + +#define DEVICE3_STATUS_FUNCTION_ENABLE_SHIFT 25u +#define DEVICE3_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u +#define GET_DEVICE3_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) +#define SET_DEVICE3_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) +#define DEVICE3_STATUS_FUNCTION_NUMBER_SHIFT 30u +#define DEVICE3_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u +#define GET_DEVICE3_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) +#define SET_DEVICE3_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) + +#define REG_DEVICE3_CLOCK_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0073630) /* */ +#define REG_DEVICE3_GPHY_CONTROL_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0073638) /* */ +#define DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u +#define DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u +#define DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u +#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u +#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u +#define DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u +#define DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u +#define DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u +#define DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u +#define DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u +#define GET_DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) + +#define REG_DEVICE3_CHIP_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0073658) /* */ +#define REG_DEVICE3_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa007365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ +#define REG_DEVICE3_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa0073660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ +#define REG_DEVICE3_GPHY_STRAP ((volatile APE_DEVICE3_H_uint32_t*)0xa0073664) /* */ +#define DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u +#define DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u +#define GET_DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u +#define DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u +#define GET_DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u +#define DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u +#define GET_DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) + +#define REG_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa007367c) /* */ +#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u +#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u +#define GET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u +#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u +#define GET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE3_EEE_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa00736b0) /* */ +#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u +#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u +#define GET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u +#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u +#define GET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u +#define DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u +#define GET_DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u +#define DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u +#define GET_DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u +#define DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u +#define GET_DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u +#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u +#define GET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u +#define DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u +#define GET_DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u +#define DEVICE3_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u +#define GET_DEVICE3_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u +#define DEVICE3_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u +#define GET_DEVICE3_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u +#define DEVICE3_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u +#define GET_DEVICE3_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u +#define DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u +#define GET_DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_EEE_MODE_BLOCK_TIME_SHIFT 11u +#define DEVICE3_EEE_MODE_BLOCK_TIME_MASK 0x7f800u +#define GET_DEVICE3_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) +#define SET_DEVICE3_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) +#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u +#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u +#define GET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) + +#define REG_DEVICE3_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736bc) /* */ +#define DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u +#define DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u +#define GET_DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) + +#define REG_DEVICE3_EEE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736d0) /* */ +#define DEVICE3_EEE_CONTROL_EXIT_TIME_SHIFT 0u +#define DEVICE3_EEE_CONTROL_EXIT_TIME_MASK 0xffffu +#define GET_DEVICE3_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE3_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u +#define DEVICE3_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u +#define GET_DEVICE3_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE3_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE3_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f0) /* */ +#define REG_DEVICE3_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f4) /* */ +#define REG_DEVICE3_MEMORY_ARBITER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074000) /* */ +#define DEVICE3_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u +#define DEVICE3_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE3_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_DEVICE3_BUFFER_MANAGER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074400) /* */ +#define DEVICE3_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u +#define DEVICE3_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u +#define GET_DEVICE3_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u +#define DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u +#define GET_DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u +#define DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u +#define GET_DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) + +#define REG_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0074910) /* */ +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u +#define GET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u + +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u +#define GET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) +#define SET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u +#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u + + +#define REG_DEVICE3_RX_RISC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0075000) /* */ +#define DEVICE3_RX_RISC_MODE_RESET_SHIFT 0u +#define DEVICE3_RX_RISC_MODE_RESET_MASK 0x1u +#define GET_DEVICE3_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u +#define DEVICE3_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u +#define GET_DEVICE3_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u +#define DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u +#define GET_DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u +#define DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u +#define GET_DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u +#define DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u +#define GET_DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_RX_RISC_MODE_ROM_FAIL_SHIFT 6u +#define DEVICE3_RX_RISC_MODE_ROM_FAIL_MASK 0x40u +#define GET_DEVICE3_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u +#define DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u +#define GET_DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u +#define DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u +#define GET_DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u +#define DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u +#define GET_DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_RX_RISC_MODE_HALT_SHIFT 10u +#define DEVICE3_RX_RISC_MODE_HALT_MASK 0x400u +#define GET_DEVICE3_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u +#define DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u +#define GET_DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u +#define DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u +#define GET_DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u +#define DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u +#define GET_DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u +#define DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u +#define GET_DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) + +#define REG_DEVICE3_RX_RISC_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0075004) /* */ +#define DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u +#define DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u +#define GET_DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) +#define DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u +#define DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u +#define GET_DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u +#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u +#define GET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) +#define SET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) +#define DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u +#define DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u +#define GET_DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) +#define SET_DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) +#define DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u +#define DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u +#define GET_DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) +#define DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u +#define DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u +#define GET_DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) +#define SET_DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) +#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u +#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u +#define GET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) +#define SET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) +#define DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u +#define DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u +#define GET_DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) +#define SET_DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) +#define DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u +#define DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u +#define GET_DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u +#define DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u +#define GET_DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_RX_RISC_STATUS_HALTED_SHIFT 10u +#define DEVICE3_RX_RISC_STATUS_HALTED_MASK 0x400u +#define GET_DEVICE3_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_RX_RISC_STATUS_UNKNOWN_SHIFT 11u +#define DEVICE3_RX_RISC_STATUS_UNKNOWN_MASK 0x800u +#define GET_DEVICE3_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE3_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u +#define DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u +#define GET_DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u +#define DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u +#define GET_DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u +#define DEVICE3_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u +#define GET_DEVICE3_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE3_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE3_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE3_H_uint32_t*)0xa007501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ +#define REG_DEVICE3_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE3_H_uint32_t*)0xa0075020) /* This undocumented register contains the current word located at the program counter address loaded in */ +#define REG_DEVICE3_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE3_H_uint32_t*)0xa0075034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ +#define REG_DEVICE3_RX_RISC_REGISTER_0 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075200) /* $zero (R0) */ +#define REG_DEVICE3_RX_RISC_REGISTER_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075204) /* $at (R1) */ +#define REG_DEVICE3_RX_RISC_REGISTER_2 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075208) /* $v0 (R2) */ +#define REG_DEVICE3_RX_RISC_REGISTER_3 ((volatile APE_DEVICE3_H_uint32_t*)0xa007520c) /* $v1 (R3) */ +#define REG_DEVICE3_RX_RISC_REGISTER_4 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075210) /* $a0 (R4) */ +#define REG_DEVICE3_RX_RISC_REGISTER_5 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075214) /* $a1 (R5) */ +#define REG_DEVICE3_RX_RISC_REGISTER_6 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075218) /* $a2 (R6) */ +#define REG_DEVICE3_RX_RISC_REGISTER_7 ((volatile APE_DEVICE3_H_uint32_t*)0xa007521c) /* $a3 (R7) */ +#define REG_DEVICE3_RX_RISC_REGISTER_8 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075220) /* $t0 (R8) */ +#define REG_DEVICE3_RX_RISC_REGISTER_9 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075224) /* $t1 (R9) */ +#define REG_DEVICE3_RX_RISC_REGISTER_10 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075228) /* $t2 (R10) */ +#define REG_DEVICE3_RX_RISC_REGISTER_11 ((volatile APE_DEVICE3_H_uint32_t*)0xa007522c) /* $t3 (R11) */ +#define REG_DEVICE3_RX_RISC_REGISTER_12 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075230) /* $t4 (R12) */ +#define REG_DEVICE3_RX_RISC_REGISTER_13 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075234) /* $t5 (R13) */ +#define REG_DEVICE3_RX_RISC_REGISTER_14 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075238) /* $t6 (R14) */ +#define REG_DEVICE3_RX_RISC_REGISTER_15 ((volatile APE_DEVICE3_H_uint32_t*)0xa007523c) /* $t7 (R15) */ +#define REG_DEVICE3_RX_RISC_REGISTER_16 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075240) /* $s0 (R16) */ +#define REG_DEVICE3_RX_RISC_REGISTER_17 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075244) /* $s1 (R17) */ +#define REG_DEVICE3_RX_RISC_REGISTER_18 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075248) /* $s2 (R18) */ +#define REG_DEVICE3_RX_RISC_REGISTER_19 ((volatile APE_DEVICE3_H_uint32_t*)0xa007524c) /* $s3 (R19) */ +#define REG_DEVICE3_RX_RISC_REGISTER_20 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075250) /* $s4 (R20) */ +#define REG_DEVICE3_RX_RISC_REGISTER_21 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075254) /* $s5 (R21) */ +#define REG_DEVICE3_RX_RISC_REGISTER_22 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075258) /* $s6 (R22) */ +#define REG_DEVICE3_RX_RISC_REGISTER_23 ((volatile APE_DEVICE3_H_uint32_t*)0xa007525c) /* $s7 (R23) */ +#define REG_DEVICE3_RX_RISC_REGISTER_24 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075260) /* $t8 (R24) */ +#define REG_DEVICE3_RX_RISC_REGISTER_25 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075264) /* $t9 (R25) */ +#define REG_DEVICE3_RX_RISC_REGISTER_26 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075268) /* $k0 (R26) */ +#define REG_DEVICE3_RX_RISC_REGISTER_27 ((volatile APE_DEVICE3_H_uint32_t*)0xa007526c) /* $k1 (R27) */ +#define REG_DEVICE3_RX_RISC_REGISTER_28 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075270) /* $gp (R28) */ +#define REG_DEVICE3_RX_RISC_REGISTER_29 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075274) /* $sp (R29) */ +#define REG_DEVICE3_RX_RISC_REGISTER_30 ((volatile APE_DEVICE3_H_uint32_t*)0xa0075278) /* $fp (R30) */ +#define REG_DEVICE3_RX_RISC_REGISTER_31 ((volatile APE_DEVICE3_H_uint32_t*)0xa007527c) /* $ra (R31) */ +#define REG_DEVICE3_6408 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076408) /* */ +#define REG_DEVICE3_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE3_H_uint32_t*)0xa0076410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE3_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE3_H_uint32_t*)0xa0076414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ +#define REG_DEVICE3_PCI_VPD_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa007642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ +#define DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u +#define DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u +#define GET_DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) +#define SET_DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) + +#define REG_DEVICE3_PCI_VPD_RESPONSE ((volatile APE_DEVICE3_H_uint32_t*)0xa0076430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ +#define REG_DEVICE3_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0076434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ +#define DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u +#define DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu +#define GET_DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u +#define DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u +#define GET_DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE3_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0076438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ +#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u +#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu +#define GET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) +#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u +#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u +#define GET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_DEVICE3_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE3_H_uint32_t*)0xa007643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ +#define REG_DEVICE3_64C0 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c0) /* */ +#define REG_DEVICE3_64C8 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c8) /* */ +#define REG_DEVICE3_64DC ((volatile APE_DEVICE3_H_uint32_t*)0xa00764dc) /* */ +#define REG_DEVICE3_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0076504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE3_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0076508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ +#define REG_DEVICE3_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ +#define DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076514) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076518) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE3_H_uint32_t*)0xa007651c) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076520) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076524) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076528) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE3_H_uint32_t*)0xa007652c) /* See */ +#define DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u +#define DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu +#define GET_DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u +#define GET_DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u +#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u +#define DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u +#define GET_DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u +#define GET_DEVICE3_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u +#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u + +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u +#define GET_DEVICE3_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u +#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u + +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u +#define GET_DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u +#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u + + +#define REG_DEVICE3_6530 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076530) /* */ +#define REG_DEVICE3_6550 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ +#define REG_DEVICE3_65F4 ((volatile APE_DEVICE3_H_uint32_t*)0xa00765f4) /* */ +#define REG_DEVICE3_GRC_MODE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076800) /* */ +#define DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u +#define DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u +#define GET_DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) +#define SET_DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u +#define DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u +#define GET_DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) +#define SET_DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u +#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) +#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u +#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u +#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u +#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE3_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE3_H_uint32_t*)0xa0076804) /* */ +#define DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u +#define DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u +#define GET_DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE3_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u +#define DEVICE3_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu +#define GET_DEVICE3_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) +#define SET_DEVICE3_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) + +#define REG_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076808) /* */ +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u +#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u +#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) + +#define REG_DEVICE3_TIMER ((volatile APE_DEVICE3_H_uint32_t*)0xa007680c) /* 32-bit free-running counter */ +#define REG_DEVICE3_RX_CPU_EVENT ((volatile APE_DEVICE3_H_uint32_t*)0xa0076810) /* */ +#define DEVICE3_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u +#define DEVICE3_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u +#define GET_DEVICE3_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_DEVICE3_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) +#define DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u +#define DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u +#define GET_DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) +#define DEVICE3_RX_CPU_EVENT_TIMER_SHIFT 29u +#define DEVICE3_RX_CPU_EVENT_TIMER_MASK 0x20000000u +#define GET_DEVICE3_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_DEVICE3_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) +#define DEVICE3_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u +#define DEVICE3_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE3_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE3_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE3_6838 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076838) /* Unknown. Used by PXE agent. */ +#define REG_DEVICE3_MDI_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ +#define REG_DEVICE3_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE3_H_uint32_t*)0xa007684c) /* */ +#define DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u +#define DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u +#define GET_DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) + +#define REG_DEVICE3_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE3_H_uint32_t*)0xa0076894) /* */ +#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u +#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu +#define GET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) +#define SET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) +#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u +#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u +#define GET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_DEVICE3_EXPANSION_ROM_ADDR ((volatile APE_DEVICE3_H_uint32_t*)0xa00768ec) /* Expansion ROM base address, expect to be d- word aligned. */ +#define REG_DEVICE3_68F0 ((volatile APE_DEVICE3_H_uint32_t*)0xa00768f0) /* */ +#define REG_DEVICE3_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076908) /* */ +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u +#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u + +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u +#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) +#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u +#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) +#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u +#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) +#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u + +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u +#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) +#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u +#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u + + +#define REG_DEVICE3_7C04 ((volatile APE_DEVICE3_H_uint32_t*)0xa0077c04) /* PCIe-related. tg3 driver calls this */ +/** @brief Device Registers, function 3 */ +extern volatile DEVICE_t DEVICE3; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_DEVICE3_H */ + +/** @} */ diff --git a/include/APE_FILTERS1.h b/include/APE_FILTERS1.h new file mode 100644 index 0000000..9474688 --- /dev/null +++ b/include/APE_FILTERS1.h @@ -0,0 +1,195 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS1.h +/// +/// @project ape +/// +/// @brief APE_FILTERS1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_FILTERS1_H APE_FILTERS1 */ +/** @addtogroup APE_FILTERS1_H + * @{ + */ +#ifndef APE_FILTERS1_H +#define APE_FILTERS1_H + +#include <stdint.h> +#include "APE_FILTERS.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_FILTERS1_sim(void* base); +void init_APE_FILTERS1(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_FILTERS1_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_FILTERS1_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS1_H_uint32_t; +#define APE_FILTERS1_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_FILTERS1_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_FILTERS1_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_FILTERS1_H_uint8_t; +typedef uint16_t APE_FILTERS1_H_uint16_t; +typedef uint32_t APE_FILTERS1_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_FILTERS1_BASE ((volatile void*)0xa0058000) /* Management Filter Registers, function 1 */ +#define REG_FILTERS1_SIZE (sizeof(FILTERS_t)) + +#define REG_FILTERS1_ELEMENT_CONFIG ((volatile APE_FILTERS1_H_uint32_t*)0xa0058000) /* Element Configuration Register. */ +#define FILTERS1_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u +#define FILTERS1_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) +#define FILTERS1_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u +#define FILTERS1_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u +#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u + +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_SHIFT 16u +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_EQ 0x0u +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_NE 0x1u +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_GT 0x2u +#define FILTERS1_ELEMENT_CONFIG_RULE_OP_LT 0x3u + +#define FILTERS1_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u +#define FILTERS1_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u +#define FILTERS1_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u +#define FILTERS1_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_P3_SHIFT 27u +#define FILTERS1_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_P2_SHIFT 28u +#define FILTERS1_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_P1_SHIFT 29u +#define FILTERS1_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_AND_SHIFT 30u +#define FILTERS1_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) +#define FILTERS1_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u +#define FILTERS1_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u +#define GET_FILTERS1_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS1_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS1_ELEMENT_PATTERN ((volatile APE_FILTERS1_H_uint32_t*)0xa0058080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ +#define REG_FILTERS1_RULE_CONFIGURATION ((volatile APE_FILTERS1_H_uint32_t*)0xa0058100) /* */ +#define FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u +#define FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u +#define GET_FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) +#define FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u +#define FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u +#define GET_FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS1_RULE_SET ((volatile APE_FILTERS1_H_uint32_t*)0xa0058104) /* */ +#define FILTERS1_RULE_SET_ACTION_SHIFT 0u +#define FILTERS1_RULE_SET_ACTION_MASK 0x3u +#define GET_FILTERS1_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) +#define SET_FILTERS1_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) +#define FILTERS1_RULE_SET_ACTION_TO_APE_ONLY 0x0u +#define FILTERS1_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u +#define FILTERS1_RULE_SET_ACTION_DISCARD 0x2u + +#define FILTERS1_RULE_SET_COUNT_SHIFT 3u +#define FILTERS1_RULE_SET_COUNT_MASK 0x7fff8u +#define GET_FILTERS1_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) +#define SET_FILTERS1_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) +#define FILTERS1_RULE_SET_ENABLE_SHIFT 31u +#define FILTERS1_RULE_SET_ENABLE_MASK 0x80000000u +#define GET_FILTERS1_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS1_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS1_RULE_MASK ((volatile APE_FILTERS1_H_uint32_t*)0xa0058184) /* */ +/** @brief Management Filter Registers, function 1 */ +extern volatile FILTERS_t FILTERS1; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_FILTERS1_H */ + +/** @} */ diff --git a/include/APE_FILTERS2.h b/include/APE_FILTERS2.h new file mode 100644 index 0000000..934df47 --- /dev/null +++ b/include/APE_FILTERS2.h @@ -0,0 +1,195 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS2.h +/// +/// @project ape +/// +/// @brief APE_FILTERS2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_FILTERS2_H APE_FILTERS2 */ +/** @addtogroup APE_FILTERS2_H + * @{ + */ +#ifndef APE_FILTERS2_H +#define APE_FILTERS2_H + +#include <stdint.h> +#include "APE_FILTERS.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_FILTERS2_sim(void* base); +void init_APE_FILTERS2(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_FILTERS2_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_FILTERS2_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS2_H_uint32_t; +#define APE_FILTERS2_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_FILTERS2_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_FILTERS2_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_FILTERS2_H_uint8_t; +typedef uint16_t APE_FILTERS2_H_uint16_t; +typedef uint32_t APE_FILTERS2_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_FILTERS2_BASE ((volatile void*)0xa0068000) /* Management Filter Registers, function 2 */ +#define REG_FILTERS2_SIZE (sizeof(FILTERS_t)) + +#define REG_FILTERS2_ELEMENT_CONFIG ((volatile APE_FILTERS2_H_uint32_t*)0xa0068000) /* Element Configuration Register. */ +#define FILTERS2_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u +#define FILTERS2_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) +#define FILTERS2_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u +#define FILTERS2_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u +#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u + +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_SHIFT 16u +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_EQ 0x0u +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_NE 0x1u +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_GT 0x2u +#define FILTERS2_ELEMENT_CONFIG_RULE_OP_LT 0x3u + +#define FILTERS2_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u +#define FILTERS2_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u +#define FILTERS2_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u +#define FILTERS2_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_P3_SHIFT 27u +#define FILTERS2_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_P2_SHIFT 28u +#define FILTERS2_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_P1_SHIFT 29u +#define FILTERS2_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_AND_SHIFT 30u +#define FILTERS2_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) +#define FILTERS2_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u +#define FILTERS2_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u +#define GET_FILTERS2_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS2_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS2_ELEMENT_PATTERN ((volatile APE_FILTERS2_H_uint32_t*)0xa0068080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ +#define REG_FILTERS2_RULE_CONFIGURATION ((volatile APE_FILTERS2_H_uint32_t*)0xa0068100) /* */ +#define FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u +#define FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u +#define GET_FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) +#define FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u +#define FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u +#define GET_FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS2_RULE_SET ((volatile APE_FILTERS2_H_uint32_t*)0xa0068104) /* */ +#define FILTERS2_RULE_SET_ACTION_SHIFT 0u +#define FILTERS2_RULE_SET_ACTION_MASK 0x3u +#define GET_FILTERS2_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) +#define SET_FILTERS2_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) +#define FILTERS2_RULE_SET_ACTION_TO_APE_ONLY 0x0u +#define FILTERS2_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u +#define FILTERS2_RULE_SET_ACTION_DISCARD 0x2u + +#define FILTERS2_RULE_SET_COUNT_SHIFT 3u +#define FILTERS2_RULE_SET_COUNT_MASK 0x7fff8u +#define GET_FILTERS2_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) +#define SET_FILTERS2_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) +#define FILTERS2_RULE_SET_ENABLE_SHIFT 31u +#define FILTERS2_RULE_SET_ENABLE_MASK 0x80000000u +#define GET_FILTERS2_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS2_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS2_RULE_MASK ((volatile APE_FILTERS2_H_uint32_t*)0xa0068184) /* */ +/** @brief Management Filter Registers, function 2 */ +extern volatile FILTERS_t FILTERS2; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_FILTERS2_H */ + +/** @} */ diff --git a/include/APE_FILTERS3.h b/include/APE_FILTERS3.h new file mode 100644 index 0000000..d01670d --- /dev/null +++ b/include/APE_FILTERS3.h @@ -0,0 +1,195 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS3.h +/// +/// @project ape +/// +/// @brief APE_FILTERS3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_FILTERS3_H APE_FILTERS3 */ +/** @addtogroup APE_FILTERS3_H + * @{ + */ +#ifndef APE_FILTERS3_H +#define APE_FILTERS3_H + +#include <stdint.h> +#include "APE_FILTERS.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_FILTERS3_sim(void* base); +void init_APE_FILTERS3(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_FILTERS3_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_FILTERS3_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS3_H_uint32_t; +#define APE_FILTERS3_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_FILTERS3_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_FILTERS3_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_FILTERS3_H_uint8_t; +typedef uint16_t APE_FILTERS3_H_uint16_t; +typedef uint32_t APE_FILTERS3_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_FILTERS3_BASE ((volatile void*)0xa0078000) /* Management Filter Registers, function 3 */ +#define REG_FILTERS3_SIZE (sizeof(FILTERS_t)) + +#define REG_FILTERS3_ELEMENT_CONFIG ((volatile APE_FILTERS3_H_uint32_t*)0xa0078000) /* Element Configuration Register. */ +#define FILTERS3_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u +#define FILTERS3_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) +#define FILTERS3_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u +#define FILTERS3_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u +#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u + +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_SHIFT 16u +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_EQ 0x0u +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_NE 0x1u +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_GT 0x2u +#define FILTERS3_ELEMENT_CONFIG_RULE_OP_LT 0x3u + +#define FILTERS3_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u +#define FILTERS3_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u +#define FILTERS3_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u +#define FILTERS3_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_P3_SHIFT 27u +#define FILTERS3_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_P2_SHIFT 28u +#define FILTERS3_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_P1_SHIFT 29u +#define FILTERS3_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_AND_SHIFT 30u +#define FILTERS3_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) +#define FILTERS3_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u +#define FILTERS3_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u +#define GET_FILTERS3_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS3_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS3_ELEMENT_PATTERN ((volatile APE_FILTERS3_H_uint32_t*)0xa0078080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ +#define REG_FILTERS3_RULE_CONFIGURATION ((volatile APE_FILTERS3_H_uint32_t*)0xa0078100) /* */ +#define FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u +#define FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u +#define GET_FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) +#define FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u +#define FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u +#define GET_FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS3_RULE_SET ((volatile APE_FILTERS3_H_uint32_t*)0xa0078104) /* */ +#define FILTERS3_RULE_SET_ACTION_SHIFT 0u +#define FILTERS3_RULE_SET_ACTION_MASK 0x3u +#define GET_FILTERS3_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) +#define SET_FILTERS3_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) +#define FILTERS3_RULE_SET_ACTION_TO_APE_ONLY 0x0u +#define FILTERS3_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u +#define FILTERS3_RULE_SET_ACTION_DISCARD 0x2u + +#define FILTERS3_RULE_SET_COUNT_SHIFT 3u +#define FILTERS3_RULE_SET_COUNT_MASK 0x7fff8u +#define GET_FILTERS3_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) +#define SET_FILTERS3_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) +#define FILTERS3_RULE_SET_ENABLE_SHIFT 31u +#define FILTERS3_RULE_SET_ENABLE_MASK 0x80000000u +#define GET_FILTERS3_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_FILTERS3_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_FILTERS3_RULE_MASK ((volatile APE_FILTERS3_H_uint32_t*)0xa0078184) /* */ +/** @brief Management Filter Registers, function 3 */ +extern volatile FILTERS_t FILTERS3; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_FILTERS3_H */ + +/** @} */ diff --git a/include/APE_RX_PORT.h b/include/APE_RX_PORT.h new file mode 100644 index 0000000..d0b2449 --- /dev/null +++ b/include/APE_RX_PORT.h @@ -0,0 +1,175 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT.h +/// +/// @project ape +/// +/// @brief APE_RX_PORT +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_RX_PORT_H APE_RX_PORT */ +/** @addtogroup APE_RX_PORT_H + * @{ + */ +#ifndef APE_RX_PORT_H +#define APE_RX_PORT_H + +#include <stdint.h> + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_RX_PORT_sim(void* base); +void init_APE_RX_PORT(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT_H_uint32_t; +#define APE_RX_PORT_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_RX_PORT_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_RX_PORT_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_RX_PORT_H_uint8_t; +typedef uint16_t APE_RX_PORT_H_uint16_t; +typedef uint32_t APE_RX_PORT_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_RX_PORT_BASE ((volatile void*)0xa0000000) /* RX from network port, function 0 */ +#define REG_RX_PORT_SIZE (sizeof(RX_PORT_t)) + +#define REG_RX_PORT_IN ((volatile APE_RX_PORT_H_uint32_t*)0xa0000000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ +#define RX_PORT_IN_ALL_SHIFT 0u +#define RX_PORT_IN_ALL_MASK 0xffffffffu +#define GET_RX_PORT_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_RX_PORT_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define RX_PORT_IN_ALL_CONTROL_WORD 0x0u +#define RX_PORT_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define RX_PORT_IN_ALL_FIRST_PAYLOAD_WORD 0xcu +#define RX_PORT_IN_ALL_BLOCK_WORDS 0x20u +#define RX_PORT_IN_ALL_BLOCK_BYTES 0x80u + + +/** @brief Register definition for @ref RX_PORT_t.In. */ +typedef register_container RegRX_PORTIn_t { + /** @brief 32bit direct register access. */ + APE_RX_PORT_H_uint32_t r32; + + BITFIELD_BEGIN(APE_RX_PORT_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief All bits */ + BITFIELD_MEMBER(APE_RX_PORT_H_uint32_t, all, 0, 32) +#elif defined(__BIG_ENDIAN__) + /** @brief All bits */ + BITFIELD_MEMBER(APE_RX_PORT_H_uint32_t, all, 0, 32) +#else +#error Unknown Endian +#endif + BITFIELD_END(APE_RX_PORT_H_uint32_t, bits) +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "In"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegRX_PORTIn_t() + { + /** @brief constructor for @ref RX_PORT_t.In. */ + r32.setName("In"); + bits.all.setBaseRegister(&r32); + bits.all.setName("all"); + } + RegRX_PORTIn_t& operator=(const RegRX_PORTIn_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegRX_PORTIn_t; + +/** @brief Component definition for @ref RX_PORT. */ +typedef struct RX_PORT_t { + /** @brief This is the memory range into which frames are directed towards the APE by the hardware. */ + RegRX_PORTIn_t In[4096]; + +#ifdef CXX_SIMULATOR + RX_PORT_t() + { + for(int i = 0; i < 4096; i++) + { + In[i].r32.setComponentOffset(0x0 + (i * 4)); + } + } + typedef uint32_t (*callback_t)(uint32_t, uint32_t, void*); + callback_t mIndexReadCallback; + void* mIndexReadCallbackArgs; + + callback_t mIndexWriteCallback; + void* mIndexWriteCallbackArgs; + + uint32_t read(int offset) { return mIndexReadCallback(0, offset, mIndexReadCallbackArgs); } + void write(int offset, uint32_t value) { (void)mIndexWriteCallback(value, offset, mIndexWriteCallbackArgs); } +#endif /* CXX_SIMULATOR */ +} RX_PORT_t; + +/** @brief RX from network port, function 0 */ +extern volatile RX_PORT_t RX_PORT; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_RX_PORT_H */ + +/** @} */ diff --git a/include/APE_RX_PORT1.h b/include/APE_RX_PORT1.h new file mode 100644 index 0000000..15751c5 --- /dev/null +++ b/include/APE_RX_PORT1.h @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT1.h +/// +/// @project ape +/// +/// @brief APE_RX_PORT1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_RX_PORT1_H APE_RX_PORT1 */ +/** @addtogroup APE_RX_PORT1_H + * @{ + */ +#ifndef APE_RX_PORT1_H +#define APE_RX_PORT1_H + +#include <stdint.h> +#include "APE_RX_PORT.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_RX_PORT1_sim(void* base); +void init_APE_RX_PORT1(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT1_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT1_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT1_H_uint32_t; +#define APE_RX_PORT1_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_RX_PORT1_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_RX_PORT1_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_RX_PORT1_H_uint8_t; +typedef uint16_t APE_RX_PORT1_H_uint16_t; +typedef uint32_t APE_RX_PORT1_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_RX_PORT1_BASE ((volatile void*)0xa0004000) /* RX from network port, function 1 */ +#define REG_RX_PORT1_SIZE (sizeof(RX_PORT_t)) + +#define REG_RX_PORT1_IN ((volatile APE_RX_PORT1_H_uint32_t*)0xa0004000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ +#define RX_PORT1_IN_ALL_SHIFT 0u +#define RX_PORT1_IN_ALL_MASK 0xffffffffu +#define GET_RX_PORT1_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_RX_PORT1_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define RX_PORT1_IN_ALL_CONTROL_WORD 0x0u +#define RX_PORT1_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define RX_PORT1_IN_ALL_FIRST_PAYLOAD_WORD 0xcu +#define RX_PORT1_IN_ALL_BLOCK_WORDS 0x20u +#define RX_PORT1_IN_ALL_BLOCK_BYTES 0x80u + + +/** @brief RX from network port, function 1 */ +extern volatile RX_PORT_t RX_PORT1; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_RX_PORT1_H */ + +/** @} */ diff --git a/include/APE_RX_PORT2.h b/include/APE_RX_PORT2.h new file mode 100644 index 0000000..273f63a --- /dev/null +++ b/include/APE_RX_PORT2.h @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT2.h +/// +/// @project ape +/// +/// @brief APE_RX_PORT2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_RX_PORT2_H APE_RX_PORT2 */ +/** @addtogroup APE_RX_PORT2_H + * @{ + */ +#ifndef APE_RX_PORT2_H +#define APE_RX_PORT2_H + +#include <stdint.h> +#include "APE_RX_PORT.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_RX_PORT2_sim(void* base); +void init_APE_RX_PORT2(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT2_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT2_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT2_H_uint32_t; +#define APE_RX_PORT2_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_RX_PORT2_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_RX_PORT2_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_RX_PORT2_H_uint8_t; +typedef uint16_t APE_RX_PORT2_H_uint16_t; +typedef uint32_t APE_RX_PORT2_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_RX_PORT2_BASE ((volatile void*)0xa0008000) /* RX from network port, function 2 */ +#define REG_RX_PORT2_SIZE (sizeof(RX_PORT_t)) + +#define REG_RX_PORT2_IN ((volatile APE_RX_PORT2_H_uint32_t*)0xa0008000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ +#define RX_PORT2_IN_ALL_SHIFT 0u +#define RX_PORT2_IN_ALL_MASK 0xffffffffu +#define GET_RX_PORT2_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_RX_PORT2_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define RX_PORT2_IN_ALL_CONTROL_WORD 0x0u +#define RX_PORT2_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define RX_PORT2_IN_ALL_FIRST_PAYLOAD_WORD 0xcu +#define RX_PORT2_IN_ALL_BLOCK_WORDS 0x20u +#define RX_PORT2_IN_ALL_BLOCK_BYTES 0x80u + + +/** @brief RX from network port, function 2 */ +extern volatile RX_PORT_t RX_PORT2; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_RX_PORT2_H */ + +/** @} */ diff --git a/include/APE_RX_PORT3.h b/include/APE_RX_PORT3.h new file mode 100644 index 0000000..7a87e79 --- /dev/null +++ b/include/APE_RX_PORT3.h @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT3.h +/// +/// @project ape +/// +/// @brief APE_RX_PORT3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_RX_PORT3_H APE_RX_PORT3 */ +/** @addtogroup APE_RX_PORT3_H + * @{ + */ +#ifndef APE_RX_PORT3_H +#define APE_RX_PORT3_H + +#include <stdint.h> +#include "APE_RX_PORT.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_RX_PORT3_sim(void* base); +void init_APE_RX_PORT3(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT3_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT3_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT3_H_uint32_t; +#define APE_RX_PORT3_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_RX_PORT3_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_RX_PORT3_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_RX_PORT3_H_uint8_t; +typedef uint16_t APE_RX_PORT3_H_uint16_t; +typedef uint32_t APE_RX_PORT3_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_RX_PORT3_BASE ((volatile void*)0xa000c000) /* RX from network port, function 3 */ +#define REG_RX_PORT3_SIZE (sizeof(RX_PORT_t)) + +#define REG_RX_PORT3_IN ((volatile APE_RX_PORT3_H_uint32_t*)0xa000c000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ +#define RX_PORT3_IN_ALL_SHIFT 0u +#define RX_PORT3_IN_ALL_MASK 0xffffffffu +#define GET_RX_PORT3_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_RX_PORT3_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define RX_PORT3_IN_ALL_CONTROL_WORD 0x0u +#define RX_PORT3_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define RX_PORT3_IN_ALL_FIRST_PAYLOAD_WORD 0xcu +#define RX_PORT3_IN_ALL_BLOCK_WORDS 0x20u +#define RX_PORT3_IN_ALL_BLOCK_BYTES 0x80u + + +/** @brief RX from network port, function 3 */ +extern volatile RX_PORT_t RX_PORT3; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_RX_PORT3_H */ + +/** @} */ diff --git a/include/APE_SHM1.h b/include/APE_SHM1.h new file mode 100644 index 0000000..8a5b6b9 --- /dev/null +++ b/include/APE_SHM1.h @@ -0,0 +1,245 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_SHM1.h +/// +/// @project ape +/// +/// @brief APE_SHM1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_SHM1_H APE_SHM1 */ +/** @addtogroup APE_SHM1_H + * @{ + */ +#ifndef APE_SHM1_H +#define APE_SHM1_H + +#include <stdint.h> +#include "APE_SHM.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_SHM1_sim(void* base); +void init_APE_SHM1(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_SHM1_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_SHM1_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_SHM1_H_uint32_t; +#define APE_SHM1_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_SHM1_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_SHM1_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_SHM1_H_uint8_t; +typedef uint16_t APE_SHM1_H_uint16_t; +typedef uint32_t APE_SHM1_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_SHM1_BASE ((volatile void*)0x60221000) /* Device SHM Registers, function 1 */ +#define REG_SHM1_SIZE (sizeof(SHM_t)) + +#define REG_SHM1_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221000) /* APE_APE_MAGIC ('APE!') when all is well. */ +#define SHM1_SEG_SIG_SIG_SHIFT 0u +#define SHM1_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM1_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM1_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM1_SEG_SIG_SIG_LOADER 0x10ad10adu + + +#define REG_SHM1_APE_SEG_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221004) /* Set to 0x34. */ +#define REG_SHM1_FW_STATUS ((volatile APE_SHM1_H_uint32_t*)0x6022100c) /* */ +#define SHM1_FW_STATUS_READY_SHIFT 8u +#define SHM1_FW_STATUS_READY_MASK 0x100u +#define GET_SHM1_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_SHM1_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) +#define SHM1_FW_STATUS_UNKNOWN_31_28_SHIFT 28u +#define SHM1_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u +#define GET_SHM1_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_SHM1_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) + +#define REG_SHM1_FW_FEATURES ((volatile APE_SHM1_H_uint32_t*)0x60221010) /* */ +#define SHM1_FW_FEATURES_NCSI_SHIFT 1u +#define SHM1_FW_FEATURES_NCSI_MASK 0x2u +#define GET_SHM1_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_SHM1_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_SHM1_4014 ((volatile APE_SHM1_H_uint32_t*)0x60221014) /* Unknown. */ +#define REG_SHM1_FW_VERSION ((volatile APE_SHM1_H_uint32_t*)0x60221018) /* */ +#define SHM1_FW_VERSION_BUILD_SHIFT 0u +#define SHM1_FW_VERSION_BUILD_MASK 0xffu +#define GET_SHM1_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_SHM1_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) +#define SHM1_FW_VERSION_REVISION_SHIFT 8u +#define SHM1_FW_VERSION_REVISION_MASK 0xff00u +#define GET_SHM1_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM1_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM1_FW_VERSION_MINOR_SHIFT 16u +#define SHM1_FW_VERSION_MINOR_MASK 0xff0000u +#define GET_SHM1_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_SHM1_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) +#define SHM1_FW_VERSION_MAJOR_SHIFT 24u +#define SHM1_FW_VERSION_MAJOR_MASK 0xff000000u +#define GET_SHM1_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) +#define SET_SHM1_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) + +#define REG_SHM1_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM1_H_uint32_t*)0x6022101c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ +#define REG_SHM1_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221020) /* Specifies the size of the scratchpad area in bytes. */ +#define REG_SHM1_4024 ((volatile APE_SHM1_H_uint32_t*)0x60221024) /* Unknown. Bootcode related. */ +#define REG_SHM1_4028 ((volatile APE_SHM1_H_uint32_t*)0x60221028) /* Unknown. Bootcode related. */ +#define REG_SHM1_LOADER_COMMAND ((volatile APE_SHM1_H_uint32_t*)0x60221038) /* Command sent when using the the APE loader. Zero once handled. */ +#define SHM1_LOADER_COMMAND_COMMAND_SHIFT 0u +#define SHM1_LOADER_COMMAND_COMMAND_MASK 0xffffffffu +#define GET_SHM1_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM1_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM1_LOADER_COMMAND_COMMAND_NOP 0x0u +#define SHM1_LOADER_COMMAND_COMMAND_READ_MEM 0x1u +#define SHM1_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u +#define SHM1_LOADER_COMMAND_COMMAND_CALL 0x3u + + +#define REG_SHM1_LOADER_ARG0 ((volatile APE_SHM1_H_uint32_t*)0x6022103c) /* Argument 0 for the APE loader. */ +#define REG_SHM1_LOADER_ARG1 ((volatile APE_SHM1_H_uint32_t*)0x60221040) /* Argument 1 for the APE loader. */ +#define REG_SHM1_RCPU_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ +#define SHM1_RCPU_SEG_SIG_SIG_SHIFT 0u +#define SHM1_RCPU_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM1_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM1_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM1_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u + + +#define REG_SHM1_RCPU_SEG_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221104) /* Set to 0x34. */ +#define REG_SHM1_RCPU_INIT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221108) /* Incremented by RX CPU every boot. */ +#define REG_SHM1_RCPU_FW_VERSION ((volatile APE_SHM1_H_uint32_t*)0x6022110c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ +#define REG_SHM1_RCPU_CFG_FEATURE ((volatile APE_SHM1_H_uint32_t*)0x60221110) /* Set to */ +#define REG_SHM1_RCPU_PCI_VENDOR_DEVICE_ID ((volatile APE_SHM1_H_uint32_t*)0x60221114) /* Set to PCI Vendor/Device ID by S2. */ +#define REG_SHM1_RCPU_PCI_SUBSYSTEM_ID ((volatile APE_SHM1_H_uint32_t*)0x60221118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */ +#define REG_SHM1_RCPU_APE_RESET_COUNT ((volatile APE_SHM1_H_uint32_t*)0x6022111c) /* Unknown. Incremented by frobnicating routine. */ +#define REG_SHM1_RCPU_LAST_APE_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221120) /* Unknown. Written by frobnicating routine. */ +#define REG_SHM1_RCPU_LAST_APE_FW_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221124) /* Unknown. */ +#define REG_SHM1_RCPU_CFG_HW ((volatile APE_SHM1_H_uint32_t*)0x60221128) /* Set from */ +#define REG_SHM1_RCPU_CFG_HW_2 ((volatile APE_SHM1_H_uint32_t*)0x6022112c) /* Set from */ +#define REG_SHM1_RCPU_CPMU_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221130) /* Set from */ +#define SHM1_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u +#define SHM1_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu +#define GET_SHM1_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_SHM1_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) +#define SHM1_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu + +#define SHM1_RCPU_CPMU_STATUS_STATUS_SHIFT 16u +#define SHM1_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u +#define GET_SHM1_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_SHM1_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_SHM1_HOST_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ +#define REG_SHM1_HOST_SEG_LEN ((volatile APE_SHM1_H_uint32_t*)0x60221204) /* Set to 0x20. */ +#define REG_SHM1_HOST_INIT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221208) /* Incremented by host on every initialization. */ +#define REG_SHM1_HOST_DRIVER_ID ((volatile APE_SHM1_H_uint32_t*)0x6022120c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ +#define REG_SHM1_HOST_BEHAVIOR ((volatile APE_SHM1_H_uint32_t*)0x60221210) /* */ +#define SHM1_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u +#define SHM1_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u +#define GET_SHM1_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_SHM1_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) + +#define REG_SHM1_HEARTBEAT_INTERVAL ((volatile APE_SHM1_H_uint32_t*)0x60221214) /* In milliseconds. Set to 0 to disable heartbeating. */ +#define REG_SHM1_HEARTBEAT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221218) /* */ +#define REG_SHM1_HOST_DRIVER_STATE ((volatile APE_SHM1_H_uint32_t*)0x6022121c) /* */ +#define REG_SHM1_WOL_SPEED ((volatile APE_SHM1_H_uint32_t*)0x60221224) /* */ +#define REG_SHM1_EVENT_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221300) /* */ +#define SHM1_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u +#define SHM1_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u +#define GET_SHM1_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_SHM1_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) +#define SHM1_EVENT_STATUS_COMMAND_SHIFT 8u +#define SHM1_EVENT_STATUS_COMMAND_MASK 0xff00u +#define GET_SHM1_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM1_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM1_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u +#define SHM1_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u +#define SHM1_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u + +#define SHM1_EVENT_STATUS_STATE_SHIFT 16u +#define SHM1_EVENT_STATUS_STATE_MASK 0x70000u +#define GET_SHM1_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) +#define SET_SHM1_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) +#define SHM1_EVENT_STATUS_STATE_START 0x1u +#define SHM1_EVENT_STATUS_STATE_UNLOAD 0x2u +#define SHM1_EVENT_STATUS_STATE_WOL 0x3u +#define SHM1_EVENT_STATUS_STATE_SUSPEND 0x4u + +#define SHM1_EVENT_STATUS_PENDING_SHIFT 31u +#define SHM1_EVENT_STATUS_PENDING_MASK 0x80000000u +#define GET_SHM1_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_SHM1_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_SHM1_PROT_MAGIC ((volatile APE_SHM1_H_uint32_t*)0x60221308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ +#define REG_SHM1_PROT_MAC0_HIGH ((volatile APE_SHM1_H_uint32_t*)0x60221314) /* High 16 bits of MAC address 0. Only valid if */ +#define REG_SHM1_PROT_MAC0_LOW ((volatile APE_SHM1_H_uint32_t*)0x60221318) /* Low 16 bits of MAC address 0. */ +#define REG_SHM1_NCSI_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221800) /* Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only. */ +#define REG_SHM1_NCSI_BUILD_TIME ((volatile APE_SHM1_H_uint32_t*)0x60221810) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM1_NCSI_BUILD_TIME_2 ((volatile APE_SHM1_H_uint32_t*)0x60221814) /* */ +#define REG_SHM1_NCSI_BUILD_TIME_3 ((volatile APE_SHM1_H_uint32_t*)0x60221818) /* */ +#define REG_SHM1_NCSI_BUILD_DATE ((volatile APE_SHM1_H_uint32_t*)0x6022181c) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM1_NCSI_BUILD_DATE_2 ((volatile APE_SHM1_H_uint32_t*)0x60221820) /* */ +#define REG_SHM1_NCSI_BUILD_DATE_3 ((volatile APE_SHM1_H_uint32_t*)0x60221824) /* */ +#define REG_SHM1_CHIP_ID ((volatile APE_SHM1_H_uint32_t*)0x60221890) /* The APE code copies the contents of Chip ID to this word */ +/** @brief Device SHM Registers, function 1 */ +extern volatile SHM_t SHM1; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_SHM1_H */ + +/** @} */ diff --git a/include/APE_SHM2.h b/include/APE_SHM2.h new file mode 100644 index 0000000..313582a --- /dev/null +++ b/include/APE_SHM2.h @@ -0,0 +1,245 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_SHM2.h +/// +/// @project ape +/// +/// @brief APE_SHM2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_SHM2_H APE_SHM2 */ +/** @addtogroup APE_SHM2_H + * @{ + */ +#ifndef APE_SHM2_H +#define APE_SHM2_H + +#include <stdint.h> +#include "APE_SHM.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_SHM2_sim(void* base); +void init_APE_SHM2(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_SHM2_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_SHM2_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_SHM2_H_uint32_t; +#define APE_SHM2_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_SHM2_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_SHM2_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_SHM2_H_uint8_t; +typedef uint16_t APE_SHM2_H_uint16_t; +typedef uint32_t APE_SHM2_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_SHM2_BASE ((volatile void*)0x60222000) /* Device SHM Registers, function 2 */ +#define REG_SHM2_SIZE (sizeof(SHM_t)) + +#define REG_SHM2_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222000) /* APE_APE_MAGIC ('APE!') when all is well. */ +#define SHM2_SEG_SIG_SIG_SHIFT 0u +#define SHM2_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM2_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM2_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM2_SEG_SIG_SIG_LOADER 0x10ad10adu + + +#define REG_SHM2_APE_SEG_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222004) /* Set to 0x34. */ +#define REG_SHM2_FW_STATUS ((volatile APE_SHM2_H_uint32_t*)0x6022200c) /* */ +#define SHM2_FW_STATUS_READY_SHIFT 8u +#define SHM2_FW_STATUS_READY_MASK 0x100u +#define GET_SHM2_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_SHM2_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) +#define SHM2_FW_STATUS_UNKNOWN_31_28_SHIFT 28u +#define SHM2_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u +#define GET_SHM2_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_SHM2_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) + +#define REG_SHM2_FW_FEATURES ((volatile APE_SHM2_H_uint32_t*)0x60222010) /* */ +#define SHM2_FW_FEATURES_NCSI_SHIFT 1u +#define SHM2_FW_FEATURES_NCSI_MASK 0x2u +#define GET_SHM2_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_SHM2_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_SHM2_4014 ((volatile APE_SHM2_H_uint32_t*)0x60222014) /* Unknown. */ +#define REG_SHM2_FW_VERSION ((volatile APE_SHM2_H_uint32_t*)0x60222018) /* */ +#define SHM2_FW_VERSION_BUILD_SHIFT 0u +#define SHM2_FW_VERSION_BUILD_MASK 0xffu +#define GET_SHM2_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_SHM2_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) +#define SHM2_FW_VERSION_REVISION_SHIFT 8u +#define SHM2_FW_VERSION_REVISION_MASK 0xff00u +#define GET_SHM2_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM2_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM2_FW_VERSION_MINOR_SHIFT 16u +#define SHM2_FW_VERSION_MINOR_MASK 0xff0000u +#define GET_SHM2_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_SHM2_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) +#define SHM2_FW_VERSION_MAJOR_SHIFT 24u +#define SHM2_FW_VERSION_MAJOR_MASK 0xff000000u +#define GET_SHM2_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) +#define SET_SHM2_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) + +#define REG_SHM2_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM2_H_uint32_t*)0x6022201c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ +#define REG_SHM2_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222020) /* Specifies the size of the scratchpad area in bytes. */ +#define REG_SHM2_4024 ((volatile APE_SHM2_H_uint32_t*)0x60222024) /* Unknown. Bootcode related. */ +#define REG_SHM2_4028 ((volatile APE_SHM2_H_uint32_t*)0x60222028) /* Unknown. Bootcode related. */ +#define REG_SHM2_LOADER_COMMAND ((volatile APE_SHM2_H_uint32_t*)0x60222038) /* Command sent when using the the APE loader. Zero once handled. */ +#define SHM2_LOADER_COMMAND_COMMAND_SHIFT 0u +#define SHM2_LOADER_COMMAND_COMMAND_MASK 0xffffffffu +#define GET_SHM2_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM2_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM2_LOADER_COMMAND_COMMAND_NOP 0x0u +#define SHM2_LOADER_COMMAND_COMMAND_READ_MEM 0x1u +#define SHM2_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u +#define SHM2_LOADER_COMMAND_COMMAND_CALL 0x3u + + +#define REG_SHM2_LOADER_ARG0 ((volatile APE_SHM2_H_uint32_t*)0x6022203c) /* Argument 0 for the APE loader. */ +#define REG_SHM2_LOADER_ARG1 ((volatile APE_SHM2_H_uint32_t*)0x60222040) /* Argument 1 for the APE loader. */ +#define REG_SHM2_RCPU_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ +#define SHM2_RCPU_SEG_SIG_SIG_SHIFT 0u +#define SHM2_RCPU_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM2_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM2_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM2_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u + + +#define REG_SHM2_RCPU_SEG_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222104) /* Set to 0x34. */ +#define REG_SHM2_RCPU_INIT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222108) /* Incremented by RX CPU every boot. */ +#define REG_SHM2_RCPU_FW_VERSION ((volatile APE_SHM2_H_uint32_t*)0x6022210c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ +#define REG_SHM2_RCPU_CFG_FEATURE ((volatile APE_SHM2_H_uint32_t*)0x60222110) /* Set to */ +#define REG_SHM2_RCPU_PCI_VENDOR_DEVICE_ID ((volatile APE_SHM2_H_uint32_t*)0x60222114) /* Set to PCI Vendor/Device ID by S2. */ +#define REG_SHM2_RCPU_PCI_SUBSYSTEM_ID ((volatile APE_SHM2_H_uint32_t*)0x60222118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */ +#define REG_SHM2_RCPU_APE_RESET_COUNT ((volatile APE_SHM2_H_uint32_t*)0x6022211c) /* Unknown. Incremented by frobnicating routine. */ +#define REG_SHM2_RCPU_LAST_APE_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222120) /* Unknown. Written by frobnicating routine. */ +#define REG_SHM2_RCPU_LAST_APE_FW_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222124) /* Unknown. */ +#define REG_SHM2_RCPU_CFG_HW ((volatile APE_SHM2_H_uint32_t*)0x60222128) /* Set from */ +#define REG_SHM2_RCPU_CFG_HW_2 ((volatile APE_SHM2_H_uint32_t*)0x6022212c) /* Set from */ +#define REG_SHM2_RCPU_CPMU_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222130) /* Set from */ +#define SHM2_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u +#define SHM2_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu +#define GET_SHM2_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_SHM2_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) +#define SHM2_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu + +#define SHM2_RCPU_CPMU_STATUS_STATUS_SHIFT 16u +#define SHM2_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u +#define GET_SHM2_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_SHM2_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_SHM2_HOST_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ +#define REG_SHM2_HOST_SEG_LEN ((volatile APE_SHM2_H_uint32_t*)0x60222204) /* Set to 0x20. */ +#define REG_SHM2_HOST_INIT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222208) /* Incremented by host on every initialization. */ +#define REG_SHM2_HOST_DRIVER_ID ((volatile APE_SHM2_H_uint32_t*)0x6022220c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ +#define REG_SHM2_HOST_BEHAVIOR ((volatile APE_SHM2_H_uint32_t*)0x60222210) /* */ +#define SHM2_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u +#define SHM2_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u +#define GET_SHM2_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_SHM2_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) + +#define REG_SHM2_HEARTBEAT_INTERVAL ((volatile APE_SHM2_H_uint32_t*)0x60222214) /* In milliseconds. Set to 0 to disable heartbeating. */ +#define REG_SHM2_HEARTBEAT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222218) /* */ +#define REG_SHM2_HOST_DRIVER_STATE ((volatile APE_SHM2_H_uint32_t*)0x6022221c) /* */ +#define REG_SHM2_WOL_SPEED ((volatile APE_SHM2_H_uint32_t*)0x60222224) /* */ +#define REG_SHM2_EVENT_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222300) /* */ +#define SHM2_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u +#define SHM2_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u +#define GET_SHM2_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_SHM2_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) +#define SHM2_EVENT_STATUS_COMMAND_SHIFT 8u +#define SHM2_EVENT_STATUS_COMMAND_MASK 0xff00u +#define GET_SHM2_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM2_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM2_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u +#define SHM2_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u +#define SHM2_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u + +#define SHM2_EVENT_STATUS_STATE_SHIFT 16u +#define SHM2_EVENT_STATUS_STATE_MASK 0x70000u +#define GET_SHM2_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) +#define SET_SHM2_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) +#define SHM2_EVENT_STATUS_STATE_START 0x1u +#define SHM2_EVENT_STATUS_STATE_UNLOAD 0x2u +#define SHM2_EVENT_STATUS_STATE_WOL 0x3u +#define SHM2_EVENT_STATUS_STATE_SUSPEND 0x4u + +#define SHM2_EVENT_STATUS_PENDING_SHIFT 31u +#define SHM2_EVENT_STATUS_PENDING_MASK 0x80000000u +#define GET_SHM2_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_SHM2_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_SHM2_PROT_MAGIC ((volatile APE_SHM2_H_uint32_t*)0x60222308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ +#define REG_SHM2_PROT_MAC0_HIGH ((volatile APE_SHM2_H_uint32_t*)0x60222314) /* High 16 bits of MAC address 0. Only valid if */ +#define REG_SHM2_PROT_MAC0_LOW ((volatile APE_SHM2_H_uint32_t*)0x60222318) /* Low 16 bits of MAC address 0. */ +#define REG_SHM2_NCSI_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222800) /* Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only. */ +#define REG_SHM2_NCSI_BUILD_TIME ((volatile APE_SHM2_H_uint32_t*)0x60222810) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM2_NCSI_BUILD_TIME_2 ((volatile APE_SHM2_H_uint32_t*)0x60222814) /* */ +#define REG_SHM2_NCSI_BUILD_TIME_3 ((volatile APE_SHM2_H_uint32_t*)0x60222818) /* */ +#define REG_SHM2_NCSI_BUILD_DATE ((volatile APE_SHM2_H_uint32_t*)0x6022281c) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM2_NCSI_BUILD_DATE_2 ((volatile APE_SHM2_H_uint32_t*)0x60222820) /* */ +#define REG_SHM2_NCSI_BUILD_DATE_3 ((volatile APE_SHM2_H_uint32_t*)0x60222824) /* */ +#define REG_SHM2_CHIP_ID ((volatile APE_SHM2_H_uint32_t*)0x60222890) /* The APE code copies the contents of Chip ID to this word */ +/** @brief Device SHM Registers, function 2 */ +extern volatile SHM_t SHM2; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_SHM2_H */ + +/** @} */ diff --git a/include/APE_SHM3.h b/include/APE_SHM3.h new file mode 100644 index 0000000..914c1ad --- /dev/null +++ b/include/APE_SHM3.h @@ -0,0 +1,245 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_SHM3.h +/// +/// @project ape +/// +/// @brief APE_SHM3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +/** @defgroup APE_SHM3_H APE_SHM3 */ +/** @addtogroup APE_SHM3_H + * @{ + */ +#ifndef APE_SHM3_H +#define APE_SHM3_H + +#include <stdint.h> +#include "APE_SHM.h" + +#ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ +void init_APE_SHM3_sim(void* base); +void init_APE_SHM3(void); + +#include <CXXRegister.h> +typedef CXXRegister<uint8_t, 0, 8> APE_SHM3_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_SHM3_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_SHM3_H_uint32_t; +#define APE_SHM3_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_SHM3_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_SHM3_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +#define register_container struct +#define volatile +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__##_bitfield(__offset__, __bits__) __name__; +#define BITFIELD_END(__type__, __name__) } __name__; + +#else /* Firmware Data types */ +typedef uint8_t APE_SHM3_H_uint8_t; +typedef uint16_t APE_SHM3_H_uint16_t; +typedef uint32_t APE_SHM3_H_uint32_t; +#define register_container union +#define BITFIELD_BEGIN(__type__, __name__) struct { +#define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; +#define BITFIELD_END(__type__, __name__) } __name__; +#endif /* !CXX_SIMULATOR */ + +#define REG_SHM3_BASE ((volatile void*)0x60223000) /* Device SHM Registers, function 3 */ +#define REG_SHM3_SIZE (sizeof(SHM_t)) + +#define REG_SHM3_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223000) /* APE_APE_MAGIC ('APE!') when all is well. */ +#define SHM3_SEG_SIG_SIG_SHIFT 0u +#define SHM3_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM3_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM3_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM3_SEG_SIG_SIG_LOADER 0x10ad10adu + + +#define REG_SHM3_APE_SEG_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223004) /* Set to 0x34. */ +#define REG_SHM3_FW_STATUS ((volatile APE_SHM3_H_uint32_t*)0x6022300c) /* */ +#define SHM3_FW_STATUS_READY_SHIFT 8u +#define SHM3_FW_STATUS_READY_MASK 0x100u +#define GET_SHM3_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) +#define SET_SHM3_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) +#define SHM3_FW_STATUS_UNKNOWN_31_28_SHIFT 28u +#define SHM3_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u +#define GET_SHM3_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) +#define SET_SHM3_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) + +#define REG_SHM3_FW_FEATURES ((volatile APE_SHM3_H_uint32_t*)0x60223010) /* */ +#define SHM3_FW_FEATURES_NCSI_SHIFT 1u +#define SHM3_FW_FEATURES_NCSI_MASK 0x2u +#define GET_SHM3_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_SHM3_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) + +#define REG_SHM3_4014 ((volatile APE_SHM3_H_uint32_t*)0x60223014) /* Unknown. */ +#define REG_SHM3_FW_VERSION ((volatile APE_SHM3_H_uint32_t*)0x60223018) /* */ +#define SHM3_FW_VERSION_BUILD_SHIFT 0u +#define SHM3_FW_VERSION_BUILD_MASK 0xffu +#define GET_SHM3_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) +#define SET_SHM3_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) +#define SHM3_FW_VERSION_REVISION_SHIFT 8u +#define SHM3_FW_VERSION_REVISION_MASK 0xff00u +#define GET_SHM3_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM3_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM3_FW_VERSION_MINOR_SHIFT 16u +#define SHM3_FW_VERSION_MINOR_MASK 0xff0000u +#define GET_SHM3_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) +#define SET_SHM3_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) +#define SHM3_FW_VERSION_MAJOR_SHIFT 24u +#define SHM3_FW_VERSION_MAJOR_MASK 0xff000000u +#define GET_SHM3_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) +#define SET_SHM3_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) + +#define REG_SHM3_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM3_H_uint32_t*)0x6022301c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ +#define REG_SHM3_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223020) /* Specifies the size of the scratchpad area in bytes. */ +#define REG_SHM3_4024 ((volatile APE_SHM3_H_uint32_t*)0x60223024) /* Unknown. Bootcode related. */ +#define REG_SHM3_4028 ((volatile APE_SHM3_H_uint32_t*)0x60223028) /* Unknown. Bootcode related. */ +#define REG_SHM3_LOADER_COMMAND ((volatile APE_SHM3_H_uint32_t*)0x60223038) /* Command sent when using the the APE loader. Zero once handled. */ +#define SHM3_LOADER_COMMAND_COMMAND_SHIFT 0u +#define SHM3_LOADER_COMMAND_COMMAND_MASK 0xffffffffu +#define GET_SHM3_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM3_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM3_LOADER_COMMAND_COMMAND_NOP 0x0u +#define SHM3_LOADER_COMMAND_COMMAND_READ_MEM 0x1u +#define SHM3_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u +#define SHM3_LOADER_COMMAND_COMMAND_CALL 0x3u + + +#define REG_SHM3_LOADER_ARG0 ((volatile APE_SHM3_H_uint32_t*)0x6022303c) /* Argument 0 for the APE loader. */ +#define REG_SHM3_LOADER_ARG1 ((volatile APE_SHM3_H_uint32_t*)0x60223040) /* Argument 1 for the APE loader. */ +#define REG_SHM3_RCPU_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ +#define SHM3_RCPU_SEG_SIG_SIG_SHIFT 0u +#define SHM3_RCPU_SEG_SIG_SIG_MASK 0xffffffffu +#define GET_SHM3_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_SHM3_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) +#define SHM3_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u + + +#define REG_SHM3_RCPU_SEG_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223104) /* Set to 0x34. */ +#define REG_SHM3_RCPU_INIT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223108) /* Incremented by RX CPU every boot. */ +#define REG_SHM3_RCPU_FW_VERSION ((volatile APE_SHM3_H_uint32_t*)0x6022310c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ +#define REG_SHM3_RCPU_CFG_FEATURE ((volatile APE_SHM3_H_uint32_t*)0x60223110) /* Set to */ +#define REG_SHM3_RCPU_PCI_VENDOR_DEVICE_ID ((volatile APE_SHM3_H_uint32_t*)0x60223114) /* Set to PCI Vendor/Device ID by S2. */ +#define REG_SHM3_RCPU_PCI_SUBSYSTEM_ID ((volatile APE_SHM3_H_uint32_t*)0x60223118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */ +#define REG_SHM3_RCPU_APE_RESET_COUNT ((volatile APE_SHM3_H_uint32_t*)0x6022311c) /* Unknown. Incremented by frobnicating routine. */ +#define REG_SHM3_RCPU_LAST_APE_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223120) /* Unknown. Written by frobnicating routine. */ +#define REG_SHM3_RCPU_LAST_APE_FW_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223124) /* Unknown. */ +#define REG_SHM3_RCPU_CFG_HW ((volatile APE_SHM3_H_uint32_t*)0x60223128) /* Set from */ +#define REG_SHM3_RCPU_CFG_HW_2 ((volatile APE_SHM3_H_uint32_t*)0x6022312c) /* Set from */ +#define REG_SHM3_RCPU_CPMU_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223130) /* Set from */ +#define SHM3_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u +#define SHM3_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu +#define GET_SHM3_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) +#define SET_SHM3_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) +#define SHM3_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu + +#define SHM3_RCPU_CPMU_STATUS_STATUS_SHIFT 16u +#define SHM3_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u +#define GET_SHM3_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) +#define SET_SHM3_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) + +#define REG_SHM3_HOST_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ +#define REG_SHM3_HOST_SEG_LEN ((volatile APE_SHM3_H_uint32_t*)0x60223204) /* Set to 0x20. */ +#define REG_SHM3_HOST_INIT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223208) /* Incremented by host on every initialization. */ +#define REG_SHM3_HOST_DRIVER_ID ((volatile APE_SHM3_H_uint32_t*)0x6022320c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ +#define REG_SHM3_HOST_BEHAVIOR ((volatile APE_SHM3_H_uint32_t*)0x60223210) /* */ +#define SHM3_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u +#define SHM3_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u +#define GET_SHM3_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) +#define SET_SHM3_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) + +#define REG_SHM3_HEARTBEAT_INTERVAL ((volatile APE_SHM3_H_uint32_t*)0x60223214) /* In milliseconds. Set to 0 to disable heartbeating. */ +#define REG_SHM3_HEARTBEAT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223218) /* */ +#define REG_SHM3_HOST_DRIVER_STATE ((volatile APE_SHM3_H_uint32_t*)0x6022321c) /* */ +#define REG_SHM3_WOL_SPEED ((volatile APE_SHM3_H_uint32_t*)0x60223224) /* */ +#define REG_SHM3_EVENT_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223300) /* */ +#define SHM3_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u +#define SHM3_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u +#define GET_SHM3_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) +#define SET_SHM3_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) +#define SHM3_EVENT_STATUS_COMMAND_SHIFT 8u +#define SHM3_EVENT_STATUS_COMMAND_MASK 0xff00u +#define GET_SHM3_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) +#define SET_SHM3_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) +#define SHM3_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u +#define SHM3_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u +#define SHM3_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u + +#define SHM3_EVENT_STATUS_STATE_SHIFT 16u +#define SHM3_EVENT_STATUS_STATE_MASK 0x70000u +#define GET_SHM3_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) +#define SET_SHM3_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) +#define SHM3_EVENT_STATUS_STATE_START 0x1u +#define SHM3_EVENT_STATUS_STATE_UNLOAD 0x2u +#define SHM3_EVENT_STATUS_STATE_WOL 0x3u +#define SHM3_EVENT_STATUS_STATE_SUSPEND 0x4u + +#define SHM3_EVENT_STATUS_PENDING_SHIFT 31u +#define SHM3_EVENT_STATUS_PENDING_MASK 0x80000000u +#define GET_SHM3_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_SHM3_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) + +#define REG_SHM3_PROT_MAGIC ((volatile APE_SHM3_H_uint32_t*)0x60223308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ +#define REG_SHM3_PROT_MAC0_HIGH ((volatile APE_SHM3_H_uint32_t*)0x60223314) /* High 16 bits of MAC address 0. Only valid if */ +#define REG_SHM3_PROT_MAC0_LOW ((volatile APE_SHM3_H_uint32_t*)0x60223318) /* Low 16 bits of MAC address 0. */ +#define REG_SHM3_NCSI_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223800) /* Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only. */ +#define REG_SHM3_NCSI_BUILD_TIME ((volatile APE_SHM3_H_uint32_t*)0x60223810) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM3_NCSI_BUILD_TIME_2 ((volatile APE_SHM3_H_uint32_t*)0x60223814) /* */ +#define REG_SHM3_NCSI_BUILD_TIME_3 ((volatile APE_SHM3_H_uint32_t*)0x60223818) /* */ +#define REG_SHM3_NCSI_BUILD_DATE ((volatile APE_SHM3_H_uint32_t*)0x6022381c) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ +#define REG_SHM3_NCSI_BUILD_DATE_2 ((volatile APE_SHM3_H_uint32_t*)0x60223820) /* */ +#define REG_SHM3_NCSI_BUILD_DATE_3 ((volatile APE_SHM3_H_uint32_t*)0x60223824) /* */ +#define REG_SHM3_CHIP_ID ((volatile APE_SHM3_H_uint32_t*)0x60223890) /* The APE code copies the contents of Chip ID to this word */ +/** @brief Device SHM Registers, function 3 */ +extern volatile SHM_t SHM3; + + + +#ifdef CXX_SIMULATOR /* Compiling c++ code - uses register wrappers */ +#undef volatile +#endif /* CXX_SIMULATOR */ + +#undef register_container +#undef BITFIELD_BEGIN +#undef BITFIELD_MEMBER +#undef BITFIELD_END + +#endif /* !APE_SHM3_H */ + +/** @} */ diff --git a/include/APE_TX_PORT.h b/include/APE_TX_PORT.h index 91520de..33a127d 100644 --- a/include/APE_TX_PORT.h +++ b/include/APE_TX_PORT.h @@ -81,11 +81,16 @@ typedef uint32_t APE_TX_PORT_H_uint32_t; #define REG_TX_PORT_BASE ((volatile void*)0xa0020000) /* TX to network port, function 0 */ #define REG_TX_PORT_SIZE (sizeof(TX_PORT_t)) -#define REG_TX_PORT_OUT ((volatile APE_TX_PORT_H_uint32_t*)0xa0020000) /* This is the memory range into which frames are directed towards the network byte the APE firmware. */ +#define REG_TX_PORT_OUT ((volatile APE_TX_PORT_H_uint32_t*)0xa0020000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ #define TX_PORT_OUT_ALL_SHIFT 0u #define TX_PORT_OUT_ALL_MASK 0xffffffffu #define GET_TX_PORT_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_TX_PORT_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define TX_PORT_OUT_ALL_CONTROL_WORD 0x0u +#define TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define TX_PORT_OUT_ALL_FRAME_LEN_WORD 0x3u +#define TX_PORT_OUT_ALL_NUM_BLOCKS_WORD 0x9u +#define TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu #define TX_PORT_OUT_ALL_BLOCK_WORDS 0x20u #define TX_PORT_OUT_ALL_BLOCK_BYTES 0x80u @@ -130,7 +135,7 @@ typedef register_container RegTX_PORTOut_t { /** @brief Component definition for @ref TX_PORT. */ typedef struct TX_PORT_t { - /** @brief This is the memory range into which frames are directed towards the network byte the APE firmware. */ + /** @brief This is the memory range into which frames are directed towards the network by the APE firmware. */ RegTX_PORTOut_t Out[2048]; #ifdef CXX_SIMULATOR diff --git a/include/APE_TX_PORT1.h b/include/APE_TX_PORT1.h index 00550a4..aa8fedb 100644 --- a/include/APE_TX_PORT1.h +++ b/include/APE_TX_PORT1.h @@ -82,11 +82,16 @@ typedef uint32_t APE_TX_PORT1_H_uint32_t; #define REG_TX_PORT1_BASE ((volatile void*)0xa0022000) /* TX to network port, function 1 */ #define REG_TX_PORT1_SIZE (sizeof(TX_PORT_t)) -#define REG_TX_PORT1_OUT ((volatile APE_TX_PORT1_H_uint32_t*)0xa0022000) /* This is the memory range into which frames are directed towards the network byte the APE firmware. */ +#define REG_TX_PORT1_OUT ((volatile APE_TX_PORT1_H_uint32_t*)0xa0022000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ #define TX_PORT1_OUT_ALL_SHIFT 0u #define TX_PORT1_OUT_ALL_MASK 0xffffffffu #define GET_TX_PORT1_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_TX_PORT1_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define TX_PORT1_OUT_ALL_CONTROL_WORD 0x0u +#define TX_PORT1_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define TX_PORT1_OUT_ALL_FRAME_LEN_WORD 0x3u +#define TX_PORT1_OUT_ALL_NUM_BLOCKS_WORD 0x9u +#define TX_PORT1_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu #define TX_PORT1_OUT_ALL_BLOCK_WORDS 0x20u #define TX_PORT1_OUT_ALL_BLOCK_BYTES 0x80u diff --git a/include/APE_TX_PORT2.h b/include/APE_TX_PORT2.h index 28c2333..d37310c 100644 --- a/include/APE_TX_PORT2.h +++ b/include/APE_TX_PORT2.h @@ -82,11 +82,16 @@ typedef uint32_t APE_TX_PORT2_H_uint32_t; #define REG_TX_PORT2_BASE ((volatile void*)0xa0024000) /* TX to network port, function 2 */ #define REG_TX_PORT2_SIZE (sizeof(TX_PORT_t)) -#define REG_TX_PORT2_OUT ((volatile APE_TX_PORT2_H_uint32_t*)0xa0024000) /* This is the memory range into which frames are directed towards the network byte the APE firmware. */ +#define REG_TX_PORT2_OUT ((volatile APE_TX_PORT2_H_uint32_t*)0xa0024000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ #define TX_PORT2_OUT_ALL_SHIFT 0u #define TX_PORT2_OUT_ALL_MASK 0xffffffffu #define GET_TX_PORT2_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_TX_PORT2_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define TX_PORT2_OUT_ALL_CONTROL_WORD 0x0u +#define TX_PORT2_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define TX_PORT2_OUT_ALL_FRAME_LEN_WORD 0x3u +#define TX_PORT2_OUT_ALL_NUM_BLOCKS_WORD 0x9u +#define TX_PORT2_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu #define TX_PORT2_OUT_ALL_BLOCK_WORDS 0x20u #define TX_PORT2_OUT_ALL_BLOCK_BYTES 0x80u diff --git a/include/APE_TX_PORT3.h b/include/APE_TX_PORT3.h index 55c3472..3dd308f 100644 --- a/include/APE_TX_PORT3.h +++ b/include/APE_TX_PORT3.h @@ -82,11 +82,16 @@ typedef uint32_t APE_TX_PORT3_H_uint32_t; #define REG_TX_PORT3_BASE ((volatile void*)0xa0026000) /* TX to network port, function 3 */ #define REG_TX_PORT3_SIZE (sizeof(TX_PORT_t)) -#define REG_TX_PORT3_OUT ((volatile APE_TX_PORT3_H_uint32_t*)0xa0026000) /* This is the memory range into which frames are directed towards the network byte the APE firmware. */ +#define REG_TX_PORT3_OUT ((volatile APE_TX_PORT3_H_uint32_t*)0xa0026000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ #define TX_PORT3_OUT_ALL_SHIFT 0u #define TX_PORT3_OUT_ALL_MASK 0xffffffffu #define GET_TX_PORT3_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) #define SET_TX_PORT3_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define TX_PORT3_OUT_ALL_CONTROL_WORD 0x0u +#define TX_PORT3_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u +#define TX_PORT3_OUT_ALL_FRAME_LEN_WORD 0x3u +#define TX_PORT3_OUT_ALL_NUM_BLOCKS_WORD 0x9u +#define TX_PORT3_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu #define TX_PORT3_OUT_ALL_BLOCK_WORDS 0x20u #define TX_PORT3_OUT_ALL_BLOCK_BYTES 0x80u diff --git a/include/bcm5719_APE.h b/include/bcm5719_APE.h index 97ed431..b68518f 100644 --- a/include/bcm5719_APE.h +++ b/include/bcm5719_APE.h @@ -118,6 +118,14 @@ typedef uint32_t BCM5719_APE_H_uint32_t; #define APE_MODE_SWAP_ARB_DWORD_MASK 0x800u #define GET_APE_MODE_SWAP_ARB_DWORD(__reg__) (((__reg__) & 0x800) >> 11u) #define SET_APE_MODE_SWAP_ARB_DWORD(__val__) (((__val__) << 11u) & 0x800u) +#define APE_MODE_CHANNEL_0_ENABLE_SHIFT 14u +#define APE_MODE_CHANNEL_0_ENABLE_MASK 0x4000u +#define GET_APE_MODE_CHANNEL_0_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) +#define SET_APE_MODE_CHANNEL_0_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) +#define APE_MODE_CHANNEL_2_ENABLE_SHIFT 15u +#define APE_MODE_CHANNEL_2_ENABLE_MASK 0x8000u +#define GET_APE_MODE_CHANNEL_2_ENABLE(__reg__) (((__reg__) & 0x8000) >> 15u) +#define SET_APE_MODE_CHANNEL_2_ENABLE(__val__) (((__val__) << 15u) & 0x8000u) #define APE_MODE_MEMORY_ECC_SHIFT 18u #define APE_MODE_MEMORY_ECC_MASK 0x40000u #define GET_APE_MODE_MEMORY_ECC(__reg__) (((__reg__) & 0x40000) >> 18u) @@ -126,6 +134,14 @@ typedef uint32_t BCM5719_APE_H_uint32_t; #define APE_MODE_ICODE_PIP_RD_DISABLE_MASK 0x80000u #define GET_APE_MODE_ICODE_PIP_RD_DISABLE(__reg__) (((__reg__) & 0x80000) >> 19u) #define SET_APE_MODE_ICODE_PIP_RD_DISABLE(__val__) (((__val__) << 19u) & 0x80000u) +#define APE_MODE_CHANNEL_1_ENABLE_SHIFT 30u +#define APE_MODE_CHANNEL_1_ENABLE_MASK 0x40000000u +#define GET_APE_MODE_CHANNEL_1_ENABLE(__reg__) (((__reg__) & 0x40000000) >> 30u) +#define SET_APE_MODE_CHANNEL_1_ENABLE(__val__) (((__val__) << 30u) & 0x40000000u) +#define APE_MODE_CHANNEL_3_ENABLE_SHIFT 31u +#define APE_MODE_CHANNEL_3_ENABLE_MASK 0x80000000u +#define GET_APE_MODE_CHANNEL_3_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_APE_MODE_CHANNEL_3_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.Mode. */ typedef register_container RegAPEMode_t { @@ -159,22 +175,42 @@ typedef register_container RegAPEMode_t { /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SwapARBdword, 11, 1) /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_17_12, 12, 6) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_12, 12, 2) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel0Enable, 14, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel2Enable, 15, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_17_16, 16, 2) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MemoryECC, 18, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ICodePIPRdDisable, 19, 1) /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_20, 20, 12) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_29_20, 20, 10) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel1Enable, 30, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel3Enable, 31, 1) #elif defined(__BIG_ENDIAN__) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel3Enable, 31, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel1Enable, 30, 1) /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_20, 20, 12) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_29_20, 20, 10) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ICodePIPRdDisable, 19, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MemoryECC, 18, 1) /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_17_12, 12, 6) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_17_16, 16, 2) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel2Enable, 15, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Channel0Enable, 14, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_12, 12, 2) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SwapARBdword, 11, 1) /** @brief Padding */ @@ -232,10 +268,18 @@ typedef register_container RegAPEMode_t { bits.SwapATBdword.setName("SwapATBdword"); bits.SwapARBdword.setBaseRegister(&r32); bits.SwapARBdword.setName("SwapARBdword"); + bits.Channel0Enable.setBaseRegister(&r32); + bits.Channel0Enable.setName("Channel0Enable"); + bits.Channel2Enable.setBaseRegister(&r32); + bits.Channel2Enable.setName("Channel2Enable"); bits.MemoryECC.setBaseRegister(&r32); bits.MemoryECC.setName("MemoryECC"); bits.ICodePIPRdDisable.setBaseRegister(&r32); bits.ICodePIPRdDisable.setName("ICodePIPRdDisable"); + bits.Channel1Enable.setBaseRegister(&r32); + bits.Channel1Enable.setName("Channel1Enable"); + bits.Channel3Enable.setBaseRegister(&r32); + bits.Channel3Enable.setName("Channel3Enable"); } RegAPEMode_t& operator=(const RegAPEMode_t& other) { @@ -489,6 +533,10 @@ typedef register_container RegAPEEvent_t { #define APE_RXBUFOFFSET_FUNC0_VALID_MASK 0x40000000u #define GET_APE_RXBUFOFFSET_FUNC0_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) #define SET_APE_RXBUFOFFSET_FUNC0_VALID(__val__) (((__val__) << 30u) & 0x40000000u) +#define APE_RXBUFOFFSET_FUNC0_FINISHED_SHIFT 31u +#define APE_RXBUFOFFSET_FUNC0_FINISHED_MASK 0x80000000u +#define GET_APE_RXBUFOFFSET_FUNC0_FINISHED(__reg__) (((__reg__) & 0x80000000) >> 31u) +#define SET_APE_RXBUFOFFSET_FUNC0_FINISHED(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.RxbufoffsetFunc0. */ typedef register_container RegAPERxbufoffsetFunc0_t { @@ -509,11 +557,11 @@ typedef register_container RegAPERxbufoffsetFunc0_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Finished, 31, 1) #elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Finished, 31, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) /** @brief */ @@ -553,6 +601,8 @@ typedef register_container RegAPERxbufoffsetFunc0_t { bits.Count.setName("Count"); bits.Valid.setBaseRegister(&r32); bits.Valid.setName("Valid"); + bits.Finished.setBaseRegister(&r32); + bits.Finished.setName("Finished"); } RegAPERxbufoffsetFunc0_t& operator=(const RegAPERxbufoffsetFunc0_t& other) { @@ -670,9 +720,13 @@ typedef register_container RegAPERxbufoffsetFunc1_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc0. */ typedef register_container RegAPETxToNetDoorbellFunc0_t { @@ -686,10 +740,18 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -715,6 +777,8 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc0_t& operator=(const RegAPETxToNetDoorbellFunc0_t& other) { @@ -724,6 +788,84 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { #endif /* CXX_SIMULATOR */ } RegAPETxToNetDoorbellFunc0_t; +#define REG_APE_TX_STATE0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010020) /* APE TX Status. */ +#define APE_TX_STATE0_TAIL_SHIFT 0u +#define APE_TX_STATE0_TAIL_MASK 0xfffu +#define GET_APE_TX_STATE0_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) +#define SET_APE_TX_STATE0_TAIL(__val__) (((__val__) << 0u) & 0xfffu) +#define APE_TX_STATE0_HEAD_SHIFT 12u +#define APE_TX_STATE0_HEAD_MASK 0xfff000u +#define GET_APE_TX_STATE0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) +#define SET_APE_TX_STATE0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_TX_STATE0_TXERROR_SHIFT 24u +#define APE_TX_STATE0_TXERROR_MASK 0x1000000u +#define GET_APE_TX_STATE0_TXERROR(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_TX_STATE0_TXERROR(__val__) (((__val__) << 24u) & 0x1000000u) +#define APE_TX_STATE0_ERROR_CODE_SHIFT 25u +#define APE_TX_STATE0_ERROR_CODE_MASK 0xe000000u +#define GET_APE_TX_STATE0_ERROR_CODE(__reg__) (((__reg__) & 0xe000000) >> 25u) +#define SET_APE_TX_STATE0_ERROR_CODE(__val__) (((__val__) << 25u) & 0xe000000u) + +/** @brief Register definition for @ref APE_t.TxState0. */ +typedef register_container RegAPETxState0_t { + /** @brief 32bit direct register access. */ + BCM5719_APE_H_uint32_t r32; + + BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXError, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ErrorCode, 25, 3) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_28, 28, 4) +#elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_28, 28, 4) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ErrorCode, 25, 3) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXError, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) +#else +#error Unknown Endian +#endif + BITFIELD_END(BCM5719_APE_H_uint32_t, bits) +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxState0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxState0_t() + { + /** @brief constructor for @ref APE_t.TxState0. */ + r32.setName("TxState0"); + bits.Tail.setBaseRegister(&r32); + bits.Tail.setName("Tail"); + bits.Head.setBaseRegister(&r32); + bits.Head.setName("Head"); + bits.TXError.setBaseRegister(&r32); + bits.TXError.setName("TXError"); + bits.ErrorCode.setBaseRegister(&r32); + bits.ErrorCode.setName("ErrorCode"); + } + RegAPETxState0_t& operator=(const RegAPETxState0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxState0_t; + #define REG_APE_MODE_2 ((volatile BCM5719_APE_H_uint32_t*)0xc001002c) /* Expansion for MODE */ /** @brief Register definition for @ref APE_t.Mode2. */ typedef register_container RegAPEMode2_t { @@ -1040,6 +1182,10 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define APE_RX_POOL_RETIRE_0_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_0_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_0_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_0_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_0_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_0_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_0_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_0_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -1065,8 +1211,8 @@ typedef register_container RegAPERxPoolRetire0_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -1080,8 +1226,8 @@ typedef register_container RegAPERxPoolRetire0_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -1105,6 +1251,8 @@ typedef register_container RegAPERxPoolRetire0_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -1127,6 +1275,10 @@ typedef register_container RegAPERxPoolRetire0_t { #define APE_RX_POOL_RETIRE_1_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_1_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_1_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_1_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_1_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_1_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_1_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_1_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -1152,8 +1304,8 @@ typedef register_container RegAPERxPoolRetire1_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -1167,8 +1319,8 @@ typedef register_container RegAPERxPoolRetire1_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -1192,6 +1344,8 @@ typedef register_container RegAPERxPoolRetire1_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -1396,6 +1550,56 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { #endif /* CXX_SIMULATOR */ } RegAPETxToNetBufferAllocator0_t; +#define REG_APE_TX_TO_NET_BUFFER_RETURN_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010094) /* */ +/** @brief Register definition for @ref APE_t.TxToNetBufferReturn0. */ +typedef register_container RegAPETxToNetBufferReturn0_t { + /** @brief 32bit direct register access. */ + BCM5719_APE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxToNetBufferReturn0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxToNetBufferReturn0_t() + { + /** @brief constructor for @ref APE_t.TxToNetBufferReturn0. */ + r32.setName("TxToNetBufferReturn0"); + } + RegAPETxToNetBufferReturn0_t& operator=(const RegAPETxToNetBufferReturn0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxToNetBufferReturn0_t; + +#define REG_APE_TX_TO_NET_BUFFER_RING_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010098) /* */ +/** @brief Register definition for @ref APE_t.TxToNetBufferRing0. */ +typedef register_container RegAPETxToNetBufferRing0_t { + /** @brief 32bit direct register access. */ + BCM5719_APE_H_uint32_t r32; +#ifdef CXX_SIMULATOR + /** @brief Register name for use with the simulator. */ + const char* getName(void) { return "TxToNetBufferRing0"; } + + /** @brief Print register value. */ + void print(void) { r32.print(); } + + RegAPETxToNetBufferRing0_t() + { + /** @brief constructor for @ref APE_t.TxToNetBufferRing0. */ + r32.setName("TxToNetBufferRing0"); + } + RegAPETxToNetBufferRing0_t& operator=(const RegAPETxToNetBufferRing0_t& other) + { + r32 = other.r32; + return *this; + } +#endif /* CXX_SIMULATOR */ +} RegAPETxToNetBufferRing0_t; + #define REG_APE_TICK_1MHZ ((volatile BCM5719_APE_H_uint32_t*)0xc00100a8) /* Unknown, monotonically increasing value. Increases at a rate of 1MHz. */ /** @brief Register definition for @ref APE_t.Tick1mhz. */ typedef register_container RegAPETick1mhz_t { @@ -2120,9 +2324,13 @@ typedef register_container RegAPETxToNetBufferAllocator1_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc1. */ typedef register_container RegAPETxToNetDoorbellFunc1_t { @@ -2136,10 +2344,18 @@ typedef register_container RegAPETxToNetDoorbellFunc1_t { /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2165,6 +2381,8 @@ typedef register_container RegAPETxToNetDoorbellFunc1_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc1_t& operator=(const RegAPETxToNetDoorbellFunc1_t& other) { @@ -2282,9 +2500,13 @@ typedef register_container RegAPERxbufoffsetFunc2_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc2. */ typedef register_container RegAPETxToNetDoorbellFunc2_t { @@ -2298,10 +2520,18 @@ typedef register_container RegAPETxToNetDoorbellFunc2_t { /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2327,6 +2557,8 @@ typedef register_container RegAPETxToNetDoorbellFunc2_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc2_t& operator=(const RegAPETxToNetDoorbellFunc2_t& other) { @@ -2461,6 +2693,10 @@ typedef register_container RegAPERxPoolModeStatus2_t { #define APE_RX_POOL_RETIRE_2_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_2_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_2_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_2_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_2_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_2_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_2_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_2_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -2486,8 +2722,8 @@ typedef register_container RegAPERxPoolRetire2_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -2501,8 +2737,8 @@ typedef register_container RegAPERxPoolRetire2_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2526,6 +2762,8 @@ typedef register_container RegAPERxPoolRetire2_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -2838,9 +3076,13 @@ typedef register_container RegAPERxbufoffsetFunc3_t { #define GET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) #define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xff000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xff000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xf000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) +#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_SHIFT 28u +#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_MASK 0x10000000u +#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) +#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc3. */ typedef register_container RegAPETxToNetDoorbellFunc3_t { @@ -2854,10 +3096,18 @@ typedef register_container RegAPETxToNetDoorbellFunc3_t { /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) #elif defined(__BIG_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 8) + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -2883,6 +3133,8 @@ typedef register_container RegAPETxToNetDoorbellFunc3_t { bits.Head.setName("Head"); bits.Length.setBaseRegister(&r32); bits.Length.setName("Length"); + bits.TXQueueFull.setBaseRegister(&r32); + bits.TXQueueFull.setName("TXQueueFull"); } RegAPETxToNetDoorbellFunc3_t& operator=(const RegAPETxToNetDoorbellFunc3_t& other) { @@ -3017,6 +3269,10 @@ typedef register_container RegAPERxPoolModeStatus3_t { #define APE_RX_POOL_RETIRE_3_HEAD_MASK 0xfff000u #define GET_APE_RX_POOL_RETIRE_3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) #define SET_APE_RX_POOL_RETIRE_3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) +#define APE_RX_POOL_RETIRE_3_RETIRE_SHIFT 24u +#define APE_RX_POOL_RETIRE_3_RETIRE_MASK 0x1000000u +#define GET_APE_RX_POOL_RETIRE_3_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) +#define SET_APE_RX_POOL_RETIRE_3_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) #define APE_RX_POOL_RETIRE_3_STATE_SHIFT 25u #define APE_RX_POOL_RETIRE_3_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_3_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) @@ -3042,8 +3298,8 @@ typedef register_container RegAPERxPoolRetire3_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) /** @brief */ @@ -3057,8 +3313,8 @@ typedef register_container RegAPERxPoolRetire3_t { BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_24_24, 24, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) /** @brief */ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) /** @brief */ @@ -3082,6 +3338,8 @@ typedef register_container RegAPERxPoolRetire3_t { bits.Tail.setName("Tail"); bits.Head.setBaseRegister(&r32); bits.Head.setName("Head"); + bits.Retire.setBaseRegister(&r32); + bits.Retire.setName("Retire"); bits.State.setBaseRegister(&r32); bits.State.setName("State"); bits.Count.setBaseRegister(&r32); @@ -3312,8 +3570,11 @@ typedef struct APE_t { /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ RegAPETxToNetDoorbellFunc0_t TxToNetDoorbellFunc0; + /** @brief APE TX Status. */ + RegAPETxState0_t TxState0; + /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_32[3]; + BCM5719_APE_H_uint32_t reserved_36[2]; /** @brief Expansion for MODE */ RegAPEMode2_t Mode2; @@ -3351,8 +3612,14 @@ typedef struct APE_t { /** @brief */ RegAPETxToNetBufferAllocator0_t TxToNetBufferAllocator0; + /** @brief */ + RegAPETxToNetBufferReturn0_t TxToNetBufferReturn0; + + /** @brief */ + RegAPETxToNetBufferRing0_t TxToNetBufferRing0; + /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_148[5]; + BCM5719_APE_H_uint32_t reserved_156[3]; /** @brief Unknown, monotonically increasing value. Increases at a rate of 1MHz. */ RegAPETick1mhz_t Tick1mhz; @@ -3475,6 +3742,7 @@ typedef struct APE_t { RxbufoffsetFunc0.r32.setComponentOffset(0x14); RxbufoffsetFunc1.r32.setComponentOffset(0x18); TxToNetDoorbellFunc0.r32.setComponentOffset(0x1c); + TxState0.r32.setComponentOffset(0x20); Mode2.r32.setComponentOffset(0x2c); Status2.r32.setComponentOffset(0x30); LockGrantObsolete.r32.setComponentOffset(0x4c); @@ -3484,6 +3752,8 @@ typedef struct APE_t { RxPoolRetire1.r32.setComponentOffset(0x88); TxToNetPoolModeStatus0.r32.setComponentOffset(0x8c); TxToNetBufferAllocator0.r32.setComponentOffset(0x90); + TxToNetBufferReturn0.r32.setComponentOffset(0x94); + TxToNetBufferRing0.r32.setComponentOffset(0x98); Tick1mhz.r32.setComponentOffset(0xa8); Tick1khz.r32.setComponentOffset(0xac); Tick10hz.r32.setComponentOffset(0xb0); diff --git a/include/bcm5719_APE_PERI.h b/include/bcm5719_APE_PERI.h index 6024989..734339b 100644 --- a/include/bcm5719_APE_PERI.h +++ b/include/bcm5719_APE_PERI.h @@ -980,10 +980,27 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch6Low_t { } RegAPE_PERIBmcToNcSourceMacMatch6Low_t; #define REG_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc0018344) /* Upper four bytes of the MAC */ +#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH_SHIFT 0u +#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH_MASK 0xffffffffu +#define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffffffu) + /** @brief Register definition for @ref APE_PERI_t.BmcToNcSourceMacMatch7High. */ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { /** @brief 32bit direct register access. */ BCM5719_APE_PERI_H_uint32_t r32; + + BITFIELD_BEGIN(BCM5719_APE_PERI_H_uint32_t, bits) +#if defined(__LITTLE_ENDIAN__) + /** @brief Upper four bytes of the MAC */ + BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, High, 0, 32) +#elif defined(__BIG_ENDIAN__) + /** @brief Upper four bytes of the MAC */ + BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, High, 0, 32) +#else +#error Unknown Endian +#endif + BITFIELD_END(BCM5719_APE_PERI_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "BmcToNcSourceMacMatch7High"; } @@ -995,6 +1012,8 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { { /** @brief constructor for @ref APE_PERI_t.BmcToNcSourceMacMatch7High. */ r32.setName("BmcToNcSourceMacMatch7High"); + bits.High.setBaseRegister(&r32); + bits.High.setName("High"); } RegAPE_PERIBmcToNcSourceMacMatch7High_t& operator=(const RegAPE_PERIBmcToNcSourceMacMatch7High_t& other) { @@ -1009,10 +1028,6 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7High_t { #define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW_MASK 0xffff0000u #define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW(__reg__) (((__reg__) & 0xffff0000) >> 16u) #define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_LOW(__val__) (((__val__) << 16u) & 0xffff0000u) -#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH_SHIFT 0u -#define APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH_MASK 0xffffffffu -#define GET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_APE_PERI_BMC_TO_NC_SOURCE_MAC_MATCH_7_LOW_HIGH(__val__) (((__val__) << 0u) & 0xffffffffu) /** @brief Register definition for @ref APE_PERI_t.BmcToNcSourceMacMatch7Low. */ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { @@ -1025,11 +1040,7 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, reserved_15_0, 0, 16) /** @brief Lower two bytes of the MAC */ BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, Low, 16, 16) - /** @brief Upper four bytes of the MAC */ - BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, High, 0, 32) #elif defined(__BIG_ENDIAN__) - /** @brief Upper four bytes of the MAC */ - BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, High, 0, 32) /** @brief Lower two bytes of the MAC */ BITFIELD_MEMBER(BCM5719_APE_PERI_H_uint32_t, Low, 16, 16) /** @brief Padding */ @@ -1051,8 +1062,6 @@ typedef register_container RegAPE_PERIBmcToNcSourceMacMatch7Low_t { r32.setName("BmcToNcSourceMacMatch7Low"); bits.Low.setBaseRegister(&r32); bits.Low.setName("Low"); - bits.High.setBaseRegister(&r32); - bits.High.setName("High"); } RegAPE_PERIBmcToNcSourceMacMatch7Low_t& operator=(const RegAPE_PERIBmcToNcSourceMacMatch7Low_t& other) { diff --git a/include/bcm5719_DEVICE.h b/include/bcm5719_DEVICE.h index 5513ab6..d25c2f2 100644 --- a/include/bcm5719_DEVICE.h +++ b/include/bcm5719_DEVICE.h @@ -6636,10 +6636,14 @@ typedef register_container RegDEVICEGrcModeControl_t { } RegDEVICEGrcModeControl_t; #define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006804) /* */ -#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 0u -#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xffffffffu -#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u +#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u +#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) +#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) +#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u +#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu +#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) +#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) /** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */ typedef register_container RegDEVICEMiscellaneousConfig_t { @@ -6648,11 +6652,19 @@ typedef register_container RegDEVICEMiscellaneousConfig_t { BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1) + /** @brief */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 1, 1) /** @brief */ - BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 1, 31) #elif defined(__BIG_ENDIAN__) /** @brief */ - BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 1, 31) + /** @brief */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 1, 1) + /** @brief Padding */ + BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1) #else #error Unknown Endian #endif @@ -6668,6 +6680,8 @@ typedef register_container RegDEVICEMiscellaneousConfig_t { { /** @brief constructor for @ref DEVICE_t.MiscellaneousConfig. */ r32.setName("MiscellaneousConfig"); + bits.GRCReset.setBaseRegister(&r32); + bits.GRCReset.setName("GRCReset"); bits.all.setBaseRegister(&r32); bits.all.setName("all"); } diff --git a/include/types.h b/include/types.h index e9ec714..0b3baba 100644 --- a/include/types.h +++ b/include/types.h @@ -1,11 +1,12 @@ #ifndef TYPES_H #define TYPES_H +#define SECTION(__section__) __attribute__((section, __section__)) -#define SECTION(__section__) __attribute__((section, __section__)) - -#define ARRAY_ELEMENTS(__array__) (sizeof(__array__)/sizeof(__array__[0])) +#define ARRAY_ELEMENTS(__array__) (sizeof(__array__) / sizeof(__array__[0])) +#define DIVIDE_RND_UP(__value__, __round__) (((__value__) + (__round__)-1) / (__round__)) +#define DIVIDE_RND_DOWN(__value__, __round__) ((__value__) / (__round__)) typedef union { uint64_t u64; @@ -13,12 +14,12 @@ typedef union { struct { uint8_t pad[2]; - uint8_t u8[6]; + uint8_t u8[6]; } oct; struct { - uint32_t u32[2]; + uint32_t u32[2]; } word; } mac_t; diff --git a/ipxact/APE.xml b/ipxact/APE.xml index b368f69..1ce1997 100644 --- a/ipxact/APE.xml +++ b/ipxact/APE.xml @@ -66,11 +66,51 @@ <ipxact:addressBlock> <ipxact:name>RX_PORT</ipxact:name> <ipxact:description>RX from network port, function 0</ipxact:description> + <ipxact:typeIdentifier>RX_PORT</ipxact:typeIdentifier> <ipxact:baseAddress>0xA0000000</ipxact:baseAddress> <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> <ipxact:usage>register</ipxact:usage> <ipxact:volatile>false</ipxact:volatile> + <ipxact:register> + <ipxact:name>in</ipxact:name> + <ipxact:description>This is the memory range into which frames are directed towards the APE by the hardware.</ipxact:description> + <ipxact:addressOffset>0x0</ipxact:addressOffset> + <ipxact:dim>0x1000</ipxact:dim> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>all</ipxact:name> + <ipxact:description>All bits</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>BLOCK_WORDS</ipxact:name> + <ipxact:value>32</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>BLOCK_BYTES</ipxact:name> + <ipxact:value>128</ipxact:value> + </ipxact:enumeratedValue> + + <ipxact:enumeratedValue> + <ipxact:name>Control Word</ipxact:name> + <ipxact:value>0</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>First Payload Word</ipxact:name> + <ipxact:value>12</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Additional Payload Word</ipxact:name> + <ipxact:value>2</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + </ipxact:register> </ipxact:addressBlock> </ipxact:memoryMap> @@ -87,15 +127,6 @@ <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> <ipxact:usage>register</ipxact:usage> <ipxact:volatile>false</ipxact:volatile> - <ipxact:register> - <ipxact:name>queue</ipxact:name> - <ipxact:description>This is the memory range into which frames received and directed towards the APE are placed by the hardware. The hardware will tell you where in this region the frame has been placed.</ipxact:description> - <ipxact:addressOffset>0x0</ipxact:addressOffset> - <ipxact:dim>0x1000</ipxact:dim> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> </ipxact:addressBlock> </ipxact:memoryMap> @@ -146,7 +177,7 @@ <ipxact:volatile>false</ipxact:volatile> <ipxact:register> <ipxact:name>out</ipxact:name> - <ipxact:description>This is the memory range into which frames are directed towards the network byte the APE firmware.</ipxact:description> + <ipxact:description>This is the memory range into which frames are directed towards the network by the APE firmware.</ipxact:description> <ipxact:addressOffset>0x0</ipxact:addressOffset> <ipxact:dim>0x800</ipxact:dim> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -167,6 +198,27 @@ <ipxact:name>BLOCK_BYTES</ipxact:name> <ipxact:value>128</ipxact:value> </ipxact:enumeratedValue> + + <ipxact:enumeratedValue> + <ipxact:name>Control Word</ipxact:name> + <ipxact:value>0</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Frame Len Word</ipxact:name> + <ipxact:value>3</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Num Blocks Word</ipxact:name> + <ipxact:value>9</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>First Payload Word</ipxact:name> + <ipxact:value>12</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Additional Payload Word</ipxact:name> + <ipxact:value>2</ipxact:value> + </ipxact:enumeratedValue> </ipxact:enumeratedValues> </ipxact:field> </ipxact:register> diff --git a/ipxact/APE_component.xml b/ipxact/APE_component.xml index bf5ff9e..dbe49e8 100644 --- a/ipxact/APE_component.xml +++ b/ipxact/APE_component.xml @@ -89,6 +89,20 @@ <ipxact:access>read-write</ipxact:access> </ipxact:field> <ipxact:field> + <ipxact:name>Channel 0 Enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>14</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Channel 2 Enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>15</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>Memory ECC</ipxact:name> <ipxact:description></ipxact:description> <ipxact:bitOffset>18</ipxact:bitOffset> @@ -101,7 +115,22 @@ <ipxact:bitOffset>19</ipxact:bitOffset> <ipxact:bitWidth>1</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> + </ipxact:field> + <ipxact:field> + <ipxact:name>Channel 1 Enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>30</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Channel 3 Enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> <ipxact:register> <ipxact:name>STATUS</ipxact:name> <ipxact:description></ipxact:description> @@ -342,6 +371,12 @@ <ipxact:bitWidth>1</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> + <ipxact:field> + <ipxact:name>Finished</ipxact:name> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>RXBufOffset Func1</ipxact:name> @@ -409,7 +444,45 @@ <ipxact:field> <ipxact:name>Length</ipxact:name> <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TX Queue Full</ipxact:name> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>TX State0</ipxact:name> + <ipxact:description>APE TX Status.</ipxact:description> + <ipxact:addressOffset>0x20</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Tail</ipxact:name> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>12</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Head</ipxact:name> + <ipxact:bitOffset>12</ipxact:bitOffset> + <ipxact:bitWidth>12</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TXError</ipxact:name> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Error Code</ipxact:name> + <ipxact:bitOffset>25</ipxact:bitOffset> + <ipxact:bitWidth>3</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> </ipxact:register> @@ -573,6 +646,13 @@ <ipxact:access>read-write</ipxact:access> </ipxact:field> <ipxact:field> + <ipxact:name>Retire</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>State</ipxact:name> <ipxact:description></ipxact:description> <ipxact:bitOffset>25</ipxact:bitOffset> @@ -628,6 +708,13 @@ <ipxact:access>read-write</ipxact:access> </ipxact:field> <ipxact:field> + <ipxact:name>Retire</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>State</ipxact:name> <ipxact:description></ipxact:description> <ipxact:bitOffset>25</ipxact:bitOffset> @@ -774,6 +861,22 @@ </ipxact:field> </ipxact:register> <ipxact:register> + <ipxact:name>TX To Net Buffer Return 0</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x94</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>TX To Net Buffer Ring 0</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x98</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> <ipxact:name>Tick 1MHz</ipxact:name> <ipxact:description>Unknown, monotonically increasing value. Increases at a rate of 1MHz.</ipxact:description> <ipxact:addressOffset>0xa8</ipxact:addressOffset> @@ -1159,7 +1262,13 @@ <ipxact:field> <ipxact:name>Length</ipxact:name> <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TX Queue Full</ipxact:name> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> </ipxact:register> @@ -1229,7 +1338,13 @@ <ipxact:field> <ipxact:name>Length</ipxact:name> <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TX Queue Full</ipxact:name> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> </ipxact:register> @@ -1312,6 +1427,13 @@ <ipxact:access>read-write</ipxact:access> </ipxact:field> <ipxact:field> + <ipxact:name>Retire</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>State</ipxact:name> <ipxact:description></ipxact:description> <ipxact:bitOffset>25</ipxact:bitOffset> @@ -1523,7 +1645,13 @@ <ipxact:field> <ipxact:name>Length</ipxact:name> <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TX Queue Full</ipxact:name> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> </ipxact:register> @@ -1606,6 +1734,13 @@ <ipxact:access>read-write</ipxact:access> </ipxact:field> <ipxact:field> + <ipxact:name>Retire</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>State</ipxact:name> <ipxact:description></ipxact:description> <ipxact:bitOffset>25</ipxact:bitOffset> @@ -2101,6 +2236,13 @@ <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> <ipxact:size>32</ipxact:size> <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>High</ipxact:name> + <ipxact:description>Upper four bytes of the MAC</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>BMC to NC Source MAC Match 7 Low</ipxact:name> @@ -2116,13 +2258,6 @@ <ipxact:bitWidth>16</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> - <ipxact:field> - <ipxact:name>High</ipxact:name> - <ipxact:description>Upper four bytes of the MAC</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>BMC to NC RX VLAN</ipxact:name> diff --git a/ipxact/DEVICE.xml b/ipxact/DEVICE.xml index d8b710c..4506d88 100644 --- a/ipxact/DEVICE.xml +++ b/ipxact/DEVICE.xml @@ -3728,10 +3728,17 @@ <ipxact:size>32</ipxact:size> <ipxact:volatile>true</ipxact:volatile> <ipxact:field> + <ipxact:name>GRC Reset</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> <ipxact:name>all</ipxact:name> <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>31</ipxact:bitWidth> <ipxact:access>read-write</ipxact:access> </ipxact:field> </ipxact:register> diff --git a/ipxact/regen.sh b/ipxact/regen.sh index 976be00..28c0c20 100755 --- a/ipxact/regen.sh +++ b/ipxact/regen.sh @@ -24,6 +24,10 @@ mv bcm5719_BOOTCODE.h ../include ${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.cpp +rm bcm5719_BOOTCODE*.cpp +rm bcm5719_RXMBUF*.cpp +rm bcm5719_TXMBUF*.cpp +rm bcm5719_SDBCACHE*.cpp mv *.cpp ../simulator/ # ${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.s @@ -46,6 +50,7 @@ mv APE_SHM*.h ../include mv APE_FILTERS*.h ../include mv APE_DEVICE*.h ../include mv APE_TX_PORT*.h ../include +mv APE_RX_PORT*.h ../include # ${IPXACT} -p ${PROJECT} NVIC.xml APE_full.xml APE.s ${IPXACT} -p ${PROJECT} APE_full.xml -t asym APE_sym.s @@ -55,6 +60,4 @@ ${IPXACT} -p ${PROJECT} APE_full.xml -t ape_cpp APE.cpp rm APE_APE*.cpp rm APE_SHM*.cpp rm APE_NVM*.cpp -rm APE_DEVICE*.cpp -rm APE_TX_PORT*.cpp mv *.cpp ../simulator/ diff --git a/libs/APE/ape.c b/libs/APE/ape.c index 2f3d6ee..0dd2acb 100644 --- a/libs/APE/ape.c +++ b/libs/APE/ape.c @@ -51,7 +51,7 @@ void APE_aquireLock(void) lock_req.bits.Bootcode = 1; uint8_t function = DEVICE.Status.bits.FunctionNumber; - switch(function) + switch (function) { default: case 0: @@ -59,7 +59,7 @@ void APE_aquireLock(void) do { // spin - } while(lock_req.r32 != APE_PERI.PerLockGrantPhy0.r32); + } while (lock_req.r32 != APE_PERI.PerLockGrantPhy0.r32); return; case 1: @@ -67,7 +67,7 @@ void APE_aquireLock(void) do { // spin - } while(lock_req.r32 != APE_PERI.PerLockGrantPhy1.r32); + } while (lock_req.r32 != APE_PERI.PerLockGrantPhy1.r32); return; case 2: @@ -75,7 +75,7 @@ void APE_aquireLock(void) do { // spin - } while(lock_req.r32 != APE_PERI.PerLockGrantPhy2.r32); + } while (lock_req.r32 != APE_PERI.PerLockGrantPhy2.r32); return; case 3: @@ -83,10 +83,9 @@ void APE_aquireLock(void) do { // spin - } while(lock_req.r32 != APE_PERI.PerLockGrantPhy3.r32); + } while (lock_req.r32 != APE_PERI.PerLockGrantPhy3.r32); return; } - } void APE_releaseLock(void) @@ -96,7 +95,7 @@ void APE_releaseLock(void) lock_release.bits.Bootcode = 1; uint8_t function = DEVICE.Status.bits.FunctionNumber; - switch(function) + switch (function) { default: case 0: @@ -119,12 +118,12 @@ void APE_releaseAllLocks(void) lock_release.r32 = 0; lock_release.bits.Bootcode = 1; - APE_PERI.PerLockGrantPhy0.r32 = lock_release.r32; - APE_PERI.PerLockGrantGrc.r32 = lock_release.r32; - APE_PERI.PerLockGrantPhy1.r32 = lock_release.r32; - APE_PERI.PerLockGrantPhy2.r32 = lock_release.r32; - APE_PERI.PerLockGrantMem.r32 = lock_release.r32; - APE_PERI.PerLockGrantPhy3.r32 = lock_release.r32; - APE_PERI.PerLockGrantPort6.r32 = lock_release.r32; - APE_PERI.PerLockGrantGpio.r32 = lock_release.r32; + APE_PERI.PerLockGrantPhy0.r32 = lock_release.r32; + APE_PERI.PerLockGrantGrc.r32 = lock_release.r32; + APE_PERI.PerLockGrantPhy1.r32 = lock_release.r32; + APE_PERI.PerLockGrantPhy2.r32 = lock_release.r32; + APE_PERI.PerLockGrantMem.r32 = lock_release.r32; + APE_PERI.PerLockGrantPhy3.r32 = lock_release.r32; + APE_PERI.PerLockGrantPort6.r32 = lock_release.r32; + APE_PERI.PerLockGrantGpio.r32 = lock_release.r32; } diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index b3fe23b..f3ef1e1 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -49,6 +49,7 @@ add_subdirectory(MII) add_subdirectory(VPD) add_subdirectory(NCSI) +add_subdirectory(Network) add_subdirectory(OptParse) diff --git a/libs/Compress/compress.c b/libs/Compress/compress.c index 4501340..c8385ba 100644 --- a/libs/Compress/compress.c +++ b/libs/Compress/compress.c @@ -43,24 +43,24 @@ //////////////////////////////////////////////////////////////////////////////// #include <Compress.h> - #include <assert.h> -// Original implementation from https://github.com/hlandau/ortega/blob/master/apestamp.c - +// Original implementation from +// https://github.com/hlandau/ortega/blob/master/apestamp.c #define N 2048 #define F 34 #define THRESHOLD 2 #define NIL N -typedef struct { - uint8_t dict[N+F-1]; +typedef struct +{ + uint8_t dict[N + F - 1]; // Describes longest match. Set by _InsertNode. int matchPos, matchLen; // Left and right children and parents. Makes up a binary search tree. - int lson[N+1], rson[N+257], parent[N+1]; + int lson[N + 1], rson[N + 257], parent[N + 1]; } compressor_state; // Inserts a string of length F, text_buf[r..r+F-1] into one of the trees @@ -79,7 +79,7 @@ static void _InsertNode(compressor_state *st, int r) cmp = 1; key = &dict[r]; - p = N+1+key[0]; + p = N + 1 + key[0]; rson[r] = lson[r] = NIL; st->matchLen = 0; for (;;) @@ -113,9 +113,9 @@ static void _InsertNode(compressor_state *st, int r) // Compare. int i; - for (i=1; i<F; ++i) + for (i = 1; i < F; ++i) { - cmp = key[i] - dict[p+i]; + cmp = key[i] - dict[p + i]; if (cmp) { break; @@ -135,7 +135,7 @@ static void _InsertNode(compressor_state *st, int r) } } - parent[r] = parent[p]; + parent[r] = parent[p]; lson[r] = lson[p]; rson[r] = rson[p]; parent[lson[p]] = r; @@ -152,7 +152,8 @@ static void _InsertNode(compressor_state *st, int r) } // Deletes node p from the tree. -static void _DeleteNode(compressor_state *st, int p) { +static void _DeleteNode(compressor_state *st, int p) +{ int q; int *lson = st->lson, *rson = st->rson, *parent = st->parent; @@ -171,10 +172,11 @@ static void _DeleteNode(compressor_state *st, int p) { { q = rson[p]; } - else { + else { - q = lson[p]; - } + { + q = lson[p]; + } if (rson[q] != NIL) { do @@ -207,11 +209,11 @@ static void _DeleteNode(compressor_state *st, int p) { // int32_t decompress(uint8_t* outBuffer, int32_t outBytes, // uint8_t* inBuffer, int32_t inBytes) - // Compression routine adapted from original 1989 LZSS.C by Haruhiko Okumura. // "Use, distribute, and modify this program freely." -int32_t compress(uint8_t *outBuffer, int32_t outBytes, - const uint8_t *inBuffer, int32_t inBytes) { +int32_t compress(uint8_t *outBuffer, int32_t outBytes, const uint8_t *inBuffer, + int32_t inBytes) +{ const uint8_t *inEnd = inBuffer + inBytes; size_t bytesWritten_ = 0; @@ -223,40 +225,41 @@ int32_t compress(uint8_t *outBuffer, int32_t outBytes, } // Initialize tree. - for (int i=N+1; i <= N+256; ++i) + for (int i = N + 1; i <= N + 256; ++i) { st.rson[i] = NIL; } - for (int i=0; i<N; ++i) + for (int i = 0; i < N; ++i) { st.parent[i] = NIL; } - int i, c, len, r = N-F, s = 0, lastMatchLen, codeBufPtr = 1; + int i, c, len, r = N - F, s = 0, lastMatchLen, codeBufPtr = 1; uint8_t codeBuf[17], mask = 1; codeBuf[0] = 0; // Clear the buffer. - for (i=0; i<r; ++i) + for (i = 0; i < r; ++i) { st.dict[i] = 0x20; } // Read F bytes into the last F bytes of the buffer. - for (len=0; len < F && inBuffer < inEnd; ++len) + for (len = 0; len < F && inBuffer < inEnd; ++len) { - st.dict[r+len] = c = *inBuffer++; + st.dict[r + len] = c = *inBuffer++; } // Insert the F strings, each of which begins with one or more 'space' // characters. Note the order in which these strings are inserted. This way, // degenerate trees will be less likely to occur. - for (i=1; i<=F; ++i) + for (i = 1; i <= F; ++i) { - _InsertNode(&st, r-i); + _InsertNode(&st, r - i); } - // Finally, insert the whole string just read. matchLength and matchPosition are set. + // Finally, insert the whole string just read. matchLength and matchPosition + // are set. _InsertNode(&st, r); do @@ -271,28 +274,29 @@ int32_t compress(uint8_t *outBuffer, int32_t outBytes, { // Not long enough match. Send one byte. st.matchLen = 1; - codeBuf[0] |= mask; // "Send one byte" flag. + codeBuf[0] |= mask; // "Send one byte" flag. codeBuf[codeBufPtr++] = st.dict[r]; // Send uncoded. - //printf(" LIT 0x%02x\n", st.dict[r]); + // printf(" LIT 0x%02x\n", st.dict[r]); } else { // Send position and length pair. Note that matchLen > THRESHOLD. - //printf(" REF off=%4u len=%4u\n", st.matchPos, st.matchLen); - //printf(" "); - //for (size_t j=0; j<st.matchLen; ++j) + // printf(" REF off=%4u len=%4u\n", st.matchPos, st.matchLen); + // printf(" "); + // for (size_t j=0; j<st.matchLen; ++j) // printf("%02x ", st.dict[st.matchPos+j]); - //printf("\n"); + // printf("\n"); codeBuf[codeBufPtr++] = (uint8_t)st.matchPos; - assert(st.matchLen - (THRESHOLD+1) < 0x20); - codeBuf[codeBufPtr++] = (uint8_t)(((st.matchPos >> 3) & 0xE0) | (st.matchLen - (THRESHOLD+1))); + assert(st.matchLen - (THRESHOLD + 1) < 0x20); + codeBuf[codeBufPtr++] = (uint8_t)(((st.matchPos >> 3) & 0xE0) | + (st.matchLen - (THRESHOLD + 1))); } mask <<= 1; if (!mask) { // Send at most eight units of code together. - for (i=0; i<codeBufPtr; ++i) + for (i = 0; i < codeBufPtr; ++i) { *outBuffer++ = codeBuf[i]; outBytes--; @@ -303,31 +307,32 @@ int32_t compress(uint8_t *outBuffer, int32_t outBytes, } lastMatchLen = st.matchLen; - for (i=0; i<lastMatchLen && inBuffer < inEnd; ++i) + for (i = 0; i < lastMatchLen && inBuffer < inEnd; ++i) { // Delete old strings and read new bytes. c = *inBuffer++; _DeleteNode(&st, s); st.dict[s] = c; - // If the position is near the end of the buffer, extend the buffer to - // make string comparison easier. - if (s < F-1) + // If the position is near the end of the buffer, extend the buffer + // to make string comparison easier. + if (s < F - 1) { - st.dict[s+N] = c; + st.dict[s + N] = c; } // Since this is a ring buffer, increment the position modulo N. - s = (s+1) % N; - r = (r+1) % N; + s = (s + 1) % N; + r = (r + 1) % N; // Register the string in dict[r..r+F-1]. _InsertNode(&st, r); } while (i++ < lastMatchLen) { - // After the end of text, no need to read, but buffer may not be empty. + // After the end of text, no need to read, but buffer may not be + // empty. _DeleteNode(&st, s); - s = (s+1) % N; - r = (r+1) % N; + s = (s + 1) % N; + r = (r + 1) % N; if (--len) { _InsertNode(&st, r); @@ -338,7 +343,7 @@ int32_t compress(uint8_t *outBuffer, int32_t outBytes, // Send remaining code. if (codeBufPtr > 1) { - for (i=0; i<codeBufPtr; ++i) + for (i = 0; i < codeBufPtr; ++i) { *outBuffer++ = codeBuf[i]; outBytes--; diff --git a/libs/Compress/decompress.c b/libs/Compress/decompress.c index 286e3a0..886ed7e 100644 --- a/libs/Compress/decompress.c +++ b/libs/Compress/decompress.c @@ -43,39 +43,38 @@ //////////////////////////////////////////////////////////////////////////////// #include <Compress.h> - #include <stdio.h> -#define DICTIONARY_INIT_0x20 (0x20) -#define DICTIONARY_INIT_0x00 (0x00) -#define DICTIONARY_INIT_INDEX (2014) -#define DICTIONARY_SIZE (2048) +#define DICTIONARY_INIT_0x20 (0x20) +#define DICTIONARY_INIT_0x00 (0x00) +#define DICTIONARY_INIT_INDEX (2014) +#define DICTIONARY_SIZE (2048) #define LITERAL_TYPE (1) #define REFERENCE_TYPE (0) -static struct { +static struct +{ uint8_t dictionary[DICTIONARY_SIZE]; uint32_t cursor; - const uint8_t* inBuffer; + const uint8_t *inBuffer; int32_t inBytes; - uint8_t* outBuffer; + uint8_t *outBuffer; int32_t outRemaining; int32_t outSent; } g_DecompressorState; - -static void state_init(const uint8_t* inBuffer, int32_t inBytes) +static void state_init(const uint8_t *inBuffer, int32_t inBytes) { g_DecompressorState.cursor = DICTIONARY_INIT_INDEX; int i = 0; - for(; i < g_DecompressorState.cursor; i++) + for (; i < g_DecompressorState.cursor; i++) { g_DecompressorState.dictionary[i] = DICTIONARY_INIT_0x20; } - for(; i < DICTIONARY_SIZE; i++) + for (; i < DICTIONARY_SIZE; i++) { g_DecompressorState.dictionary[i] = DICTIONARY_INIT_0x00; } @@ -88,7 +87,8 @@ static void state_insert(uint8_t byte) { g_DecompressorState.dictionary[g_DecompressorState.cursor] = byte; // Increment and wrap. - g_DecompressorState.cursor = (g_DecompressorState.cursor + 1) % DICTIONARY_SIZE; + g_DecompressorState.cursor = + (g_DecompressorState.cursor + 1) % DICTIONARY_SIZE; } static uint8_t state_get_dictionary(uint16_t offset) @@ -103,9 +103,9 @@ static uint8_t state_get_byte(void) uint8_t byte = 0; // if(bytesLeft > 0) // { - byte = *g_DecompressorState.inBuffer; - g_DecompressorState.inBuffer++; - g_DecompressorState.inBytes--; + byte = *g_DecompressorState.inBuffer; + g_DecompressorState.inBuffer++; + g_DecompressorState.inBytes--; // } return byte; @@ -116,24 +116,24 @@ int32_t state_bytes_left(void) return g_DecompressorState.inBytes; } -int32_t decompress(uint8_t* outBuffer, int32_t outBytes, - const uint8_t* inBuffer, int32_t inBytes) +int32_t decompress(uint8_t *outBuffer, int32_t outBytes, + const uint8_t *inBuffer, int32_t inBytes) { int32_t actualSize = 0; state_init(inBuffer, inBytes); - while(state_bytes_left() > 0) + while (state_bytes_left() > 0) { uint8_t control = state_get_byte(); - for(int i = 0; i < 8; i++) + for (int i = 0; i < 8; i++) { - if(actualSize >= outBytes || !state_bytes_left()) + if (actualSize >= outBytes || !state_bytes_left()) { // We have no bytes left, or we've filled up the output buffer break; } - if((control & (1 << i)) == REFERENCE_TYPE) + if ((control & (1 << i)) == REFERENCE_TYPE) { // Read in two reference bytes uint8_t B0 = state_get_byte(); @@ -142,7 +142,7 @@ int32_t decompress(uint8_t* outBuffer, int32_t outBytes, uint16_t offset = (((uint16_t)B1 & 0xE0u) << 3u) | B0; uint16_t length = (B1 & 0x1Fu) + 3u; - while(length && actualSize < outBytes) + while (length && actualSize < outBytes) { uint8_t literal = state_get_dictionary(offset); state_insert(literal); @@ -154,18 +154,15 @@ int32_t decompress(uint8_t* outBuffer, int32_t outBytes, } else /* LITERAL_TYPE */ { - uint8_t literal = state_get_byte();; + uint8_t literal = state_get_byte(); + ; state_insert(literal); // Output outBuffer[actualSize++] = literal; - } } } - // printf("inBytes: %d (%d left), outBytes: %d, actualSize: %d\n", inBytes, state_bytes_left(), outBytes, actualSize); - // while(1); - return actualSize; } diff --git a/libs/MII/include/MII.h b/libs/MII/include/MII.h index bfca1e2..85e9f9d 100644 --- a/libs/MII/include/MII.h +++ b/libs/MII/include/MII.h @@ -44,8 +44,8 @@ #ifndef MII_H #define MII_H -#include <stdint.h> #include <bcm5719_MII.h> +#include <stdint.h> #ifdef CXX_SIMULATOR typedef uint64_t mii_reg_t; diff --git a/libs/MII/mii.c b/libs/MII/mii.c index 51042d2..ad8e2ef 100644 --- a/libs/MII/mii.c +++ b/libs/MII/mii.c @@ -55,15 +55,17 @@ static void __attribute__((noinline)) MII_wait(void) uint8_t MII_getPhy(void) { - if(DEVICE.SgmiiStatus.bits.MediaSelectionMode) + if (DEVICE.SgmiiStatus.bits.MediaSelectionMode) { // SERDES platform - return DEVICE.Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0; + return DEVICE.Status.bits.FunctionNumber + + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0; } else { // GPHY platform - return DEVICE.Status.bits.FunctionNumber + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0; + return DEVICE.Status.bits.FunctionNumber + + DEVICE_MII_COMMUNICATION_PHY_ADDRESS_PHY_0; } } @@ -114,16 +116,16 @@ static void MII_writeRegisterInternal(uint8_t phy, mii_reg_t reg, uint16_t data) MII_wait(); } - static uint16_t MII_readShadowRegister18(uint8_t phy, mii_reg_t reg) { - // Write register 18h, bits [2:0] = 111 This selects the Miscellaneous Control register, shadow 7h. - // All reads must be performed through the Miscellaneous Control register. - // Bit 15 = 0 This allows only bits [14:12] and bits [2:0] to be written. - // Bits [14:12] = zzz This selects shadow register zzz to be read. - // Bits [11: 3] = <don't care> When bit 15 = 0, these bits are ignored. - // Bits [2:0] = 111 This sets the Shadow Register Select to 111 (Miscellaneous Control register). - // Read register 18h Data read back is the value from shadow register zzz. + // Write register 18h, bits [2:0] = 111 This selects the Miscellaneous + // Control register, shadow 7h. All reads must be performed through the + // Miscellaneous Control register. Bit 15 = 0 This allows only bits [14:12] + // and bits [2:0] to be written. Bits [14:12] = zzz This selects shadow + // register zzz to be read. Bits [11: 3] = <don't care> When bit 15 = 0, + // these bits are ignored. Bits [2:0] = 111 This sets the Shadow Register + // Select to 111 (Miscellaneous Control register). Read register 18h Data + // read back is the value from shadow register zzz. // -------------------------------------------- // PHY 0x18 Shadow 0x1 register read Procedure @@ -163,11 +165,11 @@ static uint16_t MII_readShadowRegister1C(uint8_t phy, mii_reg_t reg) uint16_t MII_readRegister(uint8_t phy, mii_reg_t reg) { - if((reg & 0xFF) == 0x1C) + if ((reg & 0xFF) == 0x1C) { return MII_readShadowRegister1C(phy, reg); } - else if((reg & 0xFF) == 0x18) + else if ((reg & 0xFF) == 0x18) { return MII_readShadowRegister18(phy, reg); } @@ -179,9 +181,9 @@ uint16_t MII_readRegister(uint8_t phy, mii_reg_t reg) static void MII_writeShadowRegister18(uint8_t phy, mii_reg_t reg, uint16_t data) { - // Set Bits [15:3] = Preferred write values Bits [15:3] contain the desired bits to be written to. - // Set Bits [2:0] = yyy This enables shadow register yyy to be written. - // For shadow 7h, bit 15 must also be written. + // Set Bits [15:3] = Preferred write values Bits [15:3] contain the desired + // bits to be written to. Set Bits [2:0] = yyy This enables shadow register + // yyy to be written. For shadow 7h, bit 15 must also be written. // -------------------------------------------- // PHY 0x18 Shadow 0x2 register write Procedure @@ -195,13 +197,14 @@ static void MII_writeShadowRegister18(uint8_t phy, mii_reg_t reg, uint16_t data) shadow_select.r16 = 0; shadow_select.bits.ShadowRegisterReadSelector = shadow_reg; shadow_select.bits.ShadowRegisterSelector = 7; - MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, shadow_select.r16); + MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, + shadow_select.r16); RegMIIMiscellaneousControl_t write_data; write_data.r16 = data; write_data.bits.ShadowRegisterSelector = shadow_reg; - MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, write_data.r16); - + MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, + write_data.r16); } static void MII_writeShadowRegister1C(uint8_t phy, mii_reg_t reg, uint16_t data) @@ -217,23 +220,25 @@ static void MII_writeShadowRegister1C(uint8_t phy, mii_reg_t reg, uint16_t data) RegMIICabletronLed_t shadow_select; shadow_select.r16 = 0; shadow_select.bits.ShadowRegisterSelector = shadow_reg; - MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, shadow_select.r16); + MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, + shadow_select.r16); RegMIICabletronLed_t write_data; write_data.r16 = data; write_data.bits.ShadowRegisterSelector = shadow_reg; write_data.bits.WriteEnable = 1; - MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, write_data.r16); + MII_writeRegisterInternal(phy, (mii_reg_t)REG_MII_CABLETRON_LED, + write_data.r16); } void MII_writeRegister(uint8_t phy, mii_reg_t reg, uint16_t data) { - if((reg & 0xFF) == 0x1C) + if ((reg & 0xFF) == 0x1C) { MII_writeShadowRegister1C(phy, reg, data); } - else if((reg & 0xFF) == 0x18) + else if ((reg & 0xFF) == 0x18) { MII_writeShadowRegister18(phy, reg, data); } @@ -263,5 +268,6 @@ void MII_reset(uint8_t phy) do { // Spin - } while((MII_readRegister(phy, (mii_reg_t)REG_MII_CONTROL) & MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK); + } while ((MII_readRegister(phy, (mii_reg_t)REG_MII_CONTROL) & + MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK); } diff --git a/libs/NCSI/CMakeLists.txt b/libs/NCSI/CMakeLists.txt index 67e9a1e..90fa313 100644 --- a/libs/NCSI/CMakeLists.txt +++ b/libs/NCSI/CMakeLists.txt @@ -47,12 +47,13 @@ project(NCSI) # Host Simulation library simulator_add_library(${PROJECT_NAME} STATIC ncsi.c) -target_link_libraries(${PROJECT_NAME} PRIVATE simulator) +target_link_libraries(${PROJECT_NAME} PRIVATE simulator Network) target_include_directories(${PROJECT_NAME} PUBLIC ../../include) target_include_directories(${PROJECT_NAME} PUBLIC include) # ARM Library arm_add_library(${PROJECT_NAME}-arm STATIC ncsi.c) +target_link_libraries(${PROJECT_NAME}-arm PRIVATE Network-arm) target_include_directories(${PROJECT_NAME}-arm PUBLIC ../../include) target_include_directories(${PROJECT_NAME}-arm PUBLIC include) diff --git a/libs/NCSI/include/Ethernet.h b/libs/NCSI/include/Ethernet.h index 358dcbf..632499b 100644 --- a/libs/NCSI/include/Ethernet.h +++ b/libs/NCSI/include/Ethernet.h @@ -190,6 +190,25 @@ typedef struct { uint32_t OEMLinkSettings_Low:16; } SetLink_t; +typedef struct { + // Bytes 0 - 27 + ControlPacketHeader_t header; + + // Byte 28 - 31 + uint32_t MAC54:16; + uint32_t headerPadding:16; + + // Bytes 32 - 35 + uint32_t MAC10:16; + uint32_t MAC32:16; + + // Bytes 36 - 39 + uint32_t pad:16; + uint32_t Enable:1; + uint32_t Rsvd:4; + uint32_t AT:3; + uint32_t MACNumber:8; +} SetMACAddr_t; typedef struct @@ -297,6 +316,8 @@ typedef union { SetLink_t setLink; + SetMACAddr_t setMACAddr; + /* Response Packets */ ResponsePacketHeader_t responsePacket; diff --git a/libs/NCSI/include/NCSI.h b/libs/NCSI/include/NCSI.h index 440685f..a26ac51 100644 --- a/libs/NCSI/include/NCSI.h +++ b/libs/NCSI/include/NCSI.h @@ -64,4 +64,8 @@ void handleNCSIFrame(NetworkFrame_t* frame); #define NCSI_REASON_CODE_INVALID_PAYLOAD_LENGTH (5) /* The payload length in the command is incorrect for the given command */ #define NCSI_REASON_CODE_UNKNOWN_UNSUPPORTED (0x7FFF) /* Returned when the command type is unknown or unsupported */ +void NCSI_TxPacket(uint32_t* packet, uint32_t packet_len); + +void NCSI_init(void); + #endif /* NCSI_H */
\ No newline at end of file diff --git a/libs/NCSI/ncsi.c b/libs/NCSI/ncsi.c index b27a7e2..e2c3b68 100644 --- a/libs/NCSI/ncsi.c +++ b/libs/NCSI/ncsi.c @@ -51,6 +51,9 @@ #include <APE_SHM_CHANNEL3.h> #include <stdbool.h> +#include <Network.h> +#include <types.h> + #define MAX_CHANNELS 4 #define PACKAGE_ID_SHIFT 5 @@ -78,7 +81,7 @@ NetworkFrame_t gResponseFrame = { .responsePacket = { .DestinationAddress = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, - .SourceAddress = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, + .SourceAddress = {0xFF, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF}, .HeaderRevision = 1, .ManagmentControllerID = 0, @@ -115,10 +118,10 @@ NetworkFrame_t gLinkStatusResponseFrame = .PayloadLength = 16, .reserved_1 = 0, - .ResponseCode = 0, + .ResponseCode = NCSI_RESPONSE_CODE_COMMAND_COMPLETE, .reserved_4 = 0, .LinkStatus_High = 0, - .ReasonCode = 0, + .ReasonCode = NCSI_REASON_CODE_NONE, .OtherIndications_High = 0, .LinkStatus_Low = 0, .OEMLinkStatus_High = 0, @@ -424,9 +427,19 @@ static void setMACAddressHandler(NetworkFrame_t* frame) #if CXX_SIMULATOR int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; printf("Set MAC: channel %x\n", ch); + printf("MAC54: 0x%04X\n", frame->setMACAddr.MAC54); + printf("MAC32: 0x%04X\n", frame->setMACAddr.MAC32); + printf("MAC10: 0x%04X\n", frame->setMACAddr.MAC10); + printf("Enable: 0x%04X\n", frame->setMACAddr.Enable); + printf("AT: 0x%04X\n", frame->setMACAddr.AT); + printf("MACNumber: 0x%04X\n", frame->setMACAddr.MACNumber); #endif // gPackageState.channel[ch].shm->NcsiChannelInfo.bits.Enabled = false; + uint32_t low = (frame->setMACAddr.MAC32 << 16) | frame->setMACAddr.MAC10; + Network_SetMACAddr(frame->setMACAddr.MAC54, low, frame->setMACAddr.MACNumber, frame->setMACAddr.Enable); + + sendNCSIResponse( frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, @@ -593,27 +606,13 @@ void resetChannel(int ch) channel->shm->NcsiChannelCtrlstatRx.r32 = 0; } -void sendNCSILinkStatusResponse(uint8_t InstanceID, uint8_t channelID, uint32_t LinkStatus, uint32_t OEMLinkStatus, uint32_t OtherIndications) +void NCSI_TxPacket(uint32_t* packet, uint32_t packet_len) { - uint32_t packetSize = ETHERNET_FRAME_MIN - 4; - uint32_t packetWords = ((packetSize + 3) / 4); - uint32_t lastBytes = packetSize % 4; + uint32_t packetWords = DIVIDE_RND_UP(packet_len, sizeof(uint32_t)); RegAPE_PERIBmcToNcTxControl_t txControl; txControl.r32 = 0; - txControl.bits.LastByteCount = lastBytes; - - gLinkStatusResponseFrame.linkStatusResponse.ChannelID = channelID; - gLinkStatusResponseFrame.linkStatusResponse.InstanceID = InstanceID; - gLinkStatusResponseFrame.linkStatusResponse.ResponseCode = NCSI_RESPONSE_CODE_COMMAND_COMPLETE; - gLinkStatusResponseFrame.linkStatusResponse.ReasonCode = NCSI_REASON_CODE_NONE; - - gLinkStatusResponseFrame.linkStatusResponse.LinkStatus_High = LinkStatus >> 16; - gLinkStatusResponseFrame.linkStatusResponse.LinkStatus_Low = LinkStatus & 0xffff; - gLinkStatusResponseFrame.linkStatusResponse.OEMLinkStatus_High = OEMLinkStatus >> 16; - gLinkStatusResponseFrame.linkStatusResponse.OEMLinkStatus_Low = OEMLinkStatus & 0xffff; - gLinkStatusResponseFrame.linkStatusResponse.OtherIndications_High = OtherIndications >> 16; - gLinkStatusResponseFrame.linkStatusResponse.OtherIndications_Low = OtherIndications & 0xffff; + txControl.bits.LastByteCount = packet_len % sizeof(uint32_t); // Wait for enough free space. while(APE_PERI.BmcToNcTxStatus.bits.InFifo < packetWords); @@ -622,57 +621,59 @@ void sendNCSILinkStatusResponse(uint8_t InstanceID, uint8_t channelID, uint32_t for(int i = 0; i < packetWords-1; i++) { #if CXX_SIMULATOR - printf("Transmitting word %d: 0x%08x\n", i, gLinkStatusResponseFrame.words[i]); + printf("Transmitting word %d: 0x%08x\n", i, packet[i]); #endif - APE_PERI.BmcToNcTxBuffer.r32 = gLinkStatusResponseFrame.words[i]; + APE_PERI.BmcToNcTxBuffer.r32 = packet[i]; } APE_PERI.BmcToNcTxControl = txControl; #if CXX_SIMULATOR - printf("Transmitting last word %d: 0x%08x\n", packetWords - 1, gLinkStatusResponseFrame.words[packetWords - 1]); + printf("Transmitting last word %d: 0x%08x\n", packetWords - 1, packet[packetWords - 1]); #endif + APE_PERI.BmcToNcTxBufferLast.r32 = packet[packetWords - 1]; +} +void sendNCSILinkStatusResponse(uint8_t InstanceID, uint8_t channelID, uint32_t LinkStatus, uint32_t OEMLinkStatus, uint32_t OtherIndications) +{ + uint32_t packetSize = ETHERNET_FRAME_MIN - 4; - APE_PERI.BmcToNcTxBufferLast.r32 = gLinkStatusResponseFrame.words[packetWords - 1]; + gLinkStatusResponseFrame.linkStatusResponse.ChannelID = channelID; + gLinkStatusResponseFrame.linkStatusResponse.InstanceID = InstanceID; + gLinkStatusResponseFrame.linkStatusResponse.ResponseCode = NCSI_RESPONSE_CODE_COMMAND_COMPLETE; + gLinkStatusResponseFrame.linkStatusResponse.ReasonCode = NCSI_REASON_CODE_NONE; + + gLinkStatusResponseFrame.linkStatusResponse.LinkStatus_High = LinkStatus >> 16; + gLinkStatusResponseFrame.linkStatusResponse.LinkStatus_Low = LinkStatus & 0xffff; + gLinkStatusResponseFrame.linkStatusResponse.OEMLinkStatus_High = OEMLinkStatus >> 16; + gLinkStatusResponseFrame.linkStatusResponse.OEMLinkStatus_Low = OEMLinkStatus & 0xffff; + gLinkStatusResponseFrame.linkStatusResponse.OtherIndications_High = OtherIndications >> 16; + gLinkStatusResponseFrame.linkStatusResponse.OtherIndications_Low = OtherIndications & 0xffff; + + + NCSI_TxPacket(gLinkStatusResponseFrame.words, packetSize); } void sendNCSIResponse(uint8_t InstanceID, uint8_t channelID, uint16_t controlID, uint16_t response_code, uint16_t reasons_code) { uint32_t packetSize = ETHERNET_FRAME_MIN - 4; - uint32_t packetWords = ((packetSize + 3) / 4); - uint32_t lastBytes = packetSize % 4; - - RegAPE_PERIBmcToNcTxControl_t txControl; - txControl.r32 = 0; - txControl.bits.LastByteCount = lastBytes; gResponseFrame.responsePacket.ChannelID = channelID; gResponseFrame.responsePacket.ControlPacketType = controlID | CONTROL_PACKET_TYPE_RESPONSE; gResponseFrame.responsePacket.InstanceID = InstanceID; - // Payload data - 4 bytes + gResponseFrame.responsePacket.ResponseCode = response_code; gResponseFrame.responsePacket.ReasonCode = reasons_code; - // NetworkFrame_t frame; - // frame. - // Wait for enough free space. - while(APE_PERI.BmcToNcTxStatus.bits.InFifo < packetWords); + NCSI_TxPacket(gResponseFrame.words, packetSize); +} - // Transmit. - for(int i = 0; i < packetWords-1; i++) +void NCSI_init(void) +{ + for(int i = 0; i < ARRAY_ELEMENTS(gPackageState.channel); i++) { -#if CXX_SIMULATOR - printf("Transmitting word %d: 0x%08x\n", i, gResponseFrame.words[i]); -#endif - APE_PERI.BmcToNcTxBuffer.r32 = gResponseFrame.words[i]; + gPackageState.channel[i].shm->NcsiChannelInfo.bits.Ready = false; } +} - APE_PERI.BmcToNcTxControl = txControl; - -#if CXX_SIMULATOR - printf("Transmitting last word %d: 0x%08x\n", packetWords - 1, gResponseFrame.words[packetWords - 1]); -#endif - APE_PERI.BmcToNcTxBufferLast.r32 = gResponseFrame.words[packetWords - 1]; -} diff --git a/libs/NCSI/tests/tests.cpp b/libs/NCSI/tests/tests.cpp index c74a1fd..efcc35a 100644 --- a/libs/NCSI/tests/tests.cpp +++ b/libs/NCSI/tests/tests.cpp @@ -3,14 +3,12 @@ #include <APE_APE_PERI.h> #include <Ethernet.h> #include <NCSI.h> - - #include <endian.h> uint32_t *gPacket; uint32_t gPacketLen; -uint32_t gTXPacket[0x300/4]; +uint32_t gTXPacket[0x300 / 4]; uint32_t gTXPacketPos; extern uint8_t select_package1[]; @@ -47,15 +45,14 @@ extern uint32_t disable_network_tx_len; extern uint32_t disable_channel_len; extern uint32_t deselect_package_len; - static uint32_t read_packet(uint32_t val, uint32_t offset, void *args) { uint32_t data = 0; - if(gPacketLen > 0) + if (gPacketLen > 0) { data = *gPacket; gPacket++; - if(gPacketLen > 4) + if (gPacketLen > 4) { gPacketLen -= 4; } @@ -63,7 +60,7 @@ static uint32_t read_packet(uint32_t val, uint32_t offset, void *args) { gPacketLen = 0; } - } + } return htobe32(data); } @@ -89,17 +86,15 @@ static uint32_t read_tx_status(uint32_t val, uint32_t offset, void *args) { RegAPE_PERIBmcToNcTxStatus_t stat; stat.r32 = 0; - stat.bits.InFifo = sizeof(gTXPacket) - (gTXPacketPos*4); + stat.bits.InFifo = sizeof(gTXPacket) - (gTXPacketPos * 4); return stat.r32; } - - -void send_packet(uint8_t* packet, uint32_t len) +void send_packet(uint8_t *packet, uint32_t len) { gTXPacketPos = 0; // reset response position. - gPacket = (uint32_t*)packet; + gPacket = (uint32_t *)packet; gPacketLen = len; uint32_t buffer[1024]; @@ -108,11 +103,11 @@ void send_packet(uint8_t* packet, uint32_t len) stat.r32 = APE_PERI.BmcToNcRxStatus.r32; // stat.print(); - if(stat.bits.New) + if (stat.bits.New) { int32_t bytes = stat.bits.PacketLength; int i = 0; - while(bytes > 0) + while (bytes > 0) { uint32_t word = (APE_PERI.BmcToNcReadBuffer.r32); buffer[i] = word; @@ -121,15 +116,16 @@ void send_packet(uint8_t* packet, uint32_t len) bytes -= 4; } - NetworkFrame_t *frame = ((NetworkFrame_t*)buffer); + NetworkFrame_t *frame = ((NetworkFrame_t *)buffer); - if(stat.bits.Bad) + if (stat.bits.Bad) { // TODO: ACK bad packet. APE_PERI.BmcToNcRxControl.bits.ResetBad = 1; - while(APE_PERI.BmcToNcRxControl.bits.ResetBad); + while (APE_PERI.BmcToNcRxControl.bits.ResetBad) + ; } - else if(!stat.bits.Passthru) + else if (!stat.bits.Passthru) { handleNCSIFrame(frame); @@ -137,8 +133,9 @@ void send_packet(uint8_t* packet, uint32_t len) EXPECT_EQ(gTXPacket[1], 0xffffffff); // Source/Dest MAC EXPECT_EQ(gTXPacket[2], 0xffffffff); // Dest MAC EXPECT_EQ(gTXPacket[3], 0x88f80001); // NCSI Type, Revision 1. - EXPECT_EQ(gTXPacket[4], buffer[4] | 0x8000); // IID, Channel, Package, Command | 0x80 - + EXPECT_EQ(gTXPacket[4], + buffer[4] | + 0x8000); // IID, Channel, Package, Command | 0x80 } else { @@ -147,10 +144,11 @@ void send_packet(uint8_t* packet, uint32_t len) } } +namespace +{ -namespace { - -TEST(Packet, SelectPackage) { +TEST(Packet, SelectPackage) +{ APE_PERI.BmcToNcRxStatus.r32.installReadCallback(read_rx_status, NULL); APE_PERI.BmcToNcReadBuffer.r32.installReadCallback(read_packet, NULL); APE_PERI.BmcToNcTxStatus.r32.installReadCallback(read_tx_status, NULL); @@ -158,8 +156,7 @@ TEST(Packet, SelectPackage) { APE_PERI.BmcToNcTxBuffer.r32.installWriteCallback(write_packet, NULL); APE_PERI.BmcToNcTxBufferLast.r32.installWriteCallback(write_packet, NULL); - send_packet(select_package1, select_package1_len); } -} // namespace +} // namespace diff --git a/libs/NCSI/tests/valid_commands.c b/libs/NCSI/tests/valid_commands.c index 1667f0f..5288f4f 100644 --- a/libs/NCSI/tests/valid_commands.c +++ b/libs/NCSI/tests/valid_commands.c @@ -1,146 +1,177 @@ #include <stdint.h> - // Select Packate uint8_t select_package1[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xed, 0x01, 0x1f, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0xff, 0xff, 0xfd, 0xee, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xed, 0x01, 0x1f, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0xff, 0xff, 0xfd, 0xee, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t select_package1_len = sizeof(select_package1); // Clear Initial State uint8_t clear_initial_state[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xee, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xee, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, + 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t clear_initial_state_len = sizeof(clear_initial_state); // Disable VLAN uint8_t disable_vlan[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xef, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf2, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xef, 0x0d, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf2, + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t disable_vlan_len = sizeof(disable_vlan); // Set MAC Address uint8_t set_mac_addr[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf0, 0x0e, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x09, - 0x4d, 0x00, 0x01, 0x4a, 0x01, 0x01, 0xff, 0xff, 0x75, 0xb3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf0, 0x0e, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x09, 0x4d, + 0x00, 0x01, 0x4a, 0x01, 0x01, 0xff, 0xff, 0x75, 0xb3, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t set_mac_addr_len = sizeof(set_mac_addr); // Enable Broadcast Filter uint8_t enable_bcast_filter[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf1, 0x10, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0xff, 0xff, 0xee, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf1, 0x10, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0f, 0xff, 0xff, 0xee, 0xfb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t enable_bcast_filter_len = sizeof(enable_bcast_filter); // Enable Network TX uint8_t enable_network_tx[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf2, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf9, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf2, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf9, + 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t enable_network_tx_len = sizeof(enable_network_tx); // Enable Channel uint8_t enable_channel[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf3, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xfc, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf3, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, + 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t enable_channel_len = sizeof(enable_channel); // AEN Enable uint8_t aen_enable[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf4, 0x08, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xf6, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf4, 0x08, 0x00, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xf6, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t aen_enable_len = sizeof(aen_enable); // Get Link Status Ch0 uint8_t get_link_status_ch0[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf5, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf5, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf5, 0x0a, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf5, + 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t get_link_status_ch0_len = sizeof(get_link_status_ch0); // Select Package uint8_t select_package2[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xf8, 0x01, 0x1f, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0xff, 0xff, 0xfd, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xf8, 0x01, 0x1f, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0xff, 0xff, 0xfd, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t select_package2_len = sizeof(select_package2); // Get Link Status Ch1 uint8_t get_link_status_ch1[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xfa, 0x0a, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf5, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xfa, 0x0a, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf5, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t get_link_status_ch1_len = sizeof(get_link_status_ch1); // Get Link Status Ch2 uint8_t get_link_status_ch2[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xfb, 0x0a, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf5, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xfb, 0x0a, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf5, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t get_link_status_ch2_len = sizeof(get_link_status_ch2); // Get Link Status Ch3 uint8_t get_link_status_ch3[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xfc, 0x0a, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xfc, 0x0a, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf5, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t get_link_status_ch3_len = sizeof(get_link_status_ch3); // Disable Network Tx uint8_t disable_network_tx[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xfd, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xf8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xfd, 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xf8, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t disable_network_tx_len = sizeof(disable_network_tx); // Disable Channel uint8_t disable_channel[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xfe, 0x04, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0xff, 0xff, 0xfa, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xfe, 0x04, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0xff, 0xff, 0xfa, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t disable_channel_len = sizeof(disable_channel); // Deselect Package uint8_t deselect_package[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0xf8, 0x00, 0x01, - 0x00, 0xff, 0x02, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xfc, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x88, 0xf8, 0x00, 0x01, 0x00, 0xff, 0x02, 0x1f, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, + 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; uint32_t deselect_package_len = sizeof(deselect_package); diff --git a/libs/NVRam/crc.c b/libs/NVRam/crc.c index dc1d560..d3dd384 100644 --- a/libs/NVRam/crc.c +++ b/libs/NVRam/crc.c @@ -47,8 +47,8 @@ #define CRC32_POLYNOMIAL 0xEDB88320 uint32_t NVRam_crc(const uint8_t *pcDatabuf, // Pointer to data buffer - uint32_t ulDatalen, // Length of data buffer in bytes - uint32_t crc) // Initial value + uint32_t ulDatalen, // Length of data buffer in bytes + uint32_t crc) // Initial value { uint8_t data; uint32_t idx, bit; diff --git a/libs/NVRam/include/NVRam.h b/libs/NVRam/include/NVRam.h index 405f6e9..3626ec5 100644 --- a/libs/NVRam/include/NVRam.h +++ b/libs/NVRam/include/NVRam.h @@ -63,7 +63,7 @@ void NVRam_disable(void); void NVRam_disableWrites(void); uint32_t NVRam_crc(const uint8_t *pcDatabuf, // Pointer to data buffer - uint32_t ulDatalen, // Length of data buffer in bytes - uint32_t crc); // Initial value + uint32_t ulDatalen, // Length of data buffer in bytes + uint32_t crc); // Initial value #endif /* NVRAM_H */ diff --git a/libs/NVRam/nvm.c b/libs/NVRam/nvm.c index dbbad58..bf494f6 100644 --- a/libs/NVRam/nvm.c +++ b/libs/NVRam/nvm.c @@ -108,7 +108,6 @@ void NVRam_disableWrites(void) NVM.Access.bits.WriteEnable = 0; } - static inline void NVRam_waitDone(void) { while (!NVM.Command.bits.Done) @@ -223,7 +222,7 @@ void NVRam_read(uint32_t address, uint32_t *buffer, size_t words) void NVRam_writeWord(uint32_t address, uint32_t data) { - if(data != NVRam_readWord(address)) + if (data != NVRam_readWord(address)) { // Only write if different. diff --git a/libs/Network/CMakeLists.txt b/libs/Network/CMakeLists.txt new file mode 100644 index 0000000..a393172 --- /dev/null +++ b/libs/Network/CMakeLists.txt @@ -0,0 +1,60 @@ +################################################################################ +### +### @file libs/Network/CMakeLists.txt +### +### @project +### +### @brief Network CMake file +### +################################################################################ +### +################################################################################ +### +### @copyright Copyright (c) 2019, Evan Lojewski +### @cond +### +### All rights reserved. +### +### Redistribution and use in source and binary forms, with or without +### modification, are permitted provided that the following conditions are met: +### 1. Redistributions of source code must retain the above copyright notice, +### this list of conditions and the following disclaimer. +### 2. Redistributions in binary form must reproduce the above copyright notice, +### this list of conditions and the following disclaimer in the documentation +### and/or other materials provided with the distribution. +### 3. Neither the name of the copyright holder nor the +### names of its contributors may be used to endorse or promote products +### derived from this software without specific prior written permission. +### +################################################################################ +### +### THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +### AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +### IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +### ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +### LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +### CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +### SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +### INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +### CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +### ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +### POSSIBILITY OF SUCH DAMAGE. +### @endcond +################################################################################ + +project(Network) + + +# Host Simulation library +simulator_add_library(${PROJECT_NAME} STATIC tx.c rx.c generic.c) +target_link_libraries(${PROJECT_NAME} PRIVATE simulator NCSI) +target_include_directories(${PROJECT_NAME} PUBLIC ../../include) +target_include_directories(${PROJECT_NAME} PUBLIC include) + +# ARM Library +arm_add_library(${PROJECT_NAME}-arm STATIC init.c tx.c rx.c generic.c) +target_link_libraries(${PROJECT_NAME}-arm PRIVATE NCSI-arm) +target_include_directories(${PROJECT_NAME}-arm PUBLIC ../../include) +target_include_directories(${PROJECT_NAME}-arm PUBLIC include) + +# add_subdirectory(tests)
\ No newline at end of file diff --git a/libs/Network/generic.c b/libs/Network/generic.c new file mode 100644 index 0000000..f15c58c --- /dev/null +++ b/libs/Network/generic.c @@ -0,0 +1,73 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file init.c +/// +/// @project +/// +/// @brief Initialization code for TX to network / RX from network. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the copyright holder nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_DEVICE.h> +#include <Network.h> + +void Network_SetMACAddr(uint16_t high, uint32_t low, uint32_t index, + bool enabled) +{ + uint32_t match_high = (high << 16) | (low >> 16); + uint16_t match_low = (low << 16); + + APE_PERI.BmcToNcSourceMacMatch0High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch0Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch1High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch1Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch2High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch2Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch3High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch3Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch4High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch4Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch5High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch5Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch6High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch6Low.r32 = match_low; + APE_PERI.BmcToNcSourceMacMatch7High.r32 = match_high; + APE_PERI.BmcToNcSourceMacMatch7Low.r32 = match_low; + + DEVICE.PerfectMatch1High.r32 = high; + DEVICE.PerfectMatch1Low.r32 = low; +}
\ No newline at end of file diff --git a/libs/Network/include/Network.h b/libs/Network/include/Network.h new file mode 100644 index 0000000..06bd57f --- /dev/null +++ b/libs/Network/include/Network.h @@ -0,0 +1,71 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file Network.h +/// +/// @project +/// +/// @brief Network TX/RX Support Routines +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2019, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the copyright holder nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#ifndef NETWORK_H +#define NETWORK_H + +#include <APE_APE_PERI.h> +#include <stdbool.h> +#include <stdint.h> + +void Network_InitTxRx(void); + +uint32_t Network_TX_numBlocksNeeded(uint32_t frame_size); +int32_t Network_TX_allocateBlock(void); + +void Network_TX_transmitBePacket(uint8_t *packet, uint32_t length); +void Network_TX_transmitLePacket(uint8_t *packet, uint32_t length); + +void Network_TX_transmitPassthroughPacket(uint32_t length); + +// void Network_TX_transmitPassthroughPacket(RegAPE_PERIBmcToNcRxStatus_t +// rx_status); + +bool Network_RxLePatcket(uint32_t *buffer, uint32_t *length); +bool Network_PassthroughRxPatcket(void); + +void Network_SetMACAddr(uint16_t high, uint32_t low, uint32_t index, + bool enabled); + +#endif /* NETWORK_H */
\ No newline at end of file diff --git a/ape/rx_from_network.c b/libs/Network/init.c index a1b09fb..e50cdba 100644 --- a/ape/rx_from_network.c +++ b/libs/Network/init.c @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file rx_from_network.c +/// @file init.c /// /// @project /// -/// @brief Initialization code for RX from network. +/// @brief Initialization code for TX to network / RX from network. /// //////////////////////////////////////////////////////////////////////////////// /// @@ -42,9 +42,11 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -#include "ape.h" - #include <APE_FILTERS.h> +#include <APE_APE.h> +#include <APE_DEVICE.h> + +#include <Network.h> typedef struct { RegFILTERSElementConfig_t cfg; @@ -639,7 +641,7 @@ static const FilterRuleInit_t gRuleInit[32] = { }, }; -void initRxFromNetwork(void) +void Network_InitTxRx(void) { for(int i = 0; i < 32; i++) { @@ -654,4 +656,62 @@ void initRxFromNetwork(void) } FILTERS.RuleConfiguration.r32 = 0; + + + // REG_APE_PERFECT_MATCH1_{HIGH,LOW}. For non-broadcast/multicast traffic, the hardware uses this register to match MACs and pass traffic to the APE. + // The first two bytes of a MAC are put in the HIGH register, and the remaining four bytes in the LOW. + // Note that this is a device (PCI) register, not an APE register. Set it to the BMC MAC. + + + // REG_APE__BMC_NC_RX_SRC_MAC_MATCHN_{HIGH,LOW}. + // This appears to relate to the RMU, not network RX, but its exact purpose is unknown. + // Set it to the BMC MAC. Unlike the "perfect match" register above, it takes a different format: + // for an example MAC AABB.CCDD.EEFF, set HIGH=0xAABBCCDD, LOW=0xEEFF0000. + // *** NOTE: set to 0 in rmu.c *** + + + // Ensure REG_RECEIVE_MAC_MODE has ENABLE set. + // I recommend also setting APE_PROMISCUOUS_MODE and PROMISCUOUS_MODE, + // as these will cause you less headaches during development. + RegDEVICEReceiveMacMode_t macMode; + macMode = DEVICE.ReceiveMacMode; + macMode.bits.Enable = 1; + macMode.bits.APEPromiscuousMode = 0; + DEVICE.ReceiveMacMode = macMode; + + + // Ensure REG_EMAC_MODE__ENABLE_APE_{TX,RX}_PATH are set. + // *** NOTE: Both bits are set in rmu.c ***/ + + // Enable APE channel 0/0 + RegAPEMode_t mode; + mode = APE.Mode; + mode.bits.Event1 = 1; + mode.bits.Channel0Enable = 1; + mode.bits.Channel2Enable = 1; + APE.Mode = mode; + + + + + // Enable RX for funciton 0 + RegAPERxPoolModeStatus0_t rxMode; + rxMode.r32 = 0; + rxMode.bits.Reset = 1; + APE.RxPoolModeStatus0 = rxMode; + + rxMode.bits.Reset = 0; + rxMode.bits.Enable = 1; + APE.RxPoolModeStatus0 = rxMode; + + // Enable TX for function 0 + RegAPETxToNetPoolModeStatus0_t txMode; + txMode.r32 = 0; + txMode.bits.Reset = 1; + APE.TxToNetPoolModeStatus0 = txMode; + + txMode.bits.Reset = 0; + txMode.bits.Enable = 1; + APE.TxToNetPoolModeStatus0 = txMode; + } diff --git a/libs/Network/rx.c b/libs/Network/rx.c new file mode 100644 index 0000000..fd6e883 --- /dev/null +++ b/libs/Network/rx.c @@ -0,0 +1,241 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file rx.c +/// +/// @project +/// +/// @brief Network reception routines +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2019, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the copyright holder nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_APE.h> +#include <APE_APE_PERI.h> +#include <APE_RX_PORT.h> +#include <Ethernet.h> +#include <Network.h> +#include <stdbool.h> +#include <types.h> + +#ifdef CXX_SIMULATOR +#include <stdio.h> +#endif + +bool Network_RxLePatcket(uint32_t *buffer, uint32_t *bytes) +{ + RegAPERxbufoffsetFunc0_t rxbuf; + rxbuf = APE.RxbufoffsetFunc0; + if ((int)rxbuf.bits.Valid) + { + uint32_t rx_bytes = 0; + union { + uint32_t r32; + struct + { + uint32_t payload_length:7; + uint32_t next_block:23; + uint32_t first:1; + uint32_t not_last:1; + } bits; + } control; + int count = rxbuf.bits.Count; + // int tailid = rxbuf.bits.Tail; + int blockid = rxbuf.bits.Head; + // printf("Valid packet at offset %x\n", blockid); + uint32_t buffer_pos = 0; + + do + { + // printf("Block at %x\n", blockid); + RegRX_PORTIn_t *block = (RegRX_PORTIn_t *)&RX_PORT.In[RX_PORT_IN_ALL_BLOCK_WORDS * blockid]; + // printf("Control %x\n", (uint32_t)block[0].r32); + control.r32 = block[0].r32; + // printf(" Payload Len %d\n", control.bits.payload_length); + // printf(" Next Block %d\n", control.bits.next_block); + // printf(" First %d\n", control.bits.first); + // printf(" Not Last %d\n", control.bits.not_last); + int32_t words = DIVIDE_RND_UP(control.bits.payload_length, sizeof(uint32_t)); + rx_bytes += control.bits.payload_length; + int32_t offset; + if (control.bits.first) + { + offset = RX_PORT_IN_ALL_FIRST_PAYLOAD_WORD; + } + else + { + offset = RX_PORT_IN_ALL_ADDITIONAL_PAYLOAD_WORD; + } + // printf("Using offset %d\n", offset); + for (int i = 0; i < words; i++) + { + uint32_t data = block[i + offset].r32; + buffer[buffer_pos++] = data; + // printf(" word %d: 0x%08X\n", i, data); + } + + blockid = control.bits.next_block; + count--; + } while (count); + + // Transmit to NC + // disableNCSIHandling(); + // enableNCSIHandling(); + + RegAPERxPoolRetire0_t retire; + retire.r32 = 0; + retire.bits.Head = rxbuf.bits.Head; + retire.bits.Tail = rxbuf.bits.Tail; + retire.bits.Count = rxbuf.bits.Count; + retire.bits.Retire = 1; + APE.RxPoolRetire0 = retire; + + rxbuf.bits.Finished = 1; + APE.RxbufoffsetFunc0 = rxbuf; + + *bytes = rx_bytes; + + return true; + } + else + { + return false; + } +} + +bool Network_PassthroughRxPatcket(void) +{ + RegAPERxbufoffsetFunc0_t rxbuf; + rxbuf = APE.RxbufoffsetFunc0; + if ((int)rxbuf.bits.Valid) + { +#if CXX_SIMULATOR + rxbuf.print(); +#endif + union { + uint32_t r32; + struct + { + uint32_t payload_length:7; + uint32_t next_block:23; + uint32_t first:1; + uint32_t not_last:1; + } bits; + } control; + int count = rxbuf.bits.Count; + // int tailid = rxbuf.bits.Tail; + int blockid = rxbuf.bits.Head; + + while (count--) + { + // printf("Block at %x\n", blockid); + RegRX_PORTIn_t *block = (RegRX_PORTIn_t *)&RX_PORT.In[RX_PORT_IN_ALL_BLOCK_WORDS * blockid]; + // printf("Control %x\n", (uint32_t)block[0].r32); + control.r32 = block[0].r32; + // printf(" Payload Len %d\n", control.bits.payload_length); + // printf(" Next Block %d\n", control.bits.next_block); + // printf(" First %d\n", control.bits.first); + // printf(" Not Last %d\n", control.bits.not_last); +#if CXX_SIMULATOR + printf("%d bytes in block.\n", control.bits.payload_length); +#endif + int32_t words = DIVIDE_RND_UP(control.bits.payload_length, sizeof(uint32_t)); + int32_t offset; + if (control.bits.first) + { + offset = RX_PORT_IN_ALL_FIRST_PAYLOAD_WORD; + } + else + { + offset = RX_PORT_IN_ALL_ADDITIONAL_PAYLOAD_WORD; + } + + // Wait for enough free space. + while (APE_PERI.BmcToNcTxStatus.bits.InFifo < words) + ; + + int i; + uint32_t data; + if (!control.bits.not_last) + { + // Ignore last word - drop the FCS + words--; + } + + for (i = 0; i < words - 1; i++) + { + data = block[i + offset].r32; + APE_PERI.BmcToNcTxBuffer.r32 = data; + } + + data = block[i + offset].r32; + if (control.bits.not_last) + { + APE_PERI.BmcToNcTxBuffer.r32 = data; + } + else + { + // data = block[i + offset].r32; + // Last word to send. + APE_PERI.BmcToNcTxControl.r32 = control.bits.payload_length % sizeof(uint32_t); + APE_PERI.BmcToNcTxBufferLast.r32 = data; + + // Ignore last word - drop the FCS. + // data = block[i + offset + 1].r32; + // (void)data; + } + + // Retire this block. + RegAPERxPoolRetire0_t retire; + retire.r32 = (1 << 24); + retire.bits.Head = blockid; + retire.bits.Tail = blockid; + retire.bits.Count = 1; + APE.RxPoolRetire0 = retire; + + blockid = control.bits.next_block; + } + + // Mark the frame as read. + rxbuf.bits.Finished = 1; + APE.RxbufoffsetFunc0 = rxbuf; + + return true; + } + else + { + return false; + } +}
\ No newline at end of file diff --git a/libs/Network/tx.c b/libs/Network/tx.c new file mode 100644 index 0000000..a2e998f --- /dev/null +++ b/libs/Network/tx.c @@ -0,0 +1,498 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file tx.c +/// +/// @project +/// +/// @brief Network transmission routines +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2019, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the copyright holder nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_APE.h> +#include <APE_TX_PORT.h> +#include <Ethernet.h> +#include <Network.h> +#include <stdbool.h> +#include <types.h> + +#ifdef CXX_SIMULATOR +#include <endian.h> +#include <stdio.h> +#else +/* ARM */ +static inline uint32_t be32toh(uint32_t be32) +{ + uint32_t he32 = ((be32 & 0xFF000000) >> 24) | + ((be32 & 0x00FF0000) >> 8) | + ((be32 & 0x0000FF00) << 8) | + ((be32 & 0x000000FF) << 24); + + return he32; +} +#endif + +#define FIRST_FRAME_MAX ((TX_PORT_OUT_ALL_BLOCK_WORDS - TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD) * sizeof(uint32_t)) +#define ADDITIONAL_FRAME_MAX ((TX_PORT_OUT_ALL_BLOCK_WORDS - TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD) * sizeof(uint32_t)) + +typedef union { + uint32_t r32; + struct + { + uint32_t payload_length:7; + uint32_t next_block:23; + uint32_t first:1; + uint32_t not_last:1; + } bits; +} control_t; + +uint32_t Network_TX_numBlocksNeeded(uint32_t frame_size) +{ + uint32_t blocks = 1; + + if (frame_size > FIRST_FRAME_MAX) + { + frame_size -= FIRST_FRAME_MAX; + + blocks += DIVIDE_RND_UP(frame_size, ADDITIONAL_FRAME_MAX); + } + +#ifdef CXX_SIMULATOR + printf("%d blocks needed for packet with frame size %d\n", blocks, + frame_size); +#endif + return blocks; +} + +int32_t __attribute__((noinline)) Network_TX_allocateBlock(void) +{ + int32_t block; + + // Set the alloc bit. + RegAPETxToNetBufferAllocator0_t alloc; + alloc.r32 = 0; + alloc.bits.RequestAllocation = 1; + APE.TxToNetBufferAllocator0 = alloc; + + // Wait for state machine to finish + RegAPETxToNetBufferAllocator0_t status; + do + { + status = APE.TxToNetBufferAllocator0; + } while (APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_PROCESSING == status.bits.State); + + if (APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ALLOCATION_OK != status.bits.State) + { + block = -1; +#if CXX_SIMULATOR + printf("Error: Failed to allocate TX block.\n"); +#endif + } + else + { + block = status.bits.Index; +#if CXX_SIMULATOR + printf("Allocated TX block %d\n", block); +#endif + } + + return block; +} + +static uint32_t inline Network_TX_initFirstBlock(RegTX_PORTOut_t *block, + uint32_t length, + int32_t blocks, + int32_t next_block, + uint32_t *packet, + bool big_endian) +{ + control_t control; + int copy_length; + int i; + + control.r32 = 0; + control.bits.next_block = next_block >= 0 ? next_block : 0; + control.bits.first = 1; + + if (length > FIRST_FRAME_MAX) + { + copy_length = FIRST_FRAME_MAX; + control.bits.not_last = 1; + } + else + { + // Last. + copy_length = length; + control.bits.not_last = 0; + } + + // block[1] = uninitialized; + block[2].r32 = 0; + block[TX_PORT_OUT_ALL_FRAME_LEN_WORD].r32 = length; + block[4].r32 = 0; + block[5].r32 = 0; + block[6].r32 = 0; + block[7].r32 = 0; + block[8].r32 = 0; + block[TX_PORT_OUT_ALL_NUM_BLOCKS_WORD].r32 = blocks; + // block[10] = uninitialized; + // block[11] = uninitialized; + + // Copy Payload Data. + int num_words = (copy_length + sizeof(uint32_t) - 1) / sizeof(uint32_t); + for (i = 0; i < num_words; i++) + { + if (big_endian) + { +#if CXX_SIMULATOR + printf("1st[%d] = 0x%08X\n", i, be32toh(packet[i])); +#endif + block[TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD + i].r32 = be32toh(packet[i]); + } + else + { +#if CXX_SIMULATOR + printf("1LE[%d] = 0x%08X\n", i, (packet[i])); +#endif + block[TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD + i].r32 = (packet[i]); + } + } + + length -= control.bits.payload_length; + + // Pad if too small. + if (copy_length < ETHERNET_FRAME_MIN) + { + copy_length = ETHERNET_FRAME_MIN; + length = ETHERNET_FRAME_MIN; + + num_words = DIVIDE_RND_UP(copy_length, sizeof(uint32_t)); + for (; i < num_words; i++) + { + // Pad remaining with 0's + block[TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD + i].r32 = 0; + } + } + + control.bits.payload_length = copy_length; + + block[TX_PORT_OUT_ALL_CONTROL_WORD].r32 = control.r32; + + return copy_length; +} + +static uint32_t inline Network_TX_initAdditionalBlock(RegTX_PORTOut_t *block, + int32_t next_block, + uint32_t length, + uint32_t *packet, + bool big_endian) +{ + int i; + control_t control; + + control.r32 = 0; + control.bits.first = 0; + control.bits.next_block = next_block; + + if (length > ADDITIONAL_FRAME_MAX) + { + length = ADDITIONAL_FRAME_MAX; + control.bits.payload_length = ADDITIONAL_FRAME_MAX; + control.bits.not_last = 1; + } + else + { + // Last + control.bits.payload_length = length; + control.bits.not_last = 0; + } + + // block[1] = uninitialized; + + // Copy payload data. + int num_words = DIVIDE_RND_UP(length, sizeof(uint32_t)); + for (i = 0; i < num_words; i++) + { + if (big_endian) + { + block[TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD + i].r32 = be32toh(packet[i]); + } + else + { + block[TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD + i].r32 = (packet[i]); + } + } + + block[TX_PORT_OUT_ALL_CONTROL_WORD].r32 = control.r32; + + length -= control.bits.payload_length; + + return control.bits.payload_length; +} + +static inline void Network_TX_transmitPacket_internal(uint8_t *packet, + uint32_t length, + bool big_endian) +{ + if (!length) + { + return; + } + + uint32_t *packet_32 = (uint32_t *)packet; + uint32_t consumed = 0; + uint32_t blocks = Network_TX_numBlocksNeeded(length); + int total_blocks = blocks; + ; + + // First block + int32_t tail; + int32_t first = tail = Network_TX_allocateBlock(); + if (first <= 0) + { + // Error + return; + } + int32_t next_block = -1; + if (blocks > 1) + { + next_block = Network_TX_allocateBlock(); + } + RegTX_PORTOut_t *block = (RegTX_PORTOut_t *)&TX_PORT.Out[TX_PORT_OUT_ALL_BLOCK_WORDS * first]; + + consumed += Network_TX_initFirstBlock(block, length, blocks, next_block, + &packet_32[consumed / 4], big_endian); + blocks -= 1; + while (blocks--) + { + + block = (RegTX_PORTOut_t *)&TX_PORT + .Out[TX_PORT_OUT_ALL_BLOCK_WORDS * next_block]; + if (blocks) + { + next_block = Network_TX_allocateBlock(); + consumed += Network_TX_initAdditionalBlock( + block, next_block, length - consumed, &packet_32[consumed / 4], + big_endian); + } + else + { + Network_TX_initAdditionalBlock(block, 0, length - consumed, + &packet_32[consumed / 4], + big_endian); + } + + tail = next_block; + } + + RegAPETxToNetDoorbellFunc0_t doorbell; + doorbell.r32 = 0; + doorbell.bits.Head = first; + doorbell.bits.Tail = tail; + doorbell.bits.Length = total_blocks; + + APE.TxToNetDoorbellFunc0 = doorbell; +} + +void Network_TX_transmitBePacket(uint8_t *packet, uint32_t length) +{ + Network_TX_transmitPacket_internal(packet, length, true); +} + +void Network_TX_transmitLePacket(uint8_t *packet, uint32_t length) +{ + Network_TX_transmitPacket_internal(packet, length, false); +} + +static uint32_t inline Network_TX_initFirstPassthroughBlock( + RegTX_PORTOut_t *block, uint32_t length, int32_t blocks, int32_t next_block) +{ + control_t control; + int copy_length; + int i; + + control.r32 = 0; + control.bits.next_block = next_block >= 0 ? next_block : 0; + control.bits.first = 1; + + if (length > FIRST_FRAME_MAX) + { + copy_length = FIRST_FRAME_MAX; + control.bits.not_last = 1; + } + else + { + // Last. + copy_length = length; + control.bits.not_last = 0; + } + + // block[1] = uninitialized; + block[2].r32 = 0; + block[TX_PORT_OUT_ALL_FRAME_LEN_WORD].r32 = length; + block[4].r32 = 0; + block[5].r32 = 0; + block[6].r32 = 0; + block[7].r32 = 0; + block[8].r32 = 0; + block[TX_PORT_OUT_ALL_NUM_BLOCKS_WORD].r32 = blocks; + // block[10] = uninitialized; + // block[11] = uninitialized; + + // Copy Payload Data. + int num_words = DIVIDE_RND_UP(copy_length, sizeof(uint32_t)); + for (i = 0; i < num_words; i++) + { + block[TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD + i].r32 = APE_PERI.BmcToNcReadBuffer.r32; + } + + length -= control.bits.payload_length; + + // Pad if too small. + if (copy_length < ETHERNET_FRAME_MIN) + { + copy_length = ETHERNET_FRAME_MIN; + length = ETHERNET_FRAME_MIN; + + num_words = DIVIDE_RND_UP(copy_length, sizeof(uint32_t)); + for (; i < num_words; i++) + { + // Pad remaining with 0's + block[TX_PORT_OUT_ALL_FIRST_PAYLOAD_WORD + i].r32 = 0; + } + } + + control.bits.payload_length = copy_length; + + block[TX_PORT_OUT_ALL_CONTROL_WORD].r32 = control.r32; + + return copy_length; +} + +static uint32_t inline Network_TX_initAdditionalPassthroughBlock( + RegTX_PORTOut_t *block, int32_t next_block, uint32_t length) +{ + int i; + control_t control; + + control.r32 = 0; + control.bits.first = 0; + control.bits.next_block = next_block; + + if (length > ADDITIONAL_FRAME_MAX) + { + length = ADDITIONAL_FRAME_MAX; + control.bits.payload_length = ADDITIONAL_FRAME_MAX; + control.bits.not_last = 1; + } + else + { + // Last + control.bits.payload_length = length; + control.bits.not_last = 0; + } + + // block[1] = uninitialized; + + // Copy payload data. + int num_words = DIVIDE_RND_UP(length, sizeof(uint32_t)); + for (i = 0; i < num_words; i++) + { + block[TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD + i].r32 = APE_PERI.BmcToNcReadBuffer.r32; + } + + block[TX_PORT_OUT_ALL_CONTROL_WORD].r32 = control.r32; + + length -= control.bits.payload_length; + + return control.bits.payload_length; +} + +void Network_TX_transmitPassthroughPacket(uint32_t length) +{ + if (!length) + { + return; + } + + // Drop the FCS word. It will be generated by hardware. + length -= 4; + + int32_t tail; + int32_t first = tail = Network_TX_allocateBlock(); + int32_t next_block = -1; + uint32_t blocks = Network_TX_numBlocksNeeded(length); + int total_blocks = blocks; + ; + + if (blocks > 1) + { + next_block = Network_TX_allocateBlock(); + } + RegTX_PORTOut_t *block = (RegTX_PORTOut_t *)&TX_PORT.Out[TX_PORT_OUT_ALL_BLOCK_WORDS * first]; + + length -= Network_TX_initFirstPassthroughBlock(block, length, blocks, next_block); + blocks -= 1; + while (blocks--) + { + + block = (RegTX_PORTOut_t *)&TX_PORT.Out[TX_PORT_OUT_ALL_BLOCK_WORDS * next_block]; + if (blocks) + { + next_block = Network_TX_allocateBlock(); + length -= Network_TX_initAdditionalPassthroughBlock( + block, next_block, length); + } + else + { + Network_TX_initAdditionalPassthroughBlock(block, 0, length); + } + + tail = next_block; + } + + RegAPETxToNetDoorbellFunc0_t doorbell; + doorbell.r32 = 0; + doorbell.bits.Head = first; + doorbell.bits.Tail = tail; + doorbell.bits.Length = total_blocks; + + APE.TxToNetDoorbellFunc0 = doorbell; + + // Read last RX word (FCS) to clear the buffer + uint32_t data = APE_PERI.BmcToNcReadBuffer.r32; + (void)data; +} diff --git a/libs/bcm5719/APE_sym.s b/libs/bcm5719/APE_sym.s index ecb5b80..075d3dd 100644 --- a/libs/bcm5719/APE_sym.s +++ b/libs/bcm5719/APE_sym.s @@ -90,7 +90,7 @@ .global RX_PORT .equ RX_PORT, 0xa0000000 -.size RX_PORT, 0x0 +.size RX_PORT, 0x4000 .global RX_PORT1 .equ RX_PORT1, 0xa0004000 diff --git a/libs/elfio/elf_examples/hello.c b/libs/elfio/elf_examples/hello.c index 65f198c..07dcbd7 100644 --- a/libs/elfio/elf_examples/hello.c +++ b/libs/elfio/elf_examples/hello.c @@ -2,7 +2,7 @@ int main() { - printf( "Hello\n" ); + printf("Hello\n"); return 0; } diff --git a/simulator/APE_DEVICE.cpp b/simulator/APE_DEVICE.cpp new file mode 100644 index 0000000..2eeaac9 --- /dev/null +++ b/simulator/APE_DEVICE.cpp @@ -0,0 +1,311 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_DEVICE.h> + +DEVICE_t DEVICE; + +void init_APE_DEVICE(void) +{ + /** @brief Component Registers for @ref DEVICE. */ + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousHostControl. */ + + /** @brief Bitmap for @ref DEVICE_t.PciState. */ + + /** @brief Bitmap for @ref DEVICE_t.RegisterBase. */ + + /** @brief Bitmap for @ref DEVICE_t.MemoryBase. */ + + /** @brief Bitmap for @ref DEVICE_t.RegisterData. */ + + /** @brief Bitmap for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndex. */ + + /** @brief Bitmap for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndexLow. */ + + /** @brief Bitmap for @ref DEVICE_t.LinkStatusControl. */ + + /** @brief Bitmap for @ref DEVICE_t.ApeMemoryBase. */ + + /** @brief Bitmap for @ref DEVICE_t.ApeMemoryData. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMode. */ + + /** @brief Bitmap for @ref DEVICE_t.LedControl. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses0High. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses0Low. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses1High. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses1Low. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses2High. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses2Low. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses3High. */ + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses3Low. */ + + /** @brief Bitmap for @ref DEVICE_t.WolPatternPointer. */ + + /** @brief Bitmap for @ref DEVICE_t.WolPatternCfg. */ + + /** @brief Bitmap for @ref DEVICE_t.MtuSize. */ + + /** @brief Bitmap for @ref DEVICE_t.MiiCommunication. */ + + /** @brief Bitmap for @ref DEVICE_t.MiiMode. */ + + /** @brief Bitmap for @ref DEVICE_t.TransmitMacMode. */ + + /** @brief Bitmap for @ref DEVICE_t.ReceiveMacMode. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch1High. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch1Low. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch2High. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch2Low. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch3High. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch3Low. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch4High. */ + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch4Low. */ + + /** @brief Bitmap for @ref DEVICE_t.SgmiiStatus. */ + + /** @brief Bitmap for @ref DEVICE_t.CpmuControl. */ + + /** @brief Bitmap for @ref DEVICE_t.LinkAwarePowerModeClockPolicy. */ + + /** @brief Bitmap for @ref DEVICE_t.ClockSpeedOverridePolicy. */ + + /** @brief Bitmap for @ref DEVICE_t.Status. */ + + /** @brief Bitmap for @ref DEVICE_t.ClockStatus. */ + + /** @brief Bitmap for @ref DEVICE_t.GphyControlStatus. */ + + /** @brief Bitmap for @ref DEVICE_t.ChipId. */ + + /** @brief Bitmap for @ref DEVICE_t.MutexRequest. */ + + /** @brief Bitmap for @ref DEVICE_t.MutexGrant. */ + + /** @brief Bitmap for @ref DEVICE_t.GphyStrap. */ + + /** @brief Bitmap for @ref DEVICE_t.TopLevelMiscellaneousControl1. */ + + /** @brief Bitmap for @ref DEVICE_t.EeeMode. */ + + /** @brief Bitmap for @ref DEVICE_t.EeeLinkIdleControl. */ + + /** @brief Bitmap for @ref DEVICE_t.EeeControl. */ + + /** @brief Bitmap for @ref DEVICE_t.GlobalMutexRequest. */ + + /** @brief Bitmap for @ref DEVICE_t.GlobalMutexGrant. */ + + /** @brief Bitmap for @ref DEVICE_t.MemoryArbiterMode. */ + + /** @brief Bitmap for @ref DEVICE_t.BufferManagerMode. */ + + /** @brief Bitmap for @ref DEVICE_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscMode. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscStatus. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscCurrentInstruction. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister1. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister2. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister3. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister4. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister5. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister6. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister7. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister8. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister9. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister10. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister11. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister12. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister13. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister14. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister15. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister16. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister17. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister18. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister19. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister20. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister21. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister22. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister23. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister24. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister25. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister26. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister27. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister28. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister29. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister30. */ + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister31. */ + + /** @brief Bitmap for @ref DEVICE_t.6408. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerConsumptionInfo. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerDissipatedInfo. */ + + /** @brief Bitmap for @ref DEVICE_t.PciVpdRequest. */ + + /** @brief Bitmap for @ref DEVICE_t.PciVpdResponse. */ + + /** @brief Bitmap for @ref DEVICE_t.PciVendorDeviceId. */ + + /** @brief Bitmap for @ref DEVICE_t.PciSubsystemId. */ + + /** @brief Bitmap for @ref DEVICE_t.PciClassCodeRevision. */ + + /** @brief Bitmap for @ref DEVICE_t.64c0. */ + + /** @brief Bitmap for @ref DEVICE_t.64c8. */ + + /** @brief Bitmap for @ref DEVICE_t.64dc. */ + + /** @brief Bitmap for @ref DEVICE_t.PciSerialNumberLow. */ + + /** @brief Bitmap for @ref DEVICE_t.PciSerialNumberHigh. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget0. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget1. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget2. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget3. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget4. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget5. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget6. */ + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget7. */ + + /** @brief Bitmap for @ref DEVICE_t.6530. */ + + /** @brief Bitmap for @ref DEVICE_t.6550. */ + + /** @brief Bitmap for @ref DEVICE_t.65f4. */ + + /** @brief Bitmap for @ref DEVICE_t.GrcModeControl. */ + + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousConfig. */ + + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousLocalControl. */ + + /** @brief Bitmap for @ref DEVICE_t.Timer. */ + + /** @brief Bitmap for @ref DEVICE_t.RxCpuEvent. */ + + /** @brief Bitmap for @ref DEVICE_t.6838. */ + + /** @brief Bitmap for @ref DEVICE_t.MdiControl. */ + + /** @brief Bitmap for @ref DEVICE_t.RxCpuEventEnable. */ + + /** @brief Bitmap for @ref DEVICE_t.FastBootProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE_t.ExpansionRomAddr. */ + + /** @brief Bitmap for @ref DEVICE_t.68f0. */ + + /** @brief Bitmap for @ref DEVICE_t.EavRefClockControl. */ + + /** @brief Bitmap for @ref DEVICE_t.7c04. */ + + +} diff --git a/simulator/APE_DEVICE1.cpp b/simulator/APE_DEVICE1.cpp new file mode 100644 index 0000000..6ec1cf3 --- /dev/null +++ b/simulator/APE_DEVICE1.cpp @@ -0,0 +1,311 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE1.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_DEVICE1.h> + +DEVICE_t DEVICE1; + +void init_APE_DEVICE1(void) +{ + /** @brief Component Registers for @ref DEVICE1. */ + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousHostControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciState. */ + + /** @brief Bitmap for @ref DEVICE1_t.RegisterBase. */ + + /** @brief Bitmap for @ref DEVICE1_t.MemoryBase. */ + + /** @brief Bitmap for @ref DEVICE1_t.RegisterData. */ + + /** @brief Bitmap for @ref DEVICE1_t.UndiReceiveReturnRingConsumerIndex. */ + + /** @brief Bitmap for @ref DEVICE1_t.UndiReceiveReturnRingConsumerIndexLow. */ + + /** @brief Bitmap for @ref DEVICE1_t.LinkStatusControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.ApeMemoryBase. */ + + /** @brief Bitmap for @ref DEVICE1_t.ApeMemoryData. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.LedControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses0High. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses0Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses1High. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses1Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses2High. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses2Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses3High. */ + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses3Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.WolPatternPointer. */ + + /** @brief Bitmap for @ref DEVICE1_t.WolPatternCfg. */ + + /** @brief Bitmap for @ref DEVICE1_t.MtuSize. */ + + /** @brief Bitmap for @ref DEVICE1_t.MiiCommunication. */ + + /** @brief Bitmap for @ref DEVICE1_t.MiiMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.TransmitMacMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.ReceiveMacMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch1High. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch1Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch2High. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch2Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch3High. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch3Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch4High. */ + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch4Low. */ + + /** @brief Bitmap for @ref DEVICE1_t.SgmiiStatus. */ + + /** @brief Bitmap for @ref DEVICE1_t.CpmuControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.LinkAwarePowerModeClockPolicy. */ + + /** @brief Bitmap for @ref DEVICE1_t.ClockSpeedOverridePolicy. */ + + /** @brief Bitmap for @ref DEVICE1_t.Status. */ + + /** @brief Bitmap for @ref DEVICE1_t.ClockStatus. */ + + /** @brief Bitmap for @ref DEVICE1_t.GphyControlStatus. */ + + /** @brief Bitmap for @ref DEVICE1_t.ChipId. */ + + /** @brief Bitmap for @ref DEVICE1_t.MutexRequest. */ + + /** @brief Bitmap for @ref DEVICE1_t.MutexGrant. */ + + /** @brief Bitmap for @ref DEVICE1_t.GphyStrap. */ + + /** @brief Bitmap for @ref DEVICE1_t.TopLevelMiscellaneousControl1. */ + + /** @brief Bitmap for @ref DEVICE1_t.EeeMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.EeeLinkIdleControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.EeeControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.GlobalMutexRequest. */ + + /** @brief Bitmap for @ref DEVICE1_t.GlobalMutexGrant. */ + + /** @brief Bitmap for @ref DEVICE1_t.MemoryArbiterMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.BufferManagerMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscMode. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscStatus. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscCurrentInstruction. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscHardwareBreakpoint. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister0. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister1. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister2. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister3. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister4. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister5. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister6. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister7. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister8. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister9. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister10. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister11. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister12. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister13. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister14. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister15. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister16. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister17. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister18. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister19. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister20. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister21. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister22. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister23. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister24. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister25. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister26. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister27. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister28. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister29. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister30. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister31. */ + + /** @brief Bitmap for @ref DEVICE1_t.6408. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerConsumptionInfo. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerDissipatedInfo. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciVpdRequest. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciVpdResponse. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciVendorDeviceId. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciSubsystemId. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciClassCodeRevision. */ + + /** @brief Bitmap for @ref DEVICE1_t.64c0. */ + + /** @brief Bitmap for @ref DEVICE1_t.64c8. */ + + /** @brief Bitmap for @ref DEVICE1_t.64dc. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciSerialNumberLow. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciSerialNumberHigh. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget0. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget1. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget2. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget3. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget4. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget5. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget6. */ + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget7. */ + + /** @brief Bitmap for @ref DEVICE1_t.6530. */ + + /** @brief Bitmap for @ref DEVICE1_t.6550. */ + + /** @brief Bitmap for @ref DEVICE1_t.65f4. */ + + /** @brief Bitmap for @ref DEVICE1_t.GrcModeControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousConfig. */ + + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousLocalControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.Timer. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxCpuEvent. */ + + /** @brief Bitmap for @ref DEVICE1_t.6838. */ + + /** @brief Bitmap for @ref DEVICE1_t.MdiControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.RxCpuEventEnable. */ + + /** @brief Bitmap for @ref DEVICE1_t.FastBootProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE1_t.ExpansionRomAddr. */ + + /** @brief Bitmap for @ref DEVICE1_t.68f0. */ + + /** @brief Bitmap for @ref DEVICE1_t.EavRefClockControl. */ + + /** @brief Bitmap for @ref DEVICE1_t.7c04. */ + + +} diff --git a/simulator/APE_DEVICE1_sim.cpp b/simulator/APE_DEVICE1_sim.cpp new file mode 100644 index 0000000..9c71f04 --- /dev/null +++ b/simulator/APE_DEVICE1_sim.cpp @@ -0,0 +1,608 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE1_sim.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE1_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_DEVICE1.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_DEVICE1_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0050000; + + DEVICE1.mIndexReadCallback = loader_read_mem; + DEVICE1.mIndexReadCallbackArgs = base; + + DEVICE1.mIndexWriteCallback = loader_write_mem; + DEVICE1.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref DEVICE1. */ + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousHostControl. */ + DEVICE1.MiscellaneousHostControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MiscellaneousHostControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciState. */ + DEVICE1.PciState.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciState.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RegisterBase. */ + DEVICE1.RegisterBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RegisterBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MemoryBase. */ + DEVICE1.MemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RegisterData. */ + DEVICE1.RegisterData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RegisterData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.UndiReceiveReturnRingConsumerIndex. */ + DEVICE1.UndiReceiveReturnRingConsumerIndex.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.UndiReceiveReturnRingConsumerIndex.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.UndiReceiveReturnRingConsumerIndexLow. */ + DEVICE1.UndiReceiveReturnRingConsumerIndexLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.UndiReceiveReturnRingConsumerIndexLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.LinkStatusControl. */ + DEVICE1.LinkStatusControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.LinkStatusControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ApeMemoryBase. */ + DEVICE1.ApeMemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ApeMemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ApeMemoryData. */ + DEVICE1.ApeMemoryData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ApeMemoryData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMode. */ + DEVICE1.EmacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.LedControl. */ + DEVICE1.LedControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.LedControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses0High. */ + DEVICE1.EmacMacAddresses0High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses0High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses0Low. */ + DEVICE1.EmacMacAddresses0Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses0Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses1High. */ + DEVICE1.EmacMacAddresses1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses1Low. */ + DEVICE1.EmacMacAddresses1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses2High. */ + DEVICE1.EmacMacAddresses2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses2Low. */ + DEVICE1.EmacMacAddresses2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses3High. */ + DEVICE1.EmacMacAddresses3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EmacMacAddresses3Low. */ + DEVICE1.EmacMacAddresses3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EmacMacAddresses3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.WolPatternPointer. */ + DEVICE1.WolPatternPointer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.WolPatternPointer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.WolPatternCfg. */ + DEVICE1.WolPatternCfg.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.WolPatternCfg.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MtuSize. */ + DEVICE1.MtuSize.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MtuSize.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MiiCommunication. */ + DEVICE1.MiiCommunication.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MiiCommunication.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MiiMode. */ + DEVICE1.MiiMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MiiMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.TransmitMacMode. */ + DEVICE1.TransmitMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.TransmitMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ReceiveMacMode. */ + DEVICE1.ReceiveMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ReceiveMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch1High. */ + DEVICE1.PerfectMatch1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch1Low. */ + DEVICE1.PerfectMatch1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch2High. */ + DEVICE1.PerfectMatch2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch2Low. */ + DEVICE1.PerfectMatch2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch3High. */ + DEVICE1.PerfectMatch3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch3Low. */ + DEVICE1.PerfectMatch3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch4High. */ + DEVICE1.PerfectMatch4High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch4High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PerfectMatch4Low. */ + DEVICE1.PerfectMatch4Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PerfectMatch4Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.SgmiiStatus. */ + DEVICE1.SgmiiStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.SgmiiStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.CpmuControl. */ + DEVICE1.CpmuControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.CpmuControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.LinkAwarePowerModeClockPolicy. */ + DEVICE1.LinkAwarePowerModeClockPolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.LinkAwarePowerModeClockPolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ClockSpeedOverridePolicy. */ + DEVICE1.ClockSpeedOverridePolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ClockSpeedOverridePolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.Status. */ + DEVICE1.Status.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.Status.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ClockStatus. */ + DEVICE1.ClockStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ClockStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.GphyControlStatus. */ + DEVICE1.GphyControlStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.GphyControlStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ChipId. */ + DEVICE1.ChipId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ChipId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MutexRequest. */ + DEVICE1.MutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MutexGrant. */ + DEVICE1.MutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.GphyStrap. */ + DEVICE1.GphyStrap.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.GphyStrap.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.TopLevelMiscellaneousControl1. */ + DEVICE1.TopLevelMiscellaneousControl1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.TopLevelMiscellaneousControl1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EeeMode. */ + DEVICE1.EeeMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EeeMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EeeLinkIdleControl. */ + DEVICE1.EeeLinkIdleControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EeeLinkIdleControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EeeControl. */ + DEVICE1.EeeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EeeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.GlobalMutexRequest. */ + DEVICE1.GlobalMutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.GlobalMutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.GlobalMutexGrant. */ + DEVICE1.GlobalMutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.GlobalMutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MemoryArbiterMode. */ + DEVICE1.MemoryArbiterMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MemoryArbiterMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.BufferManagerMode. */ + DEVICE1.BufferManagerMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.BufferManagerMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + DEVICE1.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscMode. */ + DEVICE1.RxRiscMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscStatus. */ + DEVICE1.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscProgramCounter. */ + DEVICE1.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscCurrentInstruction. */ + DEVICE1.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscHardwareBreakpoint. */ + DEVICE1.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister0. */ + DEVICE1.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister1. */ + DEVICE1.RxRiscRegister1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister2. */ + DEVICE1.RxRiscRegister2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister3. */ + DEVICE1.RxRiscRegister3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister4. */ + DEVICE1.RxRiscRegister4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister5. */ + DEVICE1.RxRiscRegister5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister6. */ + DEVICE1.RxRiscRegister6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister7. */ + DEVICE1.RxRiscRegister7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister8. */ + DEVICE1.RxRiscRegister8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister9. */ + DEVICE1.RxRiscRegister9.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister9.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister10. */ + DEVICE1.RxRiscRegister10.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister10.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister11. */ + DEVICE1.RxRiscRegister11.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister11.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister12. */ + DEVICE1.RxRiscRegister12.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister12.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister13. */ + DEVICE1.RxRiscRegister13.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister13.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister14. */ + DEVICE1.RxRiscRegister14.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister14.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister15. */ + DEVICE1.RxRiscRegister15.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister15.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister16. */ + DEVICE1.RxRiscRegister16.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister16.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister17. */ + DEVICE1.RxRiscRegister17.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister17.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister18. */ + DEVICE1.RxRiscRegister18.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister18.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister19. */ + DEVICE1.RxRiscRegister19.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister19.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister20. */ + DEVICE1.RxRiscRegister20.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister20.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister21. */ + DEVICE1.RxRiscRegister21.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister21.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister22. */ + DEVICE1.RxRiscRegister22.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister22.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister23. */ + DEVICE1.RxRiscRegister23.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister23.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister24. */ + DEVICE1.RxRiscRegister24.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister24.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister25. */ + DEVICE1.RxRiscRegister25.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister25.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister26. */ + DEVICE1.RxRiscRegister26.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister26.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister27. */ + DEVICE1.RxRiscRegister27.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister27.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister28. */ + DEVICE1.RxRiscRegister28.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister28.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister29. */ + DEVICE1.RxRiscRegister29.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister29.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister30. */ + DEVICE1.RxRiscRegister30.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister30.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxRiscRegister31. */ + DEVICE1.RxRiscRegister31.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxRiscRegister31.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.6408. */ + DEVICE1._6408.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._6408.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerConsumptionInfo. */ + DEVICE1.PciPowerConsumptionInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerConsumptionInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerDissipatedInfo. */ + DEVICE1.PciPowerDissipatedInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerDissipatedInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciVpdRequest. */ + DEVICE1.PciVpdRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciVpdRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciVpdResponse. */ + DEVICE1.PciVpdResponse.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciVpdResponse.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciVendorDeviceId. */ + DEVICE1.PciVendorDeviceId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciVendorDeviceId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciSubsystemId. */ + DEVICE1.PciSubsystemId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciSubsystemId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciClassCodeRevision. */ + DEVICE1.PciClassCodeRevision.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciClassCodeRevision.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.64c0. */ + DEVICE1._64c0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._64c0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.64c8. */ + DEVICE1._64c8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._64c8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.64dc. */ + DEVICE1._64dc.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._64dc.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciSerialNumberLow. */ + DEVICE1.PciSerialNumberLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciSerialNumberLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciSerialNumberHigh. */ + DEVICE1.PciSerialNumberHigh.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciSerialNumberHigh.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget0. */ + DEVICE1.PciPowerBudget0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget1. */ + DEVICE1.PciPowerBudget1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget2. */ + DEVICE1.PciPowerBudget2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget3. */ + DEVICE1.PciPowerBudget3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget4. */ + DEVICE1.PciPowerBudget4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget5. */ + DEVICE1.PciPowerBudget5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget6. */ + DEVICE1.PciPowerBudget6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.PciPowerBudget7. */ + DEVICE1.PciPowerBudget7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.PciPowerBudget7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.6530. */ + DEVICE1._6530.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._6530.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.6550. */ + DEVICE1._6550.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._6550.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.65f4. */ + DEVICE1._65f4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._65f4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.GrcModeControl. */ + DEVICE1.GrcModeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.GrcModeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousConfig. */ + DEVICE1.MiscellaneousConfig.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MiscellaneousConfig.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MiscellaneousLocalControl. */ + DEVICE1.MiscellaneousLocalControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MiscellaneousLocalControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.Timer. */ + DEVICE1.Timer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.Timer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxCpuEvent. */ + DEVICE1.RxCpuEvent.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxCpuEvent.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.6838. */ + DEVICE1._6838.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._6838.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.MdiControl. */ + DEVICE1.MdiControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.MdiControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.RxCpuEventEnable. */ + DEVICE1.RxCpuEventEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.RxCpuEventEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.FastBootProgramCounter. */ + DEVICE1.FastBootProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.FastBootProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.ExpansionRomAddr. */ + DEVICE1.ExpansionRomAddr.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.ExpansionRomAddr.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.68f0. */ + DEVICE1._68f0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._68f0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.EavRefClockControl. */ + DEVICE1.EavRefClockControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1.EavRefClockControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE1_t.7c04. */ + DEVICE1._7c04.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE1._7c04.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + +} diff --git a/simulator/APE_DEVICE2.cpp b/simulator/APE_DEVICE2.cpp new file mode 100644 index 0000000..856cc11 --- /dev/null +++ b/simulator/APE_DEVICE2.cpp @@ -0,0 +1,311 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE2.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_DEVICE2.h> + +DEVICE_t DEVICE2; + +void init_APE_DEVICE2(void) +{ + /** @brief Component Registers for @ref DEVICE2. */ + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousHostControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciState. */ + + /** @brief Bitmap for @ref DEVICE2_t.RegisterBase. */ + + /** @brief Bitmap for @ref DEVICE2_t.MemoryBase. */ + + /** @brief Bitmap for @ref DEVICE2_t.RegisterData. */ + + /** @brief Bitmap for @ref DEVICE2_t.UndiReceiveReturnRingConsumerIndex. */ + + /** @brief Bitmap for @ref DEVICE2_t.UndiReceiveReturnRingConsumerIndexLow. */ + + /** @brief Bitmap for @ref DEVICE2_t.LinkStatusControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.ApeMemoryBase. */ + + /** @brief Bitmap for @ref DEVICE2_t.ApeMemoryData. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.LedControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses0High. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses0Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses1High. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses1Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses2High. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses2Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses3High. */ + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses3Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.WolPatternPointer. */ + + /** @brief Bitmap for @ref DEVICE2_t.WolPatternCfg. */ + + /** @brief Bitmap for @ref DEVICE2_t.MtuSize. */ + + /** @brief Bitmap for @ref DEVICE2_t.MiiCommunication. */ + + /** @brief Bitmap for @ref DEVICE2_t.MiiMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.TransmitMacMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.ReceiveMacMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch1High. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch1Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch2High. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch2Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch3High. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch3Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch4High. */ + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch4Low. */ + + /** @brief Bitmap for @ref DEVICE2_t.SgmiiStatus. */ + + /** @brief Bitmap for @ref DEVICE2_t.CpmuControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.LinkAwarePowerModeClockPolicy. */ + + /** @brief Bitmap for @ref DEVICE2_t.ClockSpeedOverridePolicy. */ + + /** @brief Bitmap for @ref DEVICE2_t.Status. */ + + /** @brief Bitmap for @ref DEVICE2_t.ClockStatus. */ + + /** @brief Bitmap for @ref DEVICE2_t.GphyControlStatus. */ + + /** @brief Bitmap for @ref DEVICE2_t.ChipId. */ + + /** @brief Bitmap for @ref DEVICE2_t.MutexRequest. */ + + /** @brief Bitmap for @ref DEVICE2_t.MutexGrant. */ + + /** @brief Bitmap for @ref DEVICE2_t.GphyStrap. */ + + /** @brief Bitmap for @ref DEVICE2_t.TopLevelMiscellaneousControl1. */ + + /** @brief Bitmap for @ref DEVICE2_t.EeeMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.EeeLinkIdleControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.EeeControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.GlobalMutexRequest. */ + + /** @brief Bitmap for @ref DEVICE2_t.GlobalMutexGrant. */ + + /** @brief Bitmap for @ref DEVICE2_t.MemoryArbiterMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.BufferManagerMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscMode. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscStatus. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscCurrentInstruction. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscHardwareBreakpoint. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister0. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister1. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister2. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister3. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister4. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister5. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister6. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister7. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister8. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister9. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister10. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister11. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister12. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister13. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister14. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister15. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister16. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister17. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister18. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister19. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister20. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister21. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister22. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister23. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister24. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister25. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister26. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister27. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister28. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister29. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister30. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister31. */ + + /** @brief Bitmap for @ref DEVICE2_t.6408. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerConsumptionInfo. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerDissipatedInfo. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciVpdRequest. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciVpdResponse. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciVendorDeviceId. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciSubsystemId. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciClassCodeRevision. */ + + /** @brief Bitmap for @ref DEVICE2_t.64c0. */ + + /** @brief Bitmap for @ref DEVICE2_t.64c8. */ + + /** @brief Bitmap for @ref DEVICE2_t.64dc. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciSerialNumberLow. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciSerialNumberHigh. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget0. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget1. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget2. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget3. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget4. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget5. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget6. */ + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget7. */ + + /** @brief Bitmap for @ref DEVICE2_t.6530. */ + + /** @brief Bitmap for @ref DEVICE2_t.6550. */ + + /** @brief Bitmap for @ref DEVICE2_t.65f4. */ + + /** @brief Bitmap for @ref DEVICE2_t.GrcModeControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousConfig. */ + + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousLocalControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.Timer. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxCpuEvent. */ + + /** @brief Bitmap for @ref DEVICE2_t.6838. */ + + /** @brief Bitmap for @ref DEVICE2_t.MdiControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.RxCpuEventEnable. */ + + /** @brief Bitmap for @ref DEVICE2_t.FastBootProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE2_t.ExpansionRomAddr. */ + + /** @brief Bitmap for @ref DEVICE2_t.68f0. */ + + /** @brief Bitmap for @ref DEVICE2_t.EavRefClockControl. */ + + /** @brief Bitmap for @ref DEVICE2_t.7c04. */ + + +} diff --git a/simulator/APE_DEVICE2_sim.cpp b/simulator/APE_DEVICE2_sim.cpp new file mode 100644 index 0000000..6326730 --- /dev/null +++ b/simulator/APE_DEVICE2_sim.cpp @@ -0,0 +1,608 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE2_sim.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE2_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_DEVICE2.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_DEVICE2_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0060000; + + DEVICE2.mIndexReadCallback = loader_read_mem; + DEVICE2.mIndexReadCallbackArgs = base; + + DEVICE2.mIndexWriteCallback = loader_write_mem; + DEVICE2.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref DEVICE2. */ + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousHostControl. */ + DEVICE2.MiscellaneousHostControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MiscellaneousHostControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciState. */ + DEVICE2.PciState.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciState.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RegisterBase. */ + DEVICE2.RegisterBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RegisterBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MemoryBase. */ + DEVICE2.MemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RegisterData. */ + DEVICE2.RegisterData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RegisterData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.UndiReceiveReturnRingConsumerIndex. */ + DEVICE2.UndiReceiveReturnRingConsumerIndex.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.UndiReceiveReturnRingConsumerIndex.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.UndiReceiveReturnRingConsumerIndexLow. */ + DEVICE2.UndiReceiveReturnRingConsumerIndexLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.UndiReceiveReturnRingConsumerIndexLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.LinkStatusControl. */ + DEVICE2.LinkStatusControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.LinkStatusControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ApeMemoryBase. */ + DEVICE2.ApeMemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ApeMemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ApeMemoryData. */ + DEVICE2.ApeMemoryData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ApeMemoryData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMode. */ + DEVICE2.EmacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.LedControl. */ + DEVICE2.LedControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.LedControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses0High. */ + DEVICE2.EmacMacAddresses0High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses0High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses0Low. */ + DEVICE2.EmacMacAddresses0Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses0Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses1High. */ + DEVICE2.EmacMacAddresses1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses1Low. */ + DEVICE2.EmacMacAddresses1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses2High. */ + DEVICE2.EmacMacAddresses2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses2Low. */ + DEVICE2.EmacMacAddresses2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses3High. */ + DEVICE2.EmacMacAddresses3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EmacMacAddresses3Low. */ + DEVICE2.EmacMacAddresses3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EmacMacAddresses3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.WolPatternPointer. */ + DEVICE2.WolPatternPointer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.WolPatternPointer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.WolPatternCfg. */ + DEVICE2.WolPatternCfg.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.WolPatternCfg.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MtuSize. */ + DEVICE2.MtuSize.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MtuSize.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MiiCommunication. */ + DEVICE2.MiiCommunication.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MiiCommunication.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MiiMode. */ + DEVICE2.MiiMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MiiMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.TransmitMacMode. */ + DEVICE2.TransmitMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.TransmitMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ReceiveMacMode. */ + DEVICE2.ReceiveMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ReceiveMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch1High. */ + DEVICE2.PerfectMatch1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch1Low. */ + DEVICE2.PerfectMatch1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch2High. */ + DEVICE2.PerfectMatch2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch2Low. */ + DEVICE2.PerfectMatch2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch3High. */ + DEVICE2.PerfectMatch3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch3Low. */ + DEVICE2.PerfectMatch3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch4High. */ + DEVICE2.PerfectMatch4High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch4High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PerfectMatch4Low. */ + DEVICE2.PerfectMatch4Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PerfectMatch4Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.SgmiiStatus. */ + DEVICE2.SgmiiStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.SgmiiStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.CpmuControl. */ + DEVICE2.CpmuControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.CpmuControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.LinkAwarePowerModeClockPolicy. */ + DEVICE2.LinkAwarePowerModeClockPolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.LinkAwarePowerModeClockPolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ClockSpeedOverridePolicy. */ + DEVICE2.ClockSpeedOverridePolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ClockSpeedOverridePolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.Status. */ + DEVICE2.Status.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.Status.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ClockStatus. */ + DEVICE2.ClockStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ClockStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.GphyControlStatus. */ + DEVICE2.GphyControlStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.GphyControlStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ChipId. */ + DEVICE2.ChipId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ChipId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MutexRequest. */ + DEVICE2.MutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MutexGrant. */ + DEVICE2.MutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.GphyStrap. */ + DEVICE2.GphyStrap.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.GphyStrap.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.TopLevelMiscellaneousControl1. */ + DEVICE2.TopLevelMiscellaneousControl1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.TopLevelMiscellaneousControl1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EeeMode. */ + DEVICE2.EeeMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EeeMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EeeLinkIdleControl. */ + DEVICE2.EeeLinkIdleControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EeeLinkIdleControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EeeControl. */ + DEVICE2.EeeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EeeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.GlobalMutexRequest. */ + DEVICE2.GlobalMutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.GlobalMutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.GlobalMutexGrant. */ + DEVICE2.GlobalMutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.GlobalMutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MemoryArbiterMode. */ + DEVICE2.MemoryArbiterMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MemoryArbiterMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.BufferManagerMode. */ + DEVICE2.BufferManagerMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.BufferManagerMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + DEVICE2.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscMode. */ + DEVICE2.RxRiscMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscStatus. */ + DEVICE2.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscProgramCounter. */ + DEVICE2.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscCurrentInstruction. */ + DEVICE2.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscHardwareBreakpoint. */ + DEVICE2.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister0. */ + DEVICE2.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister1. */ + DEVICE2.RxRiscRegister1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister2. */ + DEVICE2.RxRiscRegister2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister3. */ + DEVICE2.RxRiscRegister3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister4. */ + DEVICE2.RxRiscRegister4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister5. */ + DEVICE2.RxRiscRegister5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister6. */ + DEVICE2.RxRiscRegister6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister7. */ + DEVICE2.RxRiscRegister7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister8. */ + DEVICE2.RxRiscRegister8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister9. */ + DEVICE2.RxRiscRegister9.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister9.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister10. */ + DEVICE2.RxRiscRegister10.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister10.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister11. */ + DEVICE2.RxRiscRegister11.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister11.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister12. */ + DEVICE2.RxRiscRegister12.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister12.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister13. */ + DEVICE2.RxRiscRegister13.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister13.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister14. */ + DEVICE2.RxRiscRegister14.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister14.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister15. */ + DEVICE2.RxRiscRegister15.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister15.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister16. */ + DEVICE2.RxRiscRegister16.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister16.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister17. */ + DEVICE2.RxRiscRegister17.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister17.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister18. */ + DEVICE2.RxRiscRegister18.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister18.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister19. */ + DEVICE2.RxRiscRegister19.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister19.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister20. */ + DEVICE2.RxRiscRegister20.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister20.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister21. */ + DEVICE2.RxRiscRegister21.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister21.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister22. */ + DEVICE2.RxRiscRegister22.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister22.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister23. */ + DEVICE2.RxRiscRegister23.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister23.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister24. */ + DEVICE2.RxRiscRegister24.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister24.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister25. */ + DEVICE2.RxRiscRegister25.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister25.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister26. */ + DEVICE2.RxRiscRegister26.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister26.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister27. */ + DEVICE2.RxRiscRegister27.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister27.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister28. */ + DEVICE2.RxRiscRegister28.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister28.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister29. */ + DEVICE2.RxRiscRegister29.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister29.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister30. */ + DEVICE2.RxRiscRegister30.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister30.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxRiscRegister31. */ + DEVICE2.RxRiscRegister31.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxRiscRegister31.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.6408. */ + DEVICE2._6408.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._6408.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerConsumptionInfo. */ + DEVICE2.PciPowerConsumptionInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerConsumptionInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerDissipatedInfo. */ + DEVICE2.PciPowerDissipatedInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerDissipatedInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciVpdRequest. */ + DEVICE2.PciVpdRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciVpdRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciVpdResponse. */ + DEVICE2.PciVpdResponse.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciVpdResponse.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciVendorDeviceId. */ + DEVICE2.PciVendorDeviceId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciVendorDeviceId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciSubsystemId. */ + DEVICE2.PciSubsystemId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciSubsystemId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciClassCodeRevision. */ + DEVICE2.PciClassCodeRevision.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciClassCodeRevision.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.64c0. */ + DEVICE2._64c0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._64c0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.64c8. */ + DEVICE2._64c8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._64c8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.64dc. */ + DEVICE2._64dc.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._64dc.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciSerialNumberLow. */ + DEVICE2.PciSerialNumberLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciSerialNumberLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciSerialNumberHigh. */ + DEVICE2.PciSerialNumberHigh.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciSerialNumberHigh.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget0. */ + DEVICE2.PciPowerBudget0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget1. */ + DEVICE2.PciPowerBudget1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget2. */ + DEVICE2.PciPowerBudget2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget3. */ + DEVICE2.PciPowerBudget3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget4. */ + DEVICE2.PciPowerBudget4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget5. */ + DEVICE2.PciPowerBudget5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget6. */ + DEVICE2.PciPowerBudget6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.PciPowerBudget7. */ + DEVICE2.PciPowerBudget7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.PciPowerBudget7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.6530. */ + DEVICE2._6530.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._6530.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.6550. */ + DEVICE2._6550.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._6550.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.65f4. */ + DEVICE2._65f4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._65f4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.GrcModeControl. */ + DEVICE2.GrcModeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.GrcModeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousConfig. */ + DEVICE2.MiscellaneousConfig.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MiscellaneousConfig.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MiscellaneousLocalControl. */ + DEVICE2.MiscellaneousLocalControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MiscellaneousLocalControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.Timer. */ + DEVICE2.Timer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.Timer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxCpuEvent. */ + DEVICE2.RxCpuEvent.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxCpuEvent.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.6838. */ + DEVICE2._6838.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._6838.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.MdiControl. */ + DEVICE2.MdiControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.MdiControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.RxCpuEventEnable. */ + DEVICE2.RxCpuEventEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.RxCpuEventEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.FastBootProgramCounter. */ + DEVICE2.FastBootProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.FastBootProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.ExpansionRomAddr. */ + DEVICE2.ExpansionRomAddr.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.ExpansionRomAddr.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.68f0. */ + DEVICE2._68f0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._68f0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.EavRefClockControl. */ + DEVICE2.EavRefClockControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2.EavRefClockControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE2_t.7c04. */ + DEVICE2._7c04.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE2._7c04.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + +} diff --git a/simulator/APE_DEVICE3.cpp b/simulator/APE_DEVICE3.cpp new file mode 100644 index 0000000..f33aacd --- /dev/null +++ b/simulator/APE_DEVICE3.cpp @@ -0,0 +1,311 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE3.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_DEVICE3.h> + +DEVICE_t DEVICE3; + +void init_APE_DEVICE3(void) +{ + /** @brief Component Registers for @ref DEVICE3. */ + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousHostControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciState. */ + + /** @brief Bitmap for @ref DEVICE3_t.RegisterBase. */ + + /** @brief Bitmap for @ref DEVICE3_t.MemoryBase. */ + + /** @brief Bitmap for @ref DEVICE3_t.RegisterData. */ + + /** @brief Bitmap for @ref DEVICE3_t.UndiReceiveReturnRingConsumerIndex. */ + + /** @brief Bitmap for @ref DEVICE3_t.UndiReceiveReturnRingConsumerIndexLow. */ + + /** @brief Bitmap for @ref DEVICE3_t.LinkStatusControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.ApeMemoryBase. */ + + /** @brief Bitmap for @ref DEVICE3_t.ApeMemoryData. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.LedControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses0High. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses0Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses1High. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses1Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses2High. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses2Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses3High. */ + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses3Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.WolPatternPointer. */ + + /** @brief Bitmap for @ref DEVICE3_t.WolPatternCfg. */ + + /** @brief Bitmap for @ref DEVICE3_t.MtuSize. */ + + /** @brief Bitmap for @ref DEVICE3_t.MiiCommunication. */ + + /** @brief Bitmap for @ref DEVICE3_t.MiiMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.TransmitMacMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.ReceiveMacMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch1High. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch1Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch2High. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch2Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch3High. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch3Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch4High. */ + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch4Low. */ + + /** @brief Bitmap for @ref DEVICE3_t.SgmiiStatus. */ + + /** @brief Bitmap for @ref DEVICE3_t.CpmuControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.LinkAwarePowerModeClockPolicy. */ + + /** @brief Bitmap for @ref DEVICE3_t.ClockSpeedOverridePolicy. */ + + /** @brief Bitmap for @ref DEVICE3_t.Status. */ + + /** @brief Bitmap for @ref DEVICE3_t.ClockStatus. */ + + /** @brief Bitmap for @ref DEVICE3_t.GphyControlStatus. */ + + /** @brief Bitmap for @ref DEVICE3_t.ChipId. */ + + /** @brief Bitmap for @ref DEVICE3_t.MutexRequest. */ + + /** @brief Bitmap for @ref DEVICE3_t.MutexGrant. */ + + /** @brief Bitmap for @ref DEVICE3_t.GphyStrap. */ + + /** @brief Bitmap for @ref DEVICE3_t.TopLevelMiscellaneousControl1. */ + + /** @brief Bitmap for @ref DEVICE3_t.EeeMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.EeeLinkIdleControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.EeeControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.GlobalMutexRequest. */ + + /** @brief Bitmap for @ref DEVICE3_t.GlobalMutexGrant. */ + + /** @brief Bitmap for @ref DEVICE3_t.MemoryArbiterMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.BufferManagerMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscMode. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscStatus. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscCurrentInstruction. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscHardwareBreakpoint. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister0. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister1. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister2. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister3. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister4. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister5. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister6. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister7. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister8. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister9. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister10. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister11. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister12. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister13. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister14. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister15. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister16. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister17. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister18. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister19. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister20. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister21. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister22. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister23. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister24. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister25. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister26. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister27. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister28. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister29. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister30. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister31. */ + + /** @brief Bitmap for @ref DEVICE3_t.6408. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerConsumptionInfo. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerDissipatedInfo. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciVpdRequest. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciVpdResponse. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciVendorDeviceId. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciSubsystemId. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciClassCodeRevision. */ + + /** @brief Bitmap for @ref DEVICE3_t.64c0. */ + + /** @brief Bitmap for @ref DEVICE3_t.64c8. */ + + /** @brief Bitmap for @ref DEVICE3_t.64dc. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciSerialNumberLow. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciSerialNumberHigh. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget0. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget1. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget2. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget3. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget4. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget5. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget6. */ + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget7. */ + + /** @brief Bitmap for @ref DEVICE3_t.6530. */ + + /** @brief Bitmap for @ref DEVICE3_t.6550. */ + + /** @brief Bitmap for @ref DEVICE3_t.65f4. */ + + /** @brief Bitmap for @ref DEVICE3_t.GrcModeControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousConfig. */ + + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousLocalControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.Timer. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxCpuEvent. */ + + /** @brief Bitmap for @ref DEVICE3_t.6838. */ + + /** @brief Bitmap for @ref DEVICE3_t.MdiControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.RxCpuEventEnable. */ + + /** @brief Bitmap for @ref DEVICE3_t.FastBootProgramCounter. */ + + /** @brief Bitmap for @ref DEVICE3_t.ExpansionRomAddr. */ + + /** @brief Bitmap for @ref DEVICE3_t.68f0. */ + + /** @brief Bitmap for @ref DEVICE3_t.EavRefClockControl. */ + + /** @brief Bitmap for @ref DEVICE3_t.7c04. */ + + +} diff --git a/simulator/APE_DEVICE3_sim.cpp b/simulator/APE_DEVICE3_sim.cpp new file mode 100644 index 0000000..b43bef9 --- /dev/null +++ b/simulator/APE_DEVICE3_sim.cpp @@ -0,0 +1,608 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE3_sim.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE3_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_DEVICE3.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_DEVICE3_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0070000; + + DEVICE3.mIndexReadCallback = loader_read_mem; + DEVICE3.mIndexReadCallbackArgs = base; + + DEVICE3.mIndexWriteCallback = loader_write_mem; + DEVICE3.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref DEVICE3. */ + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousHostControl. */ + DEVICE3.MiscellaneousHostControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MiscellaneousHostControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciState. */ + DEVICE3.PciState.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciState.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RegisterBase. */ + DEVICE3.RegisterBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RegisterBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MemoryBase. */ + DEVICE3.MemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RegisterData. */ + DEVICE3.RegisterData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RegisterData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.UndiReceiveReturnRingConsumerIndex. */ + DEVICE3.UndiReceiveReturnRingConsumerIndex.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.UndiReceiveReturnRingConsumerIndex.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.UndiReceiveReturnRingConsumerIndexLow. */ + DEVICE3.UndiReceiveReturnRingConsumerIndexLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.UndiReceiveReturnRingConsumerIndexLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.LinkStatusControl. */ + DEVICE3.LinkStatusControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.LinkStatusControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ApeMemoryBase. */ + DEVICE3.ApeMemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ApeMemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ApeMemoryData. */ + DEVICE3.ApeMemoryData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ApeMemoryData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMode. */ + DEVICE3.EmacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.LedControl. */ + DEVICE3.LedControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.LedControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses0High. */ + DEVICE3.EmacMacAddresses0High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses0High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses0Low. */ + DEVICE3.EmacMacAddresses0Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses0Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses1High. */ + DEVICE3.EmacMacAddresses1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses1Low. */ + DEVICE3.EmacMacAddresses1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses2High. */ + DEVICE3.EmacMacAddresses2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses2Low. */ + DEVICE3.EmacMacAddresses2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses3High. */ + DEVICE3.EmacMacAddresses3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EmacMacAddresses3Low. */ + DEVICE3.EmacMacAddresses3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EmacMacAddresses3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.WolPatternPointer. */ + DEVICE3.WolPatternPointer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.WolPatternPointer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.WolPatternCfg. */ + DEVICE3.WolPatternCfg.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.WolPatternCfg.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MtuSize. */ + DEVICE3.MtuSize.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MtuSize.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MiiCommunication. */ + DEVICE3.MiiCommunication.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MiiCommunication.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MiiMode. */ + DEVICE3.MiiMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MiiMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.TransmitMacMode. */ + DEVICE3.TransmitMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.TransmitMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ReceiveMacMode. */ + DEVICE3.ReceiveMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ReceiveMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch1High. */ + DEVICE3.PerfectMatch1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch1Low. */ + DEVICE3.PerfectMatch1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch2High. */ + DEVICE3.PerfectMatch2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch2Low. */ + DEVICE3.PerfectMatch2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch3High. */ + DEVICE3.PerfectMatch3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch3Low. */ + DEVICE3.PerfectMatch3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch4High. */ + DEVICE3.PerfectMatch4High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch4High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PerfectMatch4Low. */ + DEVICE3.PerfectMatch4Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PerfectMatch4Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.SgmiiStatus. */ + DEVICE3.SgmiiStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.SgmiiStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.CpmuControl. */ + DEVICE3.CpmuControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.CpmuControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.LinkAwarePowerModeClockPolicy. */ + DEVICE3.LinkAwarePowerModeClockPolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.LinkAwarePowerModeClockPolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ClockSpeedOverridePolicy. */ + DEVICE3.ClockSpeedOverridePolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ClockSpeedOverridePolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.Status. */ + DEVICE3.Status.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.Status.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ClockStatus. */ + DEVICE3.ClockStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ClockStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.GphyControlStatus. */ + DEVICE3.GphyControlStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.GphyControlStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ChipId. */ + DEVICE3.ChipId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ChipId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MutexRequest. */ + DEVICE3.MutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MutexGrant. */ + DEVICE3.MutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.GphyStrap. */ + DEVICE3.GphyStrap.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.GphyStrap.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.TopLevelMiscellaneousControl1. */ + DEVICE3.TopLevelMiscellaneousControl1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.TopLevelMiscellaneousControl1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EeeMode. */ + DEVICE3.EeeMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EeeMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EeeLinkIdleControl. */ + DEVICE3.EeeLinkIdleControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EeeLinkIdleControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EeeControl. */ + DEVICE3.EeeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EeeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.GlobalMutexRequest. */ + DEVICE3.GlobalMutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.GlobalMutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.GlobalMutexGrant. */ + DEVICE3.GlobalMutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.GlobalMutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MemoryArbiterMode. */ + DEVICE3.MemoryArbiterMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MemoryArbiterMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.BufferManagerMode. */ + DEVICE3.BufferManagerMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.BufferManagerMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + DEVICE3.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscMode. */ + DEVICE3.RxRiscMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscStatus. */ + DEVICE3.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscProgramCounter. */ + DEVICE3.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscCurrentInstruction. */ + DEVICE3.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscHardwareBreakpoint. */ + DEVICE3.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister0. */ + DEVICE3.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister1. */ + DEVICE3.RxRiscRegister1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister2. */ + DEVICE3.RxRiscRegister2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister3. */ + DEVICE3.RxRiscRegister3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister4. */ + DEVICE3.RxRiscRegister4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister5. */ + DEVICE3.RxRiscRegister5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister6. */ + DEVICE3.RxRiscRegister6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister7. */ + DEVICE3.RxRiscRegister7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister8. */ + DEVICE3.RxRiscRegister8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister9. */ + DEVICE3.RxRiscRegister9.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister9.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister10. */ + DEVICE3.RxRiscRegister10.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister10.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister11. */ + DEVICE3.RxRiscRegister11.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister11.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister12. */ + DEVICE3.RxRiscRegister12.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister12.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister13. */ + DEVICE3.RxRiscRegister13.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister13.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister14. */ + DEVICE3.RxRiscRegister14.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister14.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister15. */ + DEVICE3.RxRiscRegister15.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister15.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister16. */ + DEVICE3.RxRiscRegister16.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister16.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister17. */ + DEVICE3.RxRiscRegister17.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister17.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister18. */ + DEVICE3.RxRiscRegister18.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister18.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister19. */ + DEVICE3.RxRiscRegister19.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister19.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister20. */ + DEVICE3.RxRiscRegister20.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister20.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister21. */ + DEVICE3.RxRiscRegister21.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister21.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister22. */ + DEVICE3.RxRiscRegister22.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister22.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister23. */ + DEVICE3.RxRiscRegister23.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister23.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister24. */ + DEVICE3.RxRiscRegister24.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister24.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister25. */ + DEVICE3.RxRiscRegister25.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister25.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister26. */ + DEVICE3.RxRiscRegister26.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister26.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister27. */ + DEVICE3.RxRiscRegister27.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister27.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister28. */ + DEVICE3.RxRiscRegister28.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister28.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister29. */ + DEVICE3.RxRiscRegister29.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister29.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister30. */ + DEVICE3.RxRiscRegister30.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister30.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxRiscRegister31. */ + DEVICE3.RxRiscRegister31.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxRiscRegister31.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.6408. */ + DEVICE3._6408.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._6408.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerConsumptionInfo. */ + DEVICE3.PciPowerConsumptionInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerConsumptionInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerDissipatedInfo. */ + DEVICE3.PciPowerDissipatedInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerDissipatedInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciVpdRequest. */ + DEVICE3.PciVpdRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciVpdRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciVpdResponse. */ + DEVICE3.PciVpdResponse.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciVpdResponse.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciVendorDeviceId. */ + DEVICE3.PciVendorDeviceId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciVendorDeviceId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciSubsystemId. */ + DEVICE3.PciSubsystemId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciSubsystemId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciClassCodeRevision. */ + DEVICE3.PciClassCodeRevision.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciClassCodeRevision.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.64c0. */ + DEVICE3._64c0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._64c0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.64c8. */ + DEVICE3._64c8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._64c8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.64dc. */ + DEVICE3._64dc.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._64dc.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciSerialNumberLow. */ + DEVICE3.PciSerialNumberLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciSerialNumberLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciSerialNumberHigh. */ + DEVICE3.PciSerialNumberHigh.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciSerialNumberHigh.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget0. */ + DEVICE3.PciPowerBudget0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget1. */ + DEVICE3.PciPowerBudget1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget2. */ + DEVICE3.PciPowerBudget2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget3. */ + DEVICE3.PciPowerBudget3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget4. */ + DEVICE3.PciPowerBudget4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget5. */ + DEVICE3.PciPowerBudget5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget6. */ + DEVICE3.PciPowerBudget6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.PciPowerBudget7. */ + DEVICE3.PciPowerBudget7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.PciPowerBudget7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.6530. */ + DEVICE3._6530.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._6530.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.6550. */ + DEVICE3._6550.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._6550.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.65f4. */ + DEVICE3._65f4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._65f4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.GrcModeControl. */ + DEVICE3.GrcModeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.GrcModeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousConfig. */ + DEVICE3.MiscellaneousConfig.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MiscellaneousConfig.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MiscellaneousLocalControl. */ + DEVICE3.MiscellaneousLocalControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MiscellaneousLocalControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.Timer. */ + DEVICE3.Timer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.Timer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxCpuEvent. */ + DEVICE3.RxCpuEvent.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxCpuEvent.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.6838. */ + DEVICE3._6838.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._6838.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.MdiControl. */ + DEVICE3.MdiControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.MdiControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.RxCpuEventEnable. */ + DEVICE3.RxCpuEventEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.RxCpuEventEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.FastBootProgramCounter. */ + DEVICE3.FastBootProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.FastBootProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.ExpansionRomAddr. */ + DEVICE3.ExpansionRomAddr.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.ExpansionRomAddr.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.68f0. */ + DEVICE3._68f0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._68f0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.EavRefClockControl. */ + DEVICE3.EavRefClockControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3.EavRefClockControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE3_t.7c04. */ + DEVICE3._7c04.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE3._7c04.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + +} diff --git a/simulator/APE_DEVICE_sim.cpp b/simulator/APE_DEVICE_sim.cpp new file mode 100644 index 0000000..bbca657 --- /dev/null +++ b/simulator/APE_DEVICE_sim.cpp @@ -0,0 +1,608 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_DEVICE_sim.cpp +/// +/// @project ape +/// +/// @brief APE_DEVICE_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_DEVICE.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_DEVICE_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0040000; + + DEVICE.mIndexReadCallback = loader_read_mem; + DEVICE.mIndexReadCallbackArgs = base; + + DEVICE.mIndexWriteCallback = loader_write_mem; + DEVICE.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref DEVICE. */ + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousHostControl. */ + DEVICE.MiscellaneousHostControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MiscellaneousHostControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciState. */ + DEVICE.PciState.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciState.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RegisterBase. */ + DEVICE.RegisterBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RegisterBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MemoryBase. */ + DEVICE.MemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RegisterData. */ + DEVICE.RegisterData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RegisterData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndex. */ + DEVICE.UndiReceiveReturnRingConsumerIndex.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.UndiReceiveReturnRingConsumerIndex.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.UndiReceiveReturnRingConsumerIndexLow. */ + DEVICE.UndiReceiveReturnRingConsumerIndexLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.UndiReceiveReturnRingConsumerIndexLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.LinkStatusControl. */ + DEVICE.LinkStatusControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.LinkStatusControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ApeMemoryBase. */ + DEVICE.ApeMemoryBase.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ApeMemoryBase.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ApeMemoryData. */ + DEVICE.ApeMemoryData.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ApeMemoryData.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMode. */ + DEVICE.EmacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.LedControl. */ + DEVICE.LedControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.LedControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses0High. */ + DEVICE.EmacMacAddresses0High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses0High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses0Low. */ + DEVICE.EmacMacAddresses0Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses0Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses1High. */ + DEVICE.EmacMacAddresses1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses1Low. */ + DEVICE.EmacMacAddresses1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses2High. */ + DEVICE.EmacMacAddresses2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses2Low. */ + DEVICE.EmacMacAddresses2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses3High. */ + DEVICE.EmacMacAddresses3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EmacMacAddresses3Low. */ + DEVICE.EmacMacAddresses3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EmacMacAddresses3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.WolPatternPointer. */ + DEVICE.WolPatternPointer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.WolPatternPointer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.WolPatternCfg. */ + DEVICE.WolPatternCfg.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.WolPatternCfg.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MtuSize. */ + DEVICE.MtuSize.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MtuSize.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MiiCommunication. */ + DEVICE.MiiCommunication.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MiiCommunication.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MiiMode. */ + DEVICE.MiiMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MiiMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.TransmitMacMode. */ + DEVICE.TransmitMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.TransmitMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ReceiveMacMode. */ + DEVICE.ReceiveMacMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ReceiveMacMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch1High. */ + DEVICE.PerfectMatch1High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch1High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch1Low. */ + DEVICE.PerfectMatch1Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch1Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch2High. */ + DEVICE.PerfectMatch2High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch2High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch2Low. */ + DEVICE.PerfectMatch2Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch2Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch3High. */ + DEVICE.PerfectMatch3High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch3High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch3Low. */ + DEVICE.PerfectMatch3Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch3Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch4High. */ + DEVICE.PerfectMatch4High.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch4High.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PerfectMatch4Low. */ + DEVICE.PerfectMatch4Low.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PerfectMatch4Low.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.SgmiiStatus. */ + DEVICE.SgmiiStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.SgmiiStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.CpmuControl. */ + DEVICE.CpmuControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.CpmuControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.LinkAwarePowerModeClockPolicy. */ + DEVICE.LinkAwarePowerModeClockPolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.LinkAwarePowerModeClockPolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ClockSpeedOverridePolicy. */ + DEVICE.ClockSpeedOverridePolicy.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ClockSpeedOverridePolicy.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.Status. */ + DEVICE.Status.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.Status.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ClockStatus. */ + DEVICE.ClockStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ClockStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.GphyControlStatus. */ + DEVICE.GphyControlStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.GphyControlStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ChipId. */ + DEVICE.ChipId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ChipId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MutexRequest. */ + DEVICE.MutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MutexGrant. */ + DEVICE.MutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.GphyStrap. */ + DEVICE.GphyStrap.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.GphyStrap.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.TopLevelMiscellaneousControl1. */ + DEVICE.TopLevelMiscellaneousControl1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.TopLevelMiscellaneousControl1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EeeMode. */ + DEVICE.EeeMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EeeMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EeeLinkIdleControl. */ + DEVICE.EeeLinkIdleControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EeeLinkIdleControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EeeControl. */ + DEVICE.EeeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EeeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.GlobalMutexRequest. */ + DEVICE.GlobalMutexRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.GlobalMutexRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.GlobalMutexGrant. */ + DEVICE.GlobalMutexGrant.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.GlobalMutexGrant.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MemoryArbiterMode. */ + DEVICE.MemoryArbiterMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MemoryArbiterMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.BufferManagerMode. */ + DEVICE.BufferManagerMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.BufferManagerMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.LsoNonlsoBdReadDmaCorruptionEnableControl. */ + DEVICE.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.LsoNonlsoBdReadDmaCorruptionEnableControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscMode. */ + DEVICE.RxRiscMode.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscMode.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscStatus. */ + DEVICE.RxRiscStatus.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscStatus.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscProgramCounter. */ + DEVICE.RxRiscProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscCurrentInstruction. */ + DEVICE.RxRiscCurrentInstruction.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscCurrentInstruction.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscHardwareBreakpoint. */ + DEVICE.RxRiscHardwareBreakpoint.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscHardwareBreakpoint.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister0. */ + DEVICE.RxRiscRegister0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister1. */ + DEVICE.RxRiscRegister1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister2. */ + DEVICE.RxRiscRegister2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister3. */ + DEVICE.RxRiscRegister3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister4. */ + DEVICE.RxRiscRegister4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister5. */ + DEVICE.RxRiscRegister5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister6. */ + DEVICE.RxRiscRegister6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister7. */ + DEVICE.RxRiscRegister7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister8. */ + DEVICE.RxRiscRegister8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister9. */ + DEVICE.RxRiscRegister9.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister9.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister10. */ + DEVICE.RxRiscRegister10.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister10.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister11. */ + DEVICE.RxRiscRegister11.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister11.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister12. */ + DEVICE.RxRiscRegister12.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister12.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister13. */ + DEVICE.RxRiscRegister13.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister13.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister14. */ + DEVICE.RxRiscRegister14.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister14.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister15. */ + DEVICE.RxRiscRegister15.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister15.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister16. */ + DEVICE.RxRiscRegister16.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister16.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister17. */ + DEVICE.RxRiscRegister17.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister17.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister18. */ + DEVICE.RxRiscRegister18.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister18.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister19. */ + DEVICE.RxRiscRegister19.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister19.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister20. */ + DEVICE.RxRiscRegister20.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister20.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister21. */ + DEVICE.RxRiscRegister21.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister21.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister22. */ + DEVICE.RxRiscRegister22.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister22.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister23. */ + DEVICE.RxRiscRegister23.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister23.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister24. */ + DEVICE.RxRiscRegister24.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister24.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister25. */ + DEVICE.RxRiscRegister25.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister25.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister26. */ + DEVICE.RxRiscRegister26.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister26.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister27. */ + DEVICE.RxRiscRegister27.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister27.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister28. */ + DEVICE.RxRiscRegister28.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister28.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister29. */ + DEVICE.RxRiscRegister29.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister29.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister30. */ + DEVICE.RxRiscRegister30.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister30.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxRiscRegister31. */ + DEVICE.RxRiscRegister31.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxRiscRegister31.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.6408. */ + DEVICE._6408.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._6408.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerConsumptionInfo. */ + DEVICE.PciPowerConsumptionInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerConsumptionInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerDissipatedInfo. */ + DEVICE.PciPowerDissipatedInfo.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerDissipatedInfo.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciVpdRequest. */ + DEVICE.PciVpdRequest.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciVpdRequest.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciVpdResponse. */ + DEVICE.PciVpdResponse.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciVpdResponse.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciVendorDeviceId. */ + DEVICE.PciVendorDeviceId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciVendorDeviceId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciSubsystemId. */ + DEVICE.PciSubsystemId.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciSubsystemId.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciClassCodeRevision. */ + DEVICE.PciClassCodeRevision.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciClassCodeRevision.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.64c0. */ + DEVICE._64c0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._64c0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.64c8. */ + DEVICE._64c8.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._64c8.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.64dc. */ + DEVICE._64dc.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._64dc.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciSerialNumberLow. */ + DEVICE.PciSerialNumberLow.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciSerialNumberLow.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciSerialNumberHigh. */ + DEVICE.PciSerialNumberHigh.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciSerialNumberHigh.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget0. */ + DEVICE.PciPowerBudget0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget1. */ + DEVICE.PciPowerBudget1.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget1.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget2. */ + DEVICE.PciPowerBudget2.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget2.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget3. */ + DEVICE.PciPowerBudget3.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget3.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget4. */ + DEVICE.PciPowerBudget4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget5. */ + DEVICE.PciPowerBudget5.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget5.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget6. */ + DEVICE.PciPowerBudget6.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget6.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.PciPowerBudget7. */ + DEVICE.PciPowerBudget7.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.PciPowerBudget7.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.6530. */ + DEVICE._6530.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._6530.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.6550. */ + DEVICE._6550.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._6550.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.65f4. */ + DEVICE._65f4.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._65f4.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.GrcModeControl. */ + DEVICE.GrcModeControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.GrcModeControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousConfig. */ + DEVICE.MiscellaneousConfig.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MiscellaneousConfig.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MiscellaneousLocalControl. */ + DEVICE.MiscellaneousLocalControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MiscellaneousLocalControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.Timer. */ + DEVICE.Timer.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.Timer.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxCpuEvent. */ + DEVICE.RxCpuEvent.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxCpuEvent.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.6838. */ + DEVICE._6838.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._6838.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.MdiControl. */ + DEVICE.MdiControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.MdiControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.RxCpuEventEnable. */ + DEVICE.RxCpuEventEnable.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.RxCpuEventEnable.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.FastBootProgramCounter. */ + DEVICE.FastBootProgramCounter.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.FastBootProgramCounter.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.ExpansionRomAddr. */ + DEVICE.ExpansionRomAddr.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.ExpansionRomAddr.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.68f0. */ + DEVICE._68f0.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._68f0.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.EavRefClockControl. */ + DEVICE.EavRefClockControl.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE.EavRefClockControl.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref DEVICE_t.7c04. */ + DEVICE._7c04.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + DEVICE._7c04.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + +} diff --git a/utils/bcmregtool/apeloader/ape.h b/simulator/APE_FILTERS1.cpp index d4c9ae6..41c33ba 100644 --- a/utils/bcmregtool/apeloader/ape.h +++ b/simulator/APE_FILTERS1.cpp @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file stage1.h +/// @file APE_FILTERS1.cpp /// -/// @project +/// @project ape /// -/// @brief Functions provided by stage1. +/// @brief APE_FILTERS1 /// //////////////////////////////////////////////////////////////////////////////// /// @@ -22,7 +22,7 @@ /// 2. Redistributions in binary form must reproduce the above copyright notice, /// this list of conditions and the following disclaimer in the documentation /// and/or other materials provided with the distribution. -/// 3. Neither the name of the copyright holder nor the +/// 3. Neither the name of the <organization> nor the /// names of its contributors may be used to endorse or promote products /// derived from this software without specific prior written permission. /// @@ -42,25 +42,22 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -#ifndef APE_H -#define APE_H +#include <APE_FILTERS1.h> -// #include <bcm5719_eeprom.h> -// #include <bcm5719_GEN.h> +FILTERS_t FILTERS1; -// void early_init_hw(void); -// void load_nvm_config(NVRAMContents_t *nvram); -// void init_hw(NVRAMContents_t *nvram); +void init_APE_FILTERS1(void) +{ + /** @brief Component Registers for @ref FILTERS1. */ + /** @brief Bitmap for @ref FILTERS1_t.ElementConfig. */ -#define STATUS_MAIN (0x8234700u) -#define STATUS_EARLY_INIT (0x8234800u) -#define STATUS_NVM_CONFIG (0x8234900u) -#define STATUS_INIT_HW (0x8234A00u) + /** @brief Bitmap for @ref FILTERS1_t.ElementPattern. */ -// static inline void reportStatus(uint32_t code, uint8_t step) -// { -// GEN.GenDataSig.r32 = (code | step); -// } + /** @brief Bitmap for @ref FILTERS1_t.RuleConfiguration. */ + /** @brief Bitmap for @ref FILTERS1_t.RuleSet. */ -#endif /* APE_H */ + /** @brief Bitmap for @ref FILTERS1_t.RuleMask. */ + + +} diff --git a/simulator/APE_FILTERS1_sim.cpp b/simulator/APE_FILTERS1_sim.cpp new file mode 100644 index 0000000..c57bbe1 --- /dev/null +++ b/simulator/APE_FILTERS1_sim.cpp @@ -0,0 +1,124 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS1_sim.cpp +/// +/// @project ape +/// +/// @brief APE_FILTERS1_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_FILTERS1.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_FILTERS1_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0058000; + + FILTERS1.mIndexReadCallback = loader_read_mem; + FILTERS1.mIndexReadCallbackArgs = base; + + FILTERS1.mIndexWriteCallback = loader_write_mem; + FILTERS1.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref FILTERS1. */ + /** @brief Bitmap for @ref FILTERS1_t.ElementConfig. */ + for(int i = 0; i < 32; i++) + { + FILTERS1.ElementConfig[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS1.ElementConfig[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS1_t.ElementPattern. */ + for(int i = 0; i < 32; i++) + { + FILTERS1.ElementPattern[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS1.ElementPattern[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS1_t.RuleConfiguration. */ + FILTERS1.RuleConfiguration.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS1.RuleConfiguration.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref FILTERS1_t.RuleSet. */ + for(int i = 0; i < 31; i++) + { + FILTERS1.RuleSet[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS1.RuleSet[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS1_t.RuleMask. */ + for(int i = 0; i < 31; i++) + { + FILTERS1.RuleMask[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS1.RuleMask[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_FILTERS2.cpp b/simulator/APE_FILTERS2.cpp new file mode 100644 index 0000000..779fc3d --- /dev/null +++ b/simulator/APE_FILTERS2.cpp @@ -0,0 +1,63 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS2.cpp +/// +/// @project ape +/// +/// @brief APE_FILTERS2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_FILTERS2.h> + +FILTERS_t FILTERS2; + +void init_APE_FILTERS2(void) +{ + /** @brief Component Registers for @ref FILTERS2. */ + /** @brief Bitmap for @ref FILTERS2_t.ElementConfig. */ + + /** @brief Bitmap for @ref FILTERS2_t.ElementPattern. */ + + /** @brief Bitmap for @ref FILTERS2_t.RuleConfiguration. */ + + /** @brief Bitmap for @ref FILTERS2_t.RuleSet. */ + + /** @brief Bitmap for @ref FILTERS2_t.RuleMask. */ + + +} diff --git a/simulator/APE_FILTERS2_sim.cpp b/simulator/APE_FILTERS2_sim.cpp new file mode 100644 index 0000000..886a058 --- /dev/null +++ b/simulator/APE_FILTERS2_sim.cpp @@ -0,0 +1,124 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS2_sim.cpp +/// +/// @project ape +/// +/// @brief APE_FILTERS2_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_FILTERS2.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_FILTERS2_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0068000; + + FILTERS2.mIndexReadCallback = loader_read_mem; + FILTERS2.mIndexReadCallbackArgs = base; + + FILTERS2.mIndexWriteCallback = loader_write_mem; + FILTERS2.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref FILTERS2. */ + /** @brief Bitmap for @ref FILTERS2_t.ElementConfig. */ + for(int i = 0; i < 32; i++) + { + FILTERS2.ElementConfig[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS2.ElementConfig[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS2_t.ElementPattern. */ + for(int i = 0; i < 32; i++) + { + FILTERS2.ElementPattern[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS2.ElementPattern[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS2_t.RuleConfiguration. */ + FILTERS2.RuleConfiguration.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS2.RuleConfiguration.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref FILTERS2_t.RuleSet. */ + for(int i = 0; i < 31; i++) + { + FILTERS2.RuleSet[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS2.RuleSet[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS2_t.RuleMask. */ + for(int i = 0; i < 31; i++) + { + FILTERS2.RuleMask[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS2.RuleMask[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_FILTERS3.cpp b/simulator/APE_FILTERS3.cpp new file mode 100644 index 0000000..6b848b4 --- /dev/null +++ b/simulator/APE_FILTERS3.cpp @@ -0,0 +1,63 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS3.cpp +/// +/// @project ape +/// +/// @brief APE_FILTERS3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_FILTERS3.h> + +FILTERS_t FILTERS3; + +void init_APE_FILTERS3(void) +{ + /** @brief Component Registers for @ref FILTERS3. */ + /** @brief Bitmap for @ref FILTERS3_t.ElementConfig. */ + + /** @brief Bitmap for @ref FILTERS3_t.ElementPattern. */ + + /** @brief Bitmap for @ref FILTERS3_t.RuleConfiguration. */ + + /** @brief Bitmap for @ref FILTERS3_t.RuleSet. */ + + /** @brief Bitmap for @ref FILTERS3_t.RuleMask. */ + + +} diff --git a/simulator/APE_FILTERS3_sim.cpp b/simulator/APE_FILTERS3_sim.cpp new file mode 100644 index 0000000..dbab328 --- /dev/null +++ b/simulator/APE_FILTERS3_sim.cpp @@ -0,0 +1,124 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_FILTERS3_sim.cpp +/// +/// @project ape +/// +/// @brief APE_FILTERS3_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_FILTERS3.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_FILTERS3_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0078000; + + FILTERS3.mIndexReadCallback = loader_read_mem; + FILTERS3.mIndexReadCallbackArgs = base; + + FILTERS3.mIndexWriteCallback = loader_write_mem; + FILTERS3.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref FILTERS3. */ + /** @brief Bitmap for @ref FILTERS3_t.ElementConfig. */ + for(int i = 0; i < 32; i++) + { + FILTERS3.ElementConfig[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS3.ElementConfig[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS3_t.ElementPattern. */ + for(int i = 0; i < 32; i++) + { + FILTERS3.ElementPattern[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS3.ElementPattern[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS3_t.RuleConfiguration. */ + FILTERS3.RuleConfiguration.r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS3.RuleConfiguration.r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + + /** @brief Bitmap for @ref FILTERS3_t.RuleSet. */ + for(int i = 0; i < 31; i++) + { + FILTERS3.RuleSet[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS3.RuleSet[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + /** @brief Bitmap for @ref FILTERS3_t.RuleMask. */ + for(int i = 0; i < 31; i++) + { + FILTERS3.RuleMask[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + FILTERS3.RuleMask[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_RX_PORT.cpp b/simulator/APE_RX_PORT.cpp new file mode 100644 index 0000000..4eb4e45 --- /dev/null +++ b/simulator/APE_RX_PORT.cpp @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_RX_PORT.h> + +RX_PORT_t RX_PORT; + +void init_APE_RX_PORT(void) +{ + /** @brief Component Registers for @ref RX_PORT. */ + /** @brief Bitmap for @ref RX_PORT_t.In. */ + + +} diff --git a/simulator/APE_RX_PORT1.cpp b/simulator/APE_RX_PORT1.cpp new file mode 100644 index 0000000..da98e59 --- /dev/null +++ b/simulator/APE_RX_PORT1.cpp @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT1.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT1 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_RX_PORT1.h> + +RX_PORT_t RX_PORT1; + +void init_APE_RX_PORT1(void) +{ + /** @brief Component Registers for @ref RX_PORT1. */ + /** @brief Bitmap for @ref RX_PORT1_t.In. */ + + +} diff --git a/simulator/APE_RX_PORT1_sim.cpp b/simulator/APE_RX_PORT1_sim.cpp new file mode 100644 index 0000000..8cfdf65 --- /dev/null +++ b/simulator/APE_RX_PORT1_sim.cpp @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT1_sim.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT1_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_RX_PORT1.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_RX_PORT1_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0004000; + + RX_PORT1.mIndexReadCallback = loader_read_mem; + RX_PORT1.mIndexReadCallbackArgs = base; + + RX_PORT1.mIndexWriteCallback = loader_write_mem; + RX_PORT1.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref RX_PORT1. */ + /** @brief Bitmap for @ref RX_PORT1_t.In. */ + for(int i = 0; i < 4096; i++) + { + RX_PORT1.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + RX_PORT1.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_RX_PORT2.cpp b/simulator/APE_RX_PORT2.cpp new file mode 100644 index 0000000..27a2d08 --- /dev/null +++ b/simulator/APE_RX_PORT2.cpp @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT2.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT2 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_RX_PORT2.h> + +RX_PORT_t RX_PORT2; + +void init_APE_RX_PORT2(void) +{ + /** @brief Component Registers for @ref RX_PORT2. */ + /** @brief Bitmap for @ref RX_PORT2_t.In. */ + + +} diff --git a/simulator/APE_RX_PORT2_sim.cpp b/simulator/APE_RX_PORT2_sim.cpp new file mode 100644 index 0000000..c78d278 --- /dev/null +++ b/simulator/APE_RX_PORT2_sim.cpp @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT2_sim.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT2_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_RX_PORT2.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_RX_PORT2_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0008000; + + RX_PORT2.mIndexReadCallback = loader_read_mem; + RX_PORT2.mIndexReadCallbackArgs = base; + + RX_PORT2.mIndexWriteCallback = loader_write_mem; + RX_PORT2.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref RX_PORT2. */ + /** @brief Bitmap for @ref RX_PORT2_t.In. */ + for(int i = 0; i < 4096; i++) + { + RX_PORT2.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + RX_PORT2.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_RX_PORT3.cpp b/simulator/APE_RX_PORT3.cpp new file mode 100644 index 0000000..f444fe2 --- /dev/null +++ b/simulator/APE_RX_PORT3.cpp @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT3.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT3 +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <APE_RX_PORT3.h> + +RX_PORT_t RX_PORT3; + +void init_APE_RX_PORT3(void) +{ + /** @brief Component Registers for @ref RX_PORT3. */ + /** @brief Bitmap for @ref RX_PORT3_t.In. */ + + +} diff --git a/simulator/APE_RX_PORT3_sim.cpp b/simulator/APE_RX_PORT3_sim.cpp new file mode 100644 index 0000000..a46dc3e --- /dev/null +++ b/simulator/APE_RX_PORT3_sim.cpp @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT3_sim.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT3_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_RX_PORT3.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_RX_PORT3_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa000c000; + + RX_PORT3.mIndexReadCallback = loader_read_mem; + RX_PORT3.mIndexReadCallbackArgs = base; + + RX_PORT3.mIndexWriteCallback = loader_write_mem; + RX_PORT3.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref RX_PORT3. */ + /** @brief Bitmap for @ref RX_PORT3_t.In. */ + for(int i = 0; i < 4096; i++) + { + RX_PORT3.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + RX_PORT3.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/APE_RX_PORT_sim.cpp b/simulator/APE_RX_PORT_sim.cpp new file mode 100644 index 0000000..9f63ecb --- /dev/null +++ b/simulator/APE_RX_PORT_sim.cpp @@ -0,0 +1,99 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file APE_RX_PORT_sim.cpp +/// +/// @project ape +/// +/// @brief APE_RX_PORT_sim +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> +#include <APE_RX_PORT.h> + +static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_READ_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return (uint32_t)SHM.LoaderArg0.r32; +} + +static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) +{ + uint32_t addr = (uint32_t)((uint64_t)args); + addr += offset; + + SHM.LoaderArg0.r32 = addr; + SHM.LoaderArg1.r32 = val; + SHM.LoaderCommand.bits.Command = SHM_LOADER_COMMAND_COMMAND_WRITE_MEM; + + // Wait for command to be handled. + while(0 != SHM.LoaderCommand.bits.Command); + + return val; +} + +void init_APE_RX_PORT_sim(void *arg0) +{ + (void)arg0; // unused + void* base = (void*)0xa0000000; + + RX_PORT.mIndexReadCallback = loader_read_mem; + RX_PORT.mIndexReadCallbackArgs = base; + + RX_PORT.mIndexWriteCallback = loader_write_mem; + RX_PORT.mIndexWriteCallbackArgs = base; + + /** @brief Component Registers for @ref RX_PORT. */ + /** @brief Bitmap for @ref RX_PORT_t.In. */ + for(int i = 0; i < 4096; i++) + { + RX_PORT.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + RX_PORT.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + } + + +} diff --git a/simulator/CMakeLists.txt b/simulator/CMakeLists.txt index 5795cde..57e500b 100644 --- a/simulator/CMakeLists.txt +++ b/simulator/CMakeLists.txt @@ -31,6 +31,13 @@ simulator_add_library(${PROJECT_NAME} STATIC APE_FILTERS_sim.cpp APE_NVIC.cpp APE_NVIC_sim.cpp + + APE_TX_PORT.cpp + APE_TX_PORT_sim.cpp + + APE_RX_PORT.cpp + APE_RX_PORT_sim.cpp + ) include_directories(../libs/NVRam) diff --git a/simulator/HAL.cpp b/simulator/HAL.cpp index 364f33f..01f9032 100644 --- a/simulator/HAL.cpp +++ b/simulator/HAL.cpp @@ -12,6 +12,8 @@ #include <bcm5719_GEN.h> #include <APE_NVIC.h> #include <APE_FILTERS.h> +#include <APE_TX_PORT.h> +#include <APE_RX_PORT.h> #include <dirent.h> #include <endian.h> @@ -284,5 +286,11 @@ bool initHAL(const char *pci_path, int wanted_function) init_APE_NVIC(); init_APE_NVIC_sim(NULL); + init_APE_TX_PORT(); + init_APE_TX_PORT_sim(NULL); + + init_APE_RX_PORT(); + init_APE_RX_PORT_sim(NULL); + return true; } diff --git a/simulator/bcm5719_APE.cpp b/simulator/bcm5719_APE.cpp index eb62742..cd91752 100644 --- a/simulator/bcm5719_APE.cpp +++ b/simulator/bcm5719_APE.cpp @@ -63,6 +63,8 @@ void init_bcm5719_APE(void) /** @brief Bitmap for @ref APE_t.TxToNetDoorbellFunc0. */ + /** @brief Bitmap for @ref APE_t.TxState0. */ + /** @brief Bitmap for @ref APE_t.Mode2. */ /** @brief Bitmap for @ref APE_t.Status2. */ @@ -81,6 +83,10 @@ void init_bcm5719_APE(void) /** @brief Bitmap for @ref APE_t.TxToNetBufferAllocator0. */ + /** @brief Bitmap for @ref APE_t.TxToNetBufferReturn0. */ + + /** @brief Bitmap for @ref APE_t.TxToNetBufferRing0. */ + /** @brief Bitmap for @ref APE_t.Tick1mhz. */ /** @brief Bitmap for @ref APE_t.Tick1khz. */ diff --git a/simulator/bcm5719_APE_sim.cpp b/simulator/bcm5719_APE_sim.cpp index 4d21c3f..113ecf0 100644 --- a/simulator/bcm5719_APE_sim.cpp +++ b/simulator/bcm5719_APE_sim.cpp @@ -109,6 +109,10 @@ void init_bcm5719_APE_sim(void *base) APE.TxToNetDoorbellFunc0.r32.installReadCallback(read_from_ram, (uint8_t *)base); APE.TxToNetDoorbellFunc0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + /** @brief Bitmap for @ref APE_t.TxState0. */ + APE.TxState0.r32.installReadCallback(read_from_ram, (uint8_t *)base); + APE.TxState0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + /** @brief Bitmap for @ref APE_t.Mode2. */ APE.Mode2.r32.installReadCallback(read_from_ram, (uint8_t *)base); APE.Mode2.r32.installWriteCallback(write_to_ram, (uint8_t *)base); @@ -145,6 +149,14 @@ void init_bcm5719_APE_sim(void *base) APE.TxToNetBufferAllocator0.r32.installReadCallback(read_from_ram, (uint8_t *)base); APE.TxToNetBufferAllocator0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + /** @brief Bitmap for @ref APE_t.TxToNetBufferReturn0. */ + APE.TxToNetBufferReturn0.r32.installReadCallback(read_from_ram, (uint8_t *)base); + APE.TxToNetBufferReturn0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + + /** @brief Bitmap for @ref APE_t.TxToNetBufferRing0. */ + APE.TxToNetBufferRing0.r32.installReadCallback(read_from_ram, (uint8_t *)base); + APE.TxToNetBufferRing0.r32.installWriteCallback(write_to_ram, (uint8_t *)base); + /** @brief Bitmap for @ref APE_t.Tick1mhz. */ APE.Tick1mhz.r32.installReadCallback(read_from_ram, (uint8_t *)base); APE.Tick1mhz.r32.installWriteCallback(write_to_ram, (uint8_t *)base); diff --git a/simulator/include/CXXRegister.h b/simulator/include/CXXRegister.h index d565d4d..251a9b9 100644 --- a/simulator/include/CXXRegister.h +++ b/simulator/include/CXXRegister.h @@ -2,7 +2,7 @@ /// /// @file CXXRegister.h /// -/// @project +/// @project /// /// @brief C++ REgister wrapper code /// @@ -44,11 +44,11 @@ #ifndef CXX_REGISTER_H #define CXX_REGISTER_H -#include <vector> -#include <utility> -#include <stdio.h> +#include <iomanip> // std::setw #include <iostream> -#include <iomanip> // std::setw +#include <stdio.h> +#include <utility> +#include <vector> class CXXRegisterBase { @@ -60,27 +60,26 @@ public: mBaseRegister = NULL; mBitWidth = width; mBitPosition = offset; - for(unsigned int i = offset; i < offset + width; i++) + for (unsigned int i = offset; i < offset + width; i++) { mMask |= 1u << i; } } - virtual void setBaseRegister(CXXRegisterBase* base) + virtual void setBaseRegister(CXXRegisterBase *base) { // assert(base != NULL, "Base must not be null"); mBaseRegister = base; base->addRelatedRegister(this); - } - void setName(const char* name) + void setName(const char *name) { mName = name; } - const char* getName(void) + const char *getName(void) { return mName; } @@ -98,40 +97,42 @@ public: void print(unsigned int value, int indent = false) { unsigned int masked = value & mMask; - if(indent) + if (indent) { - std::cout << std::right << std::setw(35) << mName << ": 0x" << std::hex << (masked >> mBitPosition) << std::endl; + std::cout << std::right << std::setw(35) << mName << ": 0x" + << std::hex << (masked >> mBitPosition) << std::endl; } else { - std::cout << std::endl << std::left << std::setw(36) << mName << " 0x" << std::hex << (masked >> mBitPosition) << std::endl; + std::cout << std::endl + << std::left << std::setw(36) << mName << " 0x" + << std::hex << (masked >> mBitPosition) << std::endl; } } void printAll(unsigned int value) { - std::vector<CXXRegisterBase*>::iterator it; - for(it = mRelatedRegisters.begin(); it != mRelatedRegisters.end(); it++) + std::vector<CXXRegisterBase *>::iterator it; + for (it = mRelatedRegisters.begin(); it != mRelatedRegisters.end(); + it++) { (*it)->print(value, true); } } - protected: unsigned int mComponentOffset; unsigned int mBitPosition; unsigned int mBitWidth; unsigned int mMask; - const char* mName; + const char *mName; - std::vector<CXXRegisterBase*> mRelatedRegisters; + std::vector<CXXRegisterBase *> mRelatedRegisters; // This is the main controller register - CXXRegisterBase* mBaseRegister; - + CXXRegisterBase *mBaseRegister; - virtual void addRelatedRegister(CXXRegisterBase* related) + virtual void addRelatedRegister(CXXRegisterBase *related) { mRelatedRegisters.push_back(related); } @@ -145,18 +146,25 @@ protected: virtual void setRawValue(unsigned int) = 0; virtual void setTempValue(unsigned int) = 0; - - void doRelatedWritesBase(CXXRegisterBase* source) + void doRelatedWritesBase(CXXRegisterBase *source) { + if (source->mMask != this->mMask) + { + // read latest value as we are only modifying some bits. + doReadCallbacks(); + setRawValue(getTempValue()); + } + // Update base temp value with latest write. unsigned int base = getRawValue(); base &= ~(source->mMask); unsigned int tempValue = base | source->getRawValue(); - // printf("Updating base from %x & %x to %x (new write: %x)\n", getRawValue(), ~source->mMask, tempValue, source->getRawValue()); + // printf("Updating base from %x & %x to %x (new write: %x)\n", + // getRawValue(), ~source->mMask, tempValue, source->getRawValue()); setTempValue(tempValue); // Call the write callbacks. This may update the raw value as needed. - if(this != source) + if (this != source) { doWriteCallbacks(); } @@ -166,9 +174,9 @@ protected: { // printf("doRelatedWrites on %p\n", this); // Call doRelatedWrites on the base register. - if(mBaseRegister) + if (mBaseRegister) { - mBaseRegister->doRelatedWritesBase(this); + mBaseRegister->doRelatedWritesBase(this); } else { @@ -177,15 +185,16 @@ protected: } } - void doRelatedReadsBase(CXXRegisterBase* source) + void doRelatedReadsBase(CXXRegisterBase *source) { // Read the latest from the base register. doReadCallbacks(); unsigned int readValue = getTempValue(); // Update chained registers. - std::vector<CXXRegisterBase*>::iterator it; - for(it = mRelatedRegisters.begin(); it != mRelatedRegisters.end(); it++) + std::vector<CXXRegisterBase *>::iterator it; + for (it = mRelatedRegisters.begin(); it != mRelatedRegisters.end(); + it++) { // Update chained registers with latest data from base register. (*it)->setRawValue(readValue); @@ -201,7 +210,7 @@ protected: void doRelatedReads() { // Call doRelatedReads on the base register. - if(mBaseRegister) + if (mBaseRegister) { mBaseRegister->doRelatedReadsBase(this); } @@ -213,12 +222,13 @@ protected: } }; -template<typename T, unsigned int OFFSET, unsigned int WIDTH> class CXXRegister : public CXXRegisterBase +template<typename T, unsigned int OFFSET, unsigned int WIDTH> +class CXXRegister : public CXXRegisterBase { private: - typedef T (*callback_t)(T val, unsigned int, void*); - std::vector< std::pair<callback_t, void*> > mReadCallback; - std::vector< std::pair<callback_t, void*> > mWriteCallback; + typedef T (*callback_t)(T val, unsigned int, void *); + std::vector<std::pair<callback_t, void *>> mReadCallback; + std::vector<std::pair<callback_t, void *>> mWriteCallback; T mValue; T mTempValue; @@ -227,29 +237,29 @@ private: { T val = mTempValue; // call callbacks - typename std::vector<std::pair<callback_t, void*>>::iterator it; - for(it = mWriteCallback.begin(); it != mWriteCallback.end(); it++) + typename std::vector<std::pair<callback_t, void *>>::iterator it; + for (it = mWriteCallback.begin(); it != mWriteCallback.end(); it++) { callback_t callback; callback = (*it).first; - if(callback) + if (callback) { val = callback(val, mComponentOffset, (*it).second); } } - mValue = val; + mValue = val; } virtual void doReadCallbacks(void) { // call callbacks T val = mValue; - typename std::vector<std::pair<callback_t, void*>>::iterator it; - for(it = mReadCallback.begin(); it != mReadCallback.end(); it++) + typename std::vector<std::pair<callback_t, void *>>::iterator it; + for (it = mReadCallback.begin(); it != mReadCallback.end(); it++) { callback_t callback; callback = (*it).first; - if(callback) + if (callback) { val = callback(val, mComponentOffset, (*it).second); } @@ -294,7 +304,8 @@ private: virtual void setTempValue(unsigned int newVal) { - // printf("Setting temp: 0x%x (%x)\n", (newVal & mMask) >> mBitPosition, newVal); + // printf("Setting temp: 0x%x (%x)\n", (newVal & mMask) >> mBitPosition, + // newVal); mTempValue = (newVal & mMask) >> mBitPosition; } @@ -310,19 +321,18 @@ public: mValue = val; } - void installReadCallback(callback_t callback, void* args) + void installReadCallback(callback_t callback, void *args) { - mReadCallback.push_back( std::make_pair(callback, args) ); + mReadCallback.push_back(std::make_pair(callback, args)); } - void installWriteCallback(callback_t callback, void* args) + void installWriteCallback(callback_t callback, void *args) { - mWriteCallback.push_back( std::make_pair(callback, args) ); + mWriteCallback.push_back(std::make_pair(callback, args)); } virtual ~CXXRegister() { - } void print(void) @@ -349,7 +359,7 @@ public: return mValue; } - T operator=(CXXRegister<T,OFFSET,WIDTH> val) + T operator=(CXXRegister<T, OFFSET, WIDTH> val) { // Write doWrite((T)val); @@ -427,8 +437,8 @@ public: // Read - xor - Write return this->operator=(operator T() ^ val); } + protected: }; - #endif /* CXX_REGISTER_H */
\ No newline at end of file diff --git a/stage1/main.c b/stage1/main.c index 5469fbd..5a8a1fa 100644 --- a/stage1/main.c +++ b/stage1/main.c @@ -47,22 +47,20 @@ #if CXX_SIMULATOR #include <HAL.hpp> #include <endian.h> -#define crc_swap(__x__) (__x__) /* No swapping needed on the host */ +#define crc_swap(__x__) (__x__) /* No swapping needed on the host */ #else #define be32toh(__x__) (__x__) -#define crc_swap(__x__) ((((__x__) & 0x000000FF) << 24) | \ - (((__x__) & 0x0000FF00) << 8 ) | \ - (((__x__) & 0x00FF0000) >> 8 ) | \ - (((__x__) & 0xFF000000) >> 24)) +#define crc_swap(__x__) \ + ((((__x__)&0x000000FF) << 24) | (((__x__)&0x0000FF00) << 8) | \ + (((__x__)&0x00FF0000) >> 8) | (((__x__)&0xFF000000) >> 24)) #endif +#include <APE.h> #include <NVRam.h> +#include <bcm5719_APE.h> #include <bcm5719_BOOTCODE.h> -#include <bcm5719_GEN.h> #include <bcm5719_DEVICE.h> -#include <bcm5719_APE.h> +#include <bcm5719_GEN.h> #include <bcm5719_SHM.h> -#include <APE.h> - #include <string.h> NVRAMContents_t gNVMContents; @@ -70,12 +68,12 @@ NVRAMContents_t gNVMContents; int main() { reportStatus(STATUS_MAIN, 0); - uint32_t* bootcode_dest; + uint32_t *bootcode_dest; #if CXX_SIMULATOR initHAL(NULL); - bootcode_dest = (uint32_t*)malloc(REG_BOOTCODE_SIZE); + bootcode_dest = (uint32_t *)malloc(REG_BOOTCODE_SIZE); #else - bootcode_dest = (uint32_t*)&BOOTCODE; + bootcode_dest = (uint32_t *)&BOOTCODE; #endif #if !CXX_SIMULATOR @@ -110,7 +108,7 @@ int main() SHM.RcpuCpmuStatus.bits.Status = (DEVICE.Status.r32 & 0xFFFF0000) >> 16; SHM.RcpuCpmuStatus.bits.Address = SHM_RCPU_CPMU_STATUS_ADDRESS_ADDRESS; - if(SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC != SHM.RcpuSegSig.bits.Sig) + if (SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC != SHM.RcpuSegSig.bits.Sig) { SHM.RcpuInitCount.r32 = 1; } @@ -125,8 +123,7 @@ int main() // Mark it as valid. SHM.RcpuSegLength.r32 = 0x34; - SHM.RcpuSegSig.bits.Sig = SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC; - + SHM.RcpuSegSig.bits.Sig = SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC; // Set GEN_FIRMWARE_MBOX to BOOTCODE_READY_MAGIC. reportStatus(GEN_GEN_DATA_SIG_SIG_DRIVER_READY, 0); @@ -138,7 +135,7 @@ int main() APE_releaseAllLocks(); DEVICE.RxCpuEventEnable.bits.VPDAttention = 1; - for(;;) + for (;;) { // APE heartbeat. // APE.RcpuApeResetCount.r32 = APE.RcpuApeResetCount.r32 + 1; @@ -146,21 +143,19 @@ int main() // APE.RcpuLastApeFwStatus.r32 = APE.FwStatus.r32; // Spin - if(DEVICE.RxCpuEvent.bits.VPDAttention) + if (DEVICE.RxCpuEvent.bits.VPDAttention) { uint32_t vpd_offset = DEVICE.PciVpdRequest.bits.RequestedVPDOffset; - union - { + union { uint8_t r8[4]; uint32_t r32; } vpd_data; vpd_data.r8[0] = gNVMContents.vpd.bytes[vpd_offset]; - vpd_data.r8[1] = gNVMContents.vpd.bytes[vpd_offset+1]; - vpd_data.r8[2] = gNVMContents.vpd.bytes[vpd_offset+2]; - vpd_data.r8[3] = gNVMContents.vpd.bytes[vpd_offset+3]; + vpd_data.r8[1] = gNVMContents.vpd.bytes[vpd_offset + 1]; + vpd_data.r8[2] = gNVMContents.vpd.bytes[vpd_offset + 2]; + vpd_data.r8[3] = gNVMContents.vpd.bytes[vpd_offset + 3]; DEVICE.PciVpdResponse.r32 = vpd_data.r32; } } - } diff --git a/stage1/stage1.h b/stage1/stage1.h index b73eb47..dac77aa 100644 --- a/stage1/stage1.h +++ b/stage1/stage1.h @@ -45,8 +45,8 @@ #ifndef STAGE1_H #define STAGE1_H -#include <bcm5719_eeprom.h> #include <bcm5719_GEN.h> +#include <bcm5719_eeprom.h> void early_init_hw(void); void load_nvm_config(NVRAMContents_t *nvram); @@ -62,5 +62,4 @@ static inline void reportStatus(uint32_t code, uint8_t step) GEN.GenDataSig.r32 = (code | step); } - #endif /* STAGE1_H */ diff --git a/utils/ape2elf/main.cpp b/utils/ape2elf/main.cpp index 801f4a9..1fbb427 100644 --- a/utils/ape2elf/main.cpp +++ b/utils/ape2elf/main.cpp @@ -42,50 +42,46 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// +#include <Compress.h> #include <NVRam.h> -#include <bcm5719_eeprom.h> - #include <OptionParser.h> -#include <Compress.h> - - +#include <bcm5719_eeprom.h> #include <elfio/elfio.hpp> #define ENTRYPOINT_SYMBOL "__start" #define VERSION_SYMBOL "VERSION" -#define STACK_END_SYMBOL "_estack" +#define STACK_END_SYMBOL "_estack" #define THUMB_CODE_SYMBOL "$t" using namespace std; using namespace ELFIO; using optparse::OptionParser; -#define MAX_SIZE (1024u * 256u) /* 256KB - max NVRAM */ +#define MAX_SIZE (1024u * 256u) /* 256KB - max NVRAM */ int main(int argc, char const *argv[]) { union { uint8_t bytes[MAX_SIZE]; - uint32_t words[MAX_SIZE/4]; + uint32_t words[MAX_SIZE / 4]; APEHeader_t header; } ape; OptionParser parser = OptionParser().description("BCM APE to elf Utility"); parser.add_option("-i", "--input") - .dest("input") - .help("Read from the input ape binary") - .metavar("FILE"); - + .dest("input") + .help("Read from the input ape binary") + .metavar("FILE"); parser.add_option("-o", "--output") - .dest("output") - .help("Save to the specified output elf file") - .metavar("FILE"); + .dest("output") + .help("Save to the specified output elf file") + .metavar("FILE"); optparse::Values options = parser.parse_args(argc, argv); vector<string> args = parser.args(); - if(!options.is_set("input")) + if (!options.is_set("input")) { cerr << "Please specify an ape binary to use." << endl; parser.print_help(); @@ -94,14 +90,14 @@ int main(int argc, char const *argv[]) fstream infile; infile.open(options["input"], fstream::in | fstream::binary); - if(infile.is_open()) + if (infile.is_open()) { - infile.read((char*)ape.bytes, MAX_SIZE); + infile.read((char *)ape.bytes, MAX_SIZE); - if(ape.words[0] == be32toh(APE_HEADER_MAGIC)) + if (ape.words[0] == be32toh(APE_HEADER_MAGIC)) { // The file is swapped... fix it. - for(int i = 0; i < sizeof(ape)/sizeof(ape.words[0]); i++) + for (int i = 0; i < sizeof(ape) / sizeof(ape.words[0]); i++) { ape.words[i] = be32toh(ape.words[i]); } @@ -115,40 +111,39 @@ int main(int argc, char const *argv[]) exit(-1); } - elfio writer; - + // Setup the elf header - writer.create( ELFCLASS32, ELFDATA2LSB ); - writer.set_os_abi( ELFOSABI_NONE ); - writer.set_type( ET_EXEC ); - writer.set_machine( EM_ARM ); + writer.create(ELFCLASS32, ELFDATA2LSB); + writer.set_os_abi(ELFOSABI_NONE); + writer.set_type(ET_EXEC); + writer.set_machine(EM_ARM); // Create code section - section* text_sec = writer.sections.add( ".text" ); - segment* text_seg = writer.segments.add(); - text_sec->set_type( SHT_PROGBITS ); - text_sec->set_flags( SHF_ALLOC | SHF_EXECINSTR ); - text_sec->set_addr_align( 0x4 ); - - section* bss_sec = writer.sections.add( ".bss" ); - segment* bss_seg = writer.segments.add(); - bss_sec->set_type( SHT_PROGBITS ); - bss_sec->set_flags( SHF_ALLOC | SHF_WRITE ); - bss_sec->set_addr_align( 0x4 ); - - section* data_sec = writer.sections.add( ".data" ); - segment* data_seg = writer.segments.add(); - data_sec->set_type( SHT_PROGBITS ); - data_sec->set_flags( SHF_ALLOC | SHF_WRITE ); - data_sec->set_addr_align( 0x4 ); + section *text_sec = writer.sections.add(".text"); + segment *text_seg = writer.segments.add(); + text_sec->set_type(SHT_PROGBITS); + text_sec->set_flags(SHF_ALLOC | SHF_EXECINSTR); + text_sec->set_addr_align(0x4); + + section *bss_sec = writer.sections.add(".bss"); + segment *bss_seg = writer.segments.add(); + bss_sec->set_type(SHT_PROGBITS); + bss_sec->set_flags(SHF_ALLOC | SHF_WRITE); + bss_sec->set_addr_align(0x4); + + section *data_sec = writer.sections.add(".data"); + segment *data_seg = writer.segments.add(); + data_sec->set_type(SHT_PROGBITS); + data_sec->set_flags(SHF_ALLOC | SHF_WRITE); + data_sec->set_addr_align(0x4); printf("=== Header ===\n"); printf("Magic: 0x%08X\n", ape.header.magic); printf("UNK0: 0x%08X\n", ape.header.unk0); char name[sizeof(ape.header.name) + 1] = {0}; - strncpy(name, (char*)ape.header.name, sizeof(ape.header.name)); + strncpy(name, (char *)ape.header.name, sizeof(ape.header.name)); printf("Name: %s\n", name); printf("Version: 0x%08X\n", ape.header.version); printf("Start: 0x%08X\n", ape.header.entrypoint); @@ -164,35 +159,36 @@ int main(int argc, char const *argv[]) uint32_t calculated_crc = NVRam_crc(ape.bytes, (4 * ape.header.words), 0); printf("Calculated CRC: 0x%08X\n", calculated_crc); - for(int i = 0; i < ape.header.sections; i++) + for (int i = 0; i < ape.header.sections; i++) { - uint8_t * inBufferPtr = NULL; - uint8_t * outBufferPtr = NULL; + uint8_t *inBufferPtr = NULL; + uint8_t *outBufferPtr = NULL; ssize_t inBufferSize; ssize_t outBufferSize; - size_t out_length; + size_t out_length; - APESection_t* section = &ape.header.section[i]; + APESection_t *section = &ape.header.section[i]; printf("\n=== Section %i ===\n", i); printf("Load Addr: 0x%08X\n", section->loadAddr); printf("Offset: 0x%08X\n", section->offset); printf("Flags: 0x%08X\n", section->flags); - if(section->flags & APE_SECTION_FLAG_COMPRESSED) + if (section->flags & APE_SECTION_FLAG_COMPRESSED) { printf(" compressed\n"); } - if(section->flags & APE_SECTION_FLAG_CHECKSUM_IS_CRC32) + if (section->flags & APE_SECTION_FLAG_CHECKSUM_IS_CRC32) { printf(" crc32\n"); } - printf(" %s\n", section->flags & APE_SECTION_FLAG_CODE ? "code" : "data"); - if(section->flags & APE_SECTION_FLAG_UNK0) + printf(" %s\n", + section->flags & APE_SECTION_FLAG_CODE ? "code" : "data"); + if (section->flags & APE_SECTION_FLAG_UNK0) { printf(" unknown\n"); } - if(section->flags & APE_SECTION_FLAG_ZERO_ON_FAST_BOOT) + if (section->flags & APE_SECTION_FLAG_ZERO_ON_FAST_BOOT) { printf(" bss\n"); } @@ -204,99 +200,97 @@ int main(int argc, char const *argv[]) inBufferSize = section->compressedSize; outBufferPtr = (uint8_t *)malloc(section->decompressedSize); outBufferSize = section->decompressedSize; - out_length = decompress(outBufferPtr, outBufferSize, inBufferPtr, inBufferSize); + out_length = + decompress(outBufferPtr, outBufferSize, inBufferPtr, inBufferSize); calculated_crc = NVRam_crc(outBufferPtr, outBufferSize, 0); printf("out_length: 0x%08zX\n", out_length); printf("out CRC: 0x%08X\n", calculated_crc); - if(ape.header.sections == 4 && i == 0) continue; - if(section->flags & APE_SECTION_FLAG_ZERO_ON_FAST_BOOT) + if (ape.header.sections == 4 && i == 0) + continue; + if (section->flags & APE_SECTION_FLAG_ZERO_ON_FAST_BOOT) { - bss_sec->set_data((const char*)outBufferPtr, out_length); - bss_seg->set_type( PT_LOAD ); - bss_seg->set_virtual_address( section->loadAddr ); - bss_seg->set_physical_address( section->loadAddr ); - bss_seg->set_flags( PF_W | PF_R ); - bss_seg->set_align( 0x4 ); + bss_sec->set_data((const char *)outBufferPtr, out_length); + bss_seg->set_type(PT_LOAD); + bss_seg->set_virtual_address(section->loadAddr); + bss_seg->set_physical_address(section->loadAddr); + bss_seg->set_flags(PF_W | PF_R); + bss_seg->set_align(0x4); // Add data section into data segment - bss_seg->add_section_index( bss_sec->get_index(), bss_sec->get_addr_align() ); + bss_seg->add_section_index(bss_sec->get_index(), + bss_sec->get_addr_align()); } - else if(!(section->flags & APE_SECTION_FLAG_CODE)) + else if (!(section->flags & APE_SECTION_FLAG_CODE)) { - data_sec->set_data((const char*)outBufferPtr, out_length); - data_seg->set_type( PT_LOAD ); - data_seg->set_virtual_address( section->loadAddr ); - data_seg->set_physical_address( section->loadAddr ); - data_seg->set_flags( PF_W | PF_R ); - data_seg->set_align( 0x4 ); + data_sec->set_data((const char *)outBufferPtr, out_length); + data_seg->set_type(PT_LOAD); + data_seg->set_virtual_address(section->loadAddr); + data_seg->set_physical_address(section->loadAddr); + data_seg->set_flags(PF_W | PF_R); + data_seg->set_align(0x4); // Add data section into data segment - data_seg->add_section_index( data_sec->get_index(), data_sec->get_addr_align() ); + data_seg->add_section_index(data_sec->get_index(), + data_sec->get_addr_align()); } else { - text_sec->set_data((const char*)outBufferPtr, out_length); - text_seg->set_type( PT_LOAD ); - text_seg->set_virtual_address( section->loadAddr ); - text_seg->set_physical_address( section->loadAddr ); - text_seg->set_flags( PF_X | PF_R ); - text_seg->set_align( 0x4 ); + text_sec->set_data((const char *)outBufferPtr, out_length); + text_seg->set_type(PT_LOAD); + text_seg->set_virtual_address(section->loadAddr); + text_seg->set_physical_address(section->loadAddr); + text_seg->set_flags(PF_X | PF_R); + text_seg->set_align(0x4); // Add code section into program segment - text_seg->add_section_index( text_sec->get_index(), text_sec->get_addr_align() ); - + text_seg->add_section_index(text_sec->get_index(), + text_sec->get_addr_align()); } } - if(options.is_set("output")) + if (options.is_set("output")) { // REcord entry-point address writer.set_entry(ape.header.entrypoint); // Create string table section - section* str_sec = writer.sections.add( ".strtab" ); - str_sec->set_type ( SHT_STRTAB ); + section *str_sec = writer.sections.add(".strtab"); + str_sec->set_type(SHT_STRTAB); // Create string table writer - string_section_accessor stra( str_sec ); + string_section_accessor stra(str_sec); // Create symbol table section - section* sym_sec = writer.sections.add( ".symtab" ); - sym_sec->set_type ( SHT_SYMTAB ); - sym_sec->set_info ( 2 ); - sym_sec->set_addr_align( 0x4 ); - sym_sec->set_entry_size( writer.get_default_entry_size( SHT_SYMTAB ) ); - sym_sec->set_link ( str_sec->get_index() ); + section *sym_sec = writer.sections.add(".symtab"); + sym_sec->set_type(SHT_SYMTAB); + sym_sec->set_info(2); + sym_sec->set_addr_align(0x4); + sym_sec->set_entry_size(writer.get_default_entry_size(SHT_SYMTAB)); + sym_sec->set_link(str_sec->get_index()); // Create symbol table writer - symbol_section_accessor syma( writer, sym_sec ); - + symbol_section_accessor syma(writer, sym_sec); // Add label name - Elf32_Word _start = stra.add_string( ENTRYPOINT_SYMBOL ); - Elf32_Word _thumb = stra.add_string( THUMB_CODE_SYMBOL ); - Elf32_Word _version = stra.add_string( VERSION_SYMBOL ); + Elf32_Word _start = stra.add_string(ENTRYPOINT_SYMBOL); + Elf32_Word _thumb = stra.add_string(THUMB_CODE_SYMBOL); + Elf32_Word _version = stra.add_string(VERSION_SYMBOL); // Add symbol entry - syma.add_symbol( _start, ape.header.entrypoint, 0, STB_GLOBAL, - STT_FUNC, 0, - text_sec->get_index() ); - - syma.add_symbol( _thumb, ape.header.entrypoint & 0xfffffffe, 0, STB_LOCAL, - STT_OBJECT, 0, - text_sec->get_index() ); + syma.add_symbol(_start, ape.header.entrypoint, 0, STB_GLOBAL, STT_FUNC, + 0, text_sec->get_index()); - syma.add_symbol( _version, ape.header.version, 0, STB_GLOBAL, - STT_OBJECT, 0, - text_sec->get_index() ); + syma.add_symbol(_thumb, ape.header.entrypoint & 0xfffffffe, 0, + STB_LOCAL, STT_OBJECT, 0, text_sec->get_index()); - uint32_t* vectors = (uint32_t*)text_sec->get_data(); - Elf32_Word index = stra.add_string( STACK_END_SYMBOL ); - syma.add_symbol( index, vectors[0], 0, STB_GLOBAL, - STT_OBJECT, 0, - data_sec->get_index() ); + syma.add_symbol(_version, ape.header.version, 0, STB_GLOBAL, STT_OBJECT, + 0, text_sec->get_index()); + uint32_t *vectors = (uint32_t *)text_sec->get_data(); + Elf32_Word index = stra.add_string(STACK_END_SYMBOL); + syma.add_symbol(index, vectors[0], 0, STB_GLOBAL, STT_OBJECT, 0, + data_sec->get_index()); // Create ELF file writer.save(options["output"]); diff --git a/utils/bcmregtool/CMakeLists.txt b/utils/bcmregtool/CMakeLists.txt index 76fa724..2a3cb86 100644 --- a/utils/bcmregtool/CMakeLists.txt +++ b/utils/bcmregtool/CMakeLists.txt @@ -9,7 +9,7 @@ set(SOURCES ) simulator_add_executable(${PROJECT_NAME} ${SOURCES}) -target_link_libraries(${PROJECT_NAME} PRIVATE NVRam VPD MII APE apeloader-binary NCSI) +target_link_libraries(${PROJECT_NAME} PRIVATE NVRam VPD MII APE apeloader-binary NCSI Network) target_link_libraries(${PROJECT_NAME} PRIVATE simulator OptParse elfio) INSTALL(TARGETS ${PROJECT_NAME} DESTINATION .) diff --git a/utils/bcmregtool/apeloader/main.c b/utils/bcmregtool/apeloader/main.c index 71e25c5..f1e886b 100644 --- a/utils/bcmregtool/apeloader/main.c +++ b/utils/bcmregtool/apeloader/main.c @@ -42,8 +42,6 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -#include "ape.h" - #include <APE_SHM.h> int __start() @@ -52,15 +50,18 @@ int __start() SHM.SegSig.bits.Sig = SHM_SEG_SIG_SIG_LOADER; SHM.FwStatus.bits.Ready = 1; - for(;;) + for (;;) { uint32_t command = SHM.LoaderCommand.bits.Command; - if(!command) continue; + if (!command) + { + continue; + } uint32_t arg0 = SHM.LoaderArg0.r32; uint32_t arg1 = SHM.LoaderArg1.r32; - switch(command) + switch (command) { default: break; @@ -68,21 +69,21 @@ int __start() case SHM_LOADER_COMMAND_COMMAND_READ_MEM: { // Read word address specified in arg0 - uint32_t* addr = ((void*)arg0); + uint32_t *addr = ((void *)arg0); SHM.LoaderArg0.r32 = *addr; break; } case SHM_LOADER_COMMAND_COMMAND_WRITE_MEM: { // Write word address specified in arg0 with arg1 - uint32_t* addr = ((void*)arg0); + uint32_t *addr = ((void *)arg0); *addr = arg1; break; } case SHM_LOADER_COMMAND_COMMAND_CALL: { // call address specified in arg0. - void (*function)(uint32_t) = ((void*)arg0); + void (*function)(uint32_t) = ((void *)arg0); function(arg1); break; } @@ -91,5 +92,4 @@ int __start() // Mark command as handled. SHM.LoaderCommand.bits.Command = 0; } - }
\ No newline at end of file diff --git a/utils/bcmregtool/main.cpp b/utils/bcmregtool/main.cpp index c706e3d..30b30fe 100644 --- a/utils/bcmregtool/main.cpp +++ b/utils/bcmregtool/main.cpp @@ -69,13 +69,9 @@ #include <bcm5719_SHM_CHANNEL0.h> #include <elfio/elfio.hpp> -#include <APE_FILTERS.h> -#include <APE_NVIC.h> +#include <types.h> #include <APE_APE_PERI.h> -#include <Ethernet.h> -#include <NCSI.h> - #include "../NVRam/bcm5719_NVM.h" using namespace std; @@ -315,7 +311,7 @@ void step(void) // Force a re-load of the next word. uint32_t newPC = DEVICE.RxRiscProgramCounter.r32; - if(oldPC +4 != newPC) + if(oldPC + 4 != newPC) { // branched. Re-read PC to re-read opcode DEVICE.RxRiscProgramCounter.r32 = DEVICE.RxRiscProgramCounter.r32; @@ -383,11 +379,36 @@ int main(int argc, char const *argv[]) .action("store_true") .help("Print ape information registers."); + parser.add_option("-rx", "--rx") + .dest("rx") + .set_default("0") + .action("store_true") + .help("Print rx information registers."); + + parser.add_option("-tx", "--tx") + .dest("tx") + .set_default("0") + .action("store_true") + .help("Print tx information registers."); + parser.add_option("-p", "--apeboot") .dest("apeboot") .metavar("APE_FILE") .help("File to boot on the APE."); + + parser.add_option("-apereset", "--apereset") + .dest("apereset") + .set_default("0") + .action("store_true") + .help("File to boot on the APE."); + + parser.add_option("-reset", "--reset") + .dest("reset") + .set_default("0") + .action("store_true") + .help("File to boot on the APE."); + parser.add_option("-m", "--mii") .dest("mii") .set_default("0") @@ -574,6 +595,9 @@ int main(int argc, char const *argv[]) // Set the payload address APE.GpioMessage.r32 = 0x10D800|2; + // Clear the signature. + SHM.SegSig.r32 = 0xBAD0C0DE; + // Boot mode.bits.Halt = 0; mode.bits.FastBoot = 1; @@ -583,6 +607,64 @@ int main(int argc, char const *argv[]) exit(0); } + if(options.get("apereset")) + { + + // Halt + RegAPEMode_t mode; + mode.r32 = 0; + mode.bits.Halt = 1; + mode.bits.FastBoot = 0; + APE.Mode = mode; + + // Boot + mode.bits.Halt = 0; + mode.bits.FastBoot = 0; + mode.bits.Reset = 1; + APE.Mode = mode; + + exit(0); + } + + if(options.get("reset")) + { + + DEVICE.MiscellaneousConfig.bits.GRCReset = 1; + exit(0); + } + + + + if(options.get("rx")) + { + DEVICE.ReceiveMacMode.print(); + DEVICE.EmacMode.print(); + APE.RxbufoffsetFunc0.print(); + APE.RxPoolModeStatus0.print(); + + exit(0); + } + + if(options.get("tx")) + { + DEVICE.GrcModeControl.print(); + DEVICE.EmacMode.print(); + APE.Mode.print(); + APE.Status.print(); + APE.TxState0.print(); + APE.TxToNetPoolModeStatus0.print(); + APE.TxToNetBufferAllocator0.print(); + APE.TxToNetBufferRing0.print(); + APE.TxToNetBufferReturn0.print(); + APE.TxToNetDoorbellFunc0.print(); + if(APE.TxToNetDoorbellFunc0.bits.TXQueueFull) + { + fprintf(stderr, "TX Queue Full\n"); + } + + exit(0); + } + if(options.get("ape")) { APE.Mode.print(); @@ -605,6 +687,15 @@ int main(int argc, char const *argv[]) printf("APE RCPU PCI Vendor/Device ID: 0x%08X\n", (uint32_t)SHM.RcpuPciVendorDeviceId.r32); printf("APE RCPU PCI Subsystem ID: 0x%08X\n", (uint32_t)SHM.RcpuPciSubsystemId.r32); + APE_PERI.RmuControl.print(); + + DEVICE.PerfectMatch1High.print(); + DEVICE.PerfectMatch1Low.print(); + + + APE.TxToNetPoolModeStatus0.print(); + APE.RxPoolModeStatus0.print(); + exit(0); } diff --git a/utils/elf2ape/main.cpp b/utils/elf2ape/main.cpp index 7a372ba..f824eb5 100644 --- a/utils/elf2ape/main.cpp +++ b/utils/elf2ape/main.cpp @@ -42,13 +42,10 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// - - -#include <bcm5719_eeprom.h> -#include <NVRam.h> #include <Compress.h> - +#include <NVRam.h> #include <OptionParser.h> +#include <bcm5719_eeprom.h> #include <elfio/elfio.hpp> using namespace ELFIO; @@ -56,43 +53,43 @@ using namespace ELFIO; using namespace std; using optparse::OptionParser; - - -uint64_t get_symbol_value(const char* search, elfio &reader) +uint64_t get_symbol_value(const char *search, elfio &reader) { - const symbol_section_accessor* psyms = NULL; + const symbol_section_accessor *psyms = NULL; Elf_Half sec_num = reader.sections.size(); - for ( int - i = 0; i < sec_num; ++i ) { - section* psec = reader.sections[i]; + for (int i = 0; i < sec_num; ++i) + { + section *psec = reader.sections[i]; // Check section type - if ( psec->get_type() == SHT_SYMTAB ) { - psyms = new symbol_section_accessor( reader, psec ); + if (psec->get_type() == SHT_SYMTAB) + { + psyms = new symbol_section_accessor(reader, psec); break; } } - if(psyms) + if (psyms) { - for ( unsigned int j = 0; j < psyms->get_symbols_num(); ++j ) { - std::string name; - Elf64_Addr value; - Elf_Xword size; + for (unsigned int j = 0; j < psyms->get_symbols_num(); ++j) + { + std::string name; + Elf64_Addr value; + Elf_Xword size; unsigned char bind; unsigned char type; - Elf_Half section_index; + Elf_Half section_index; unsigned char other; - + // Read symbol properties - psyms->get_symbol( j, name, value, size, bind, - type, section_index, other ); + psyms->get_symbol(j, name, value, size, bind, type, section_index, + other); // std::cout << j << " " << name << " " << value << std::endl; - if(name == search) + if (name == search) { return value; - } + } } delete psyms; @@ -101,11 +98,11 @@ uint64_t get_symbol_value(const char* search, elfio &reader) return 0; } -bool save_to_file(const char* filename, void* buffer, size_t size) +bool save_to_file(const char *filename, void *buffer, size_t size) { cout << "Writing to " << filename << "." << endl; - FILE* out = fopen(filename, "w+"); - if(out) + FILE *out = fopen(filename, "w+"); + if (out) { fwrite(buffer, size, 1, out); fclose(out); @@ -118,144 +115,132 @@ bool save_to_file(const char* filename, void* buffer, size_t size) } } -#define MAX_SIZE (1024u * 256u) /* 256KB - max NVRAM */ +#define MAX_SIZE (1024u * 256u) /* 256KB - max NVRAM */ int main(int argc, char const *argv[]) { uint32_t byteOffset = 0; int numSections = 0; union { - uint8_t bytes[MAX_SIZE]; - uint32_t words[MAX_SIZE/4]; + uint8_t bytes[MAX_SIZE]; + uint32_t words[MAX_SIZE / 4]; APEHeader_t header; } ape; OptionParser parser = OptionParser().description("BCM elf 2 APE Utility"); parser.add_option("-i", "--input") - .dest("input") - .help("Input elf file to convert") - .metavar("FILE"); - + .dest("input") + .help("Input elf file to convert") + .metavar("FILE"); parser.add_option("-o", "--output") - .dest("output") - .help("Output ape binary") - .metavar("FILE"); + .dest("output") + .help("Output ape binary") + .metavar("FILE"); optparse::Values options = parser.parse_args(argc, argv); vector<string> args = parser.args(); - if(!options.is_set("input")) + if (!options.is_set("input")) { cerr << "Please specify an input elf file to use." << endl; parser.print_help(); exit(-1); } - if(!options.is_set("output")) + if (!options.is_set("output")) { cerr << "Please specify an output binary to write." << endl; parser.print_help(); exit(-1); } - elfio reader; - - if(!reader.load(options["input"])) + + if (!reader.load(options["input"])) { - printf( "File %s is not found or it is not a valid ELF file\n", argv[1] ); + printf("File %s is not found or it is not a valid ELF file\n", argv[1]); return 1; } - // writer.set_os_abi( ELFOSABI_LINUX ); + // writer.set_os_abi( ELFOSABI_LINUX ); // writer.set_type( ET_EXEC ); // writer.set_machine( EM_ARM ); - // Ensure that this is the correct elf type. - if( reader.get_class() != ELFCLASS32 || + if (reader.get_class() != ELFCLASS32 || reader.get_encoding() != ELFDATA2LSB || - reader.get_machine() != EM_ARM || - reader.get_type() != ET_EXEC - ) + reader.get_machine() != EM_ARM || reader.get_type() != ET_EXEC) { - printf( "Only 32-bit little-endian arm binaries are supported\n"); + printf("Only 32-bit little-endian arm binaries are supported\n"); return 1; } // Determine number of output sections. Elf_Half seg_num = reader.segments.size(); - for ( int i = 0; i < seg_num; ++i ) + for (int i = 0; i < seg_num; ++i) { - const segment* pseg = reader.segments[i]; - for(int j = 0; j < pseg->get_sections_num(); j++) + const segment *pseg = reader.segments[i]; + for (int j = 0; j < pseg->get_sections_num(); j++) { Elf_Half idx = pseg->get_section_index_at(j); - section* psec = reader.sections[idx]; - if(psec->get_flags() & SHF_ALLOC) + section *psec = reader.sections[idx]; + if (psec->get_flags() & SHF_ALLOC) { numSections++; } } } - byteOffset = (sizeof(ape.header) + sizeof(APESection_t) * numSections); // Print ELF file segments info std::cout << "Number of segments: " << seg_num << std::endl; numSections = 0; - for ( int i = 0; i < seg_num; ++i ) + for (int i = 0; i < seg_num; ++i) { - const segment* pseg = reader.segments[i]; - std::cout << " [" << i << "] 0x" << std::hex - << pseg->get_flags() - << "\tVirt: 0x" - << pseg->get_virtual_address() - << "\tFileSize: 0x" - << pseg->get_file_size() - << "\tSize: 0x" - << pseg->get_memory_size() - << "\tFlags: 0x" - << pseg->get_flags() - << std::endl; - - for(int j = 0; j < pseg->get_sections_num(); j++) + const segment *pseg = reader.segments[i]; + std::cout << " [" << i << "] 0x" << std::hex << pseg->get_flags() + << "\tVirt: 0x" << pseg->get_virtual_address() + << "\tFileSize: 0x" << pseg->get_file_size() << "\tSize: 0x" + << pseg->get_memory_size() << "\tFlags: 0x" + << pseg->get_flags() << std::endl; + + for (int j = 0; j < pseg->get_sections_num(); j++) { Elf_Half idx = pseg->get_section_index_at(j); - section* psec = reader.sections[idx]; - if(psec->get_flags() & SHF_ALLOC) + section *psec = reader.sections[idx]; + if (psec->get_flags() & SHF_ALLOC) { - std::cout << " [" << j << "] " - << psec->get_name() - << "\t" - << psec->get_size() - << "\tType: 0x" - << psec->get_type() - << "\tFlags: 0x" - << psec->get_flags() - << "\tAddr: 0x" - << psec->get_address() - << std::endl; + std::cout << " [" << j << "] " << psec->get_name() << "\t" + << psec->get_size() << "\tType: 0x" + << psec->get_type() << "\tFlags: 0x" + << psec->get_flags() << "\tAddr: 0x" + << psec->get_address() << std::endl; APESection_t *section = &ape.header.section[numSections++]; section->flags = 0; section->offset = byteOffset; - const char* data = psec->get_data(); - if(data) + const char *data = psec->get_data(); + if (data) { - uint32_t compressedSize = compress((uint8_t*)&ape.bytes[byteOffset], psec->get_size() * 2, // Output, compressed - (const uint8_t*)data, psec->get_size()); // input, uncompressed + uint32_t compressedSize = + compress((uint8_t *)&ape.bytes[byteOffset], + psec->get_size() * 2, // Output, compressed + (const uint8_t *)data, + psec->get_size()); // input, uncompressed // ROund up to nearest word. compressedSize = ((compressedSize + 3) / 4) * 4; section->compressedSize = compressedSize; byteOffset += section->compressedSize; - // memcpy(&ape.bytes[byteOffset], compressed, section->compressedSize); - // byteOffset += section->compressedSize; - section->crc = NVRam_crc((const uint8_t*)data, psec->get_size(), 0); - section->flags |= APE_SECTION_FLAG_CHECKSUM_IS_CRC32 | APE_SECTION_FLAG_COMPRESSED; + // memcpy(&ape.bytes[byteOffset], compressed, + // section->compressedSize); byteOffset += + // section->compressedSize; + section->crc = + NVRam_crc((const uint8_t *)data, psec->get_size(), 0); + section->flags |= APE_SECTION_FLAG_CHECKSUM_IS_CRC32 | + APE_SECTION_FLAG_COMPRESSED; } else { @@ -266,12 +251,11 @@ int main(int argc, char const *argv[]) section->decompressedSize = psec->get_size(); section->loadAddr = psec->get_address(); - if(psec->get_flags() & SHF_EXECINSTR) + if (psec->get_flags() & SHF_EXECINSTR) { section->flags |= APE_SECTION_FLAG_CODE; } } - } } @@ -281,17 +265,18 @@ int main(int argc, char const *argv[]) ape.header.version = get_symbol_value("VERSION", reader); ape.header.entrypoint = get_symbol_value("__start", reader); ape.header.unk1 = APE_HEADER_UNK1; - ape.header.words = (sizeof(ape.header) + sizeof(APESection_t) * numSections) / 4; + ape.header.words = + (sizeof(ape.header) + sizeof(APESection_t) * numSections) / 4; ape.header.unk2 = APE_HEADER_UNK2; ape.header.sections = numSections; ape.header.crc = 0; /// - printf("Magic: 0x%08X\n", ape.header.magic); + printf("Magic: 0x%08X\n", ape.header.magic); printf("UNK0: 0x%08X\n", ape.header.unk0); char name[sizeof(ape.header.name) + 1] = {0}; - strncpy(name, (char*)ape.header.name, sizeof(ape.header.name)); + strncpy(name, (char *)ape.header.name, sizeof(ape.header.name)); printf("Name: %s\n", name); printf("Version: 0x%08X\n", ape.header.version); printf("Start: 0x%08X\n", ape.header.entrypoint); @@ -305,13 +290,10 @@ int main(int argc, char const *argv[]) // ... - - calculated_crc = NVRam_crc(ape.bytes, (4 * ape.header.words), 0); ape.header.crc = calculated_crc; printf("Calculated CRC: 0x%08X\n", calculated_crc); - save_to_file(options["output"].c_str(), ape.bytes, byteOffset); // fstream infile; @@ -330,13 +312,12 @@ int main(int argc, char const *argv[]) // } // else // { - // cerr << " Unable to open file '" << options["filename"] << "'" << endl; - // exit(-1); + // cerr << " Unable to open file '" << options["filename"] << "'" << + // endl; exit(-1); // } - // elfio writer; - + // // You can't proceed without this function call! // writer.create( ELFCLASS32, ELFDATA2LSB ); // writer.set_os_abi( ELFOSABI_LINUX ); @@ -380,8 +361,8 @@ int main(int argc, char const *argv[]) // printf("CRC: 0x%08X\n", ape.header.crc); // ape.header.crc = 0; - // uint32_t calculated_crc = NVRam_crc(ape.bytes, (4 * ape.header.words), 0); - // printf("Calculated CRC: 0x%08X\n", calculated_crc); + // uint32_t calculated_crc = NVRam_crc(ape.bytes, (4 * ape.header.words), + // 0); printf("Calculated CRC: 0x%08X\n", calculated_crc); // for(int i = 0; i < ape.header.sections; i++) // { @@ -406,8 +387,8 @@ int main(int argc, char const *argv[]) // { // printf(" crc32\n"); // } - // printf(" %s\n", section->flags & APE_SECTION_FLAG_CODE ? "code" : "data"); - // if(section->flags & APE_SECTION_FLAG_UNK0) + // printf(" %s\n", section->flags & APE_SECTION_FLAG_CODE ? "code" : + // "data"); if(section->flags & APE_SECTION_FLAG_UNK0) // { // printf(" unknown\n"); // } @@ -423,18 +404,20 @@ int main(int argc, char const *argv[]) // inBufferSize = section->compressedSize; // outBufferPtr = (uint8_t *)malloc(section->decompressedSize); // outBufferSize = section->decompressedSize; - // out_length = decompress(outBufferPtr, outBufferSize, inBufferPtr, inBufferSize); - // calculated_crc = NVRam_crc(outBufferPtr, outBufferSize, 0); - // printf("out_length: 0x%08zX\n", out_length); - // printf("out CRC: 0x%08X\n", calculated_crc); + // out_length = decompress(outBufferPtr, outBufferSize, inBufferPtr, + // inBufferSize); calculated_crc = NVRam_crc(outBufferPtr, + // outBufferSize, 0); printf("out_length: 0x%08zX\n", + // out_length); printf("out CRC: 0x%08X\n", + // calculated_crc); // uint8_t* compOut = (uint8_t*)malloc(out_length * 2); // int32_t compOutSize = out_length*2; - // int32_t recomp = compress(compOut, compOutSize, outBufferPtr, out_length); - // printf("recompressed length: 0x%08X\n", recomp); + // int32_t recomp = compress(compOut, compOutSize, outBufferPtr, + // out_length); printf("recompressed length: 0x%08X\n", + // recomp); - // out_length = decompress(outBufferPtr, outBufferSize, compOut, recomp); - // calculated_crc = NVRam_crc(outBufferPtr, outBufferSize, 0); + // out_length = decompress(outBufferPtr, outBufferSize, compOut, + // recomp); calculated_crc = NVRam_crc(outBufferPtr, outBufferSize, 0); // printf("out_length: 0x%08zX\n", out_length); // printf("try CRC: 0x%08X\n", calculated_crc); @@ -454,7 +437,8 @@ int main(int argc, char const *argv[]) // bss_seg->set_align( 0x4 ); // // Add data section into data segment - // bss_seg->add_section_index( bss_sec->get_index(), bss_sec->get_addr_align() ); + // bss_seg->add_section_index( bss_sec->get_index(), + // bss_sec->get_addr_align() ); // } // else if(!(section->flags & APE_SECTION_FLAG_CODE)) // { @@ -466,7 +450,8 @@ int main(int argc, char const *argv[]) // data_seg->set_align( 0x4 ); // // Add data section into data segment - // data_seg->add_section_index( data_sec->get_index(), data_sec->get_addr_align() ); + // data_seg->add_section_index( data_sec->get_index(), + // data_sec->get_addr_align() ); // } // else // { @@ -478,7 +463,8 @@ int main(int argc, char const *argv[]) // text_seg->set_align( 0x4 ); // // Add code section into program segment - // text_seg->add_section_index( text_sec->get_index(), text_sec->get_addr_align() ); + // text_seg->add_section_index( text_sec->get_index(), + // text_sec->get_addr_align() ); // } // } |
