diff options
author | Evan Lojewski <github@meklort.com> | 2019-02-23 13:28:15 -0700 |
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committer | Evan Lojewski <github@meklort.com> | 2019-02-23 13:28:15 -0700 |
commit | 7fe2ef3fb650247e4b8e4fed2294f564119f4b6b (patch) | |
tree | 2b561a63416ce322ceb03c6a824bb7a284c4424e /stage1/main.c | |
parent | d81fa4c17c6c815fa30120dc9ddf26e29f19821b (diff) | |
download | bcm5719-ortega-7fe2ef3fb650247e4b8e4fed2294f564119f4b6b.tar.gz bcm5719-ortega-7fe2ef3fb650247e4b8e4fed2294f564119f4b6b.zip |
Update stage1 code to latest implimentation. Zero out bss during early init.
Diffstat (limited to 'stage1/main.c')
-rw-r--r-- | stage1/main.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/stage1/main.c b/stage1/main.c index ed96e80..2870d91 100644 --- a/stage1/main.c +++ b/stage1/main.c @@ -59,6 +59,7 @@ NVRAMContents_t gNVMContents; int main() { + reportStatus(STATUS_MAIN, 0); uint32_t* bootcode_dest; #if CXX_SIMULATOR initHAL(NULL); @@ -72,17 +73,24 @@ int main() early_init_hw(); #endif + reportStatus(STATUS_MAIN, 1); // Read in the NVM header. NVRam_acquireLock(); + reportStatus(STATUS_MAIN, 2); + NVRam_enable(); NVRam_read(0, (uint32_t *)&gNVMContents, sizeof(NVRAMContents_t) / 4); + #if !CXX_SIMULATOR load_nvm_config(&gNVMContents); + // Initialize the hardware. init_hw(&gNVMContents); #endif + reportStatus(STATUS_MAIN, 3); + // Locate, verify, and execute stage2. uint32_t stage1_start = be32toh(gNVMContents.header.bootstrapOffset); uint32_t stage1_length = be32toh(gNVMContents.header.bootstrapWords) * 4; // including crc. @@ -94,6 +102,8 @@ int main() uint32_t stage2_length = be32toh(stage2_hdr.length); uint32_t stage2_magic = be32toh(stage2_hdr.magic); + reportStatus(STATUS_MAIN, 4); + if(BCM_NVRAM_MAGIC == stage2_magic) { // Magic matches. Attempt to load stage2. @@ -105,7 +115,7 @@ int main() if(expected_crc == calculated_crc) { - GEN.GenDataSig.r32 = GEN_GEN_DATA_SIG_SIG_BOOTCODE_READY; + reportStatus(GEN_GEN_DATA_SIG_SIG_BOOTCODE_READY, 0); #if CXX_SIMULATOR // TODO: exec stage2. printf("Stage1 completed successfully with status 0x%08X.\n", (uint32_t)GEN.GenDataSig.r32); @@ -120,13 +130,13 @@ int main() else { // Error. Invalid CRC. - GEN.GenDataSig.r32 = GEN_GEN_DATA_SIG_SIG_STAGE2_CRC_INVALID; + reportStatus(GEN_GEN_DATA_SIG_SIG_STAGE2_CRC_INVALID, 0); } } else { // Error. Invalid magic. - GEN.GenDataSig.r32 = GEN_GEN_DATA_SIG_SIG_STAGE2_MAGIC_INVALID; + reportStatus(GEN_GEN_DATA_SIG_SIG_STAGE2_MAGIC_INVALID, 0); } NVRam_releaseLock(); |