diff options
author | Evan Lojewski <github@meklort.com> | 2020-01-21 20:28:04 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-01-21 20:28:04 -0700 |
commit | afefcfeb9555c8dd496e25e6fb7bff447530fe6c (patch) | |
tree | d8cb110a6ace39bcaa31452d1ad6dc9fa17595d5 /libs | |
parent | 550345e5f6bb536770b5d712182eb6db73f83ea1 (diff) | |
download | bcm5719-ortega-afefcfeb9555c8dd496e25e6fb7bff447530fe6c.tar.gz bcm5719-ortega-afefcfeb9555c8dd496e25e6fb7bff447530fe6c.zip |
APE: Fix shm initialization and add additional error checking to the MII library. (#15)
Diffstat (limited to 'libs')
-rw-r--r-- | libs/MII/include/MII.h | 10 | ||||
-rw-r--r-- | libs/MII/mii.c | 120 | ||||
-rw-r--r-- | libs/NCSI/ncsi.c | 55 | ||||
-rw-r--r-- | libs/Network/include/Network.h | 2 | ||||
-rw-r--r-- | libs/Network/ports.c | 8 | ||||
-rw-r--r-- | libs/bcm5719/APE_sym.s | 4 | ||||
-rw-r--r-- | libs/printf/ape_putchar.c | 1 |
7 files changed, 124 insertions, 76 deletions
diff --git a/libs/MII/include/MII.h b/libs/MII/include/MII.h index f8405e5..c6f30d5 100644 --- a/libs/MII/include/MII.h +++ b/libs/MII/include/MII.h @@ -72,27 +72,27 @@ uint8_t MII_getPhy(volatile DEVICE_t* device); /** * @fn uint16_t MII_readRegister(uint8_t PHY, uint8_t reg); */ -uint16_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg); +int32_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg); /** * @fn void MII_writeRegister(uint8_t PHY, uint8_t reg, uint16_t data); */ -void MII_writeRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data); +bool MII_writeRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data); /** * @fn void MII_selectBlock(uint8_t phy, uint16_t block); */ -void MII_selectBlock(volatile DEVICE_t* device, uint8_t phy, uint16_t block); +bool MII_selectBlock(volatile DEVICE_t* device, uint8_t phy, uint16_t block); /** * @fn uint16_t MII_getBlock(uint8_t phy); */ -uint16_t MII_getBlock(volatile DEVICE_t* device, uint8_t phy); +int32_t MII_getBlock(volatile DEVICE_t* device, uint8_t phy); /** * @fn void MII_reset(uint8_t phy); */ -void MII_reset(volatile DEVICE_t* device, uint8_t phy); +bool MII_reset(volatile DEVICE_t* device, uint8_t phy); #ifdef CXX_SIMULATOR #undef volatile diff --git a/libs/MII/mii.c b/libs/MII/mii.c index b070fe6..5048fbe 100644 --- a/libs/MII/mii.c +++ b/libs/MII/mii.c @@ -52,16 +52,20 @@ #define volatile #endif -static void __attribute__((noinline)) MII_wait(volatile DEVICE_t* device) +static bool __attribute__((noinline)) MII_wait(volatile DEVICE_t *device) { + uint32_t maxWait = 0xffff; // Wait for the status bit to be clear. - while (device->MiiCommunication.bits.Start_DIV_Busy) + while (device->MiiCommunication.bits.Start_DIV_Busy && maxWait) { // Waiting... + maxWait--; } + + return maxWait ? true : false; } -uint8_t MII_getPhy(volatile DEVICE_t* device) +uint8_t MII_getPhy(volatile DEVICE_t *device) { if (device->SgmiiStatus.bits.MediaSelectionMode) { @@ -75,7 +79,7 @@ uint8_t MII_getPhy(volatile DEVICE_t* device) } } -static uint16_t MII_readRegisterInternal(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg) +static int32_t MII_readRegisterInternal(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg) { union { @@ -92,18 +96,26 @@ static uint16_t MII_readRegisterInternal(volatile DEVICE_t* device, uint8_t phy, regcontents.bits.RegisterAddress = caster.addr; // Ensure there are no active transactions - MII_wait(device); + if (!MII_wait(device)) + { + // Unable to read + return -1; + } // Start the transaction device->MiiCommunication = regcontents; // Wait for transaction to complete. - MII_wait(device); + if (!MII_wait(device)) + { + // Unable to read + return -1; + } return device->MiiCommunication.bits.TransactionData; } -static void MII_writeRegisterInternal(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data) +static bool MII_writeRegisterInternal(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg, uint16_t data) { RegDEVICEMiiCommunication_t regcontents; regcontents.r32 = 0; @@ -114,16 +126,26 @@ static void MII_writeRegisterInternal(volatile DEVICE_t* device, uint8_t phy, mi regcontents.bits.TransactionData = data; // Ensure there are no active transactions - MII_wait(device); + if (!MII_wait(device)) + { + // Unable to read + return false; + } // Start the transaction device->MiiCommunication = regcontents; // Wait for transaction to complete (not strictly required for writes). - MII_wait(device); + if (!MII_wait(device)) + { + // Unable to read + return false; + } + + return true; } -static uint16_t MII_readShadowRegister18(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg) +static int32_t MII_readShadowRegister18(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg) { // Write register 18h, bits [2:0] = 111 This selects the Miscellaneous // Control register, shadow 7h. All reads must be performed through the @@ -146,12 +168,17 @@ static uint16_t MII_readShadowRegister18(volatile DEVICE_t* device, uint8_t phy, shadow_select.r16 = 0; shadow_select.bits.ShadowRegisterReadSelector = shadow_reg; shadow_select.bits.ShadowRegisterSelector = 7; - MII_writeRegisterInternal(device, phy, (mii_reg_t)0x18, shadow_select.r16); - - return MII_readRegisterInternal(device, phy, (mii_reg_t)0x18); + if(MII_writeRegisterInternal(device, phy, (mii_reg_t)0x18, shadow_select.r16)) + { + return MII_readRegisterInternal(device, phy, (mii_reg_t)0x18); + } + else + { + return -1; + } } -static uint16_t MII_readShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg) +static int32_t MII_readShadowRegister1C(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg) { // -------------------------------------------- // PHY 0x1C Shadow 0x1 register read Procedure @@ -170,7 +197,7 @@ static uint16_t MII_readShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, return MII_readRegisterInternal(device, phy, (mii_reg_t)0x1C); } -uint16_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg) +int32_t MII_readRegister(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg) { if ((reg & 0xFF) == 0x1C) { @@ -186,7 +213,7 @@ uint16_t MII_readRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg) } } -static void MII_writeShadowRegister18(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data) +static bool MII_writeShadowRegister18(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg, uint16_t data) { // Set Bits [15:3] = Preferred write values Bits [15:3] contain the desired // bits to be written to. Set Bits [2:0] = yyy This enables shadow register @@ -204,15 +231,19 @@ static void MII_writeShadowRegister18(volatile DEVICE_t* device, uint8_t phy, mi shadow_select.r16 = 0; shadow_select.bits.ShadowRegisterReadSelector = shadow_reg; shadow_select.bits.ShadowRegisterSelector = 7; - MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, shadow_select.r16); + if(MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, shadow_select.r16)) + { + RegMIIMiscellaneousControl_t write_data; + write_data.r16 = data; + write_data.bits.ShadowRegisterSelector = shadow_reg; + + return MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, write_data.r16); + } - RegMIIMiscellaneousControl_t write_data; - write_data.r16 = data; - write_data.bits.ShadowRegisterSelector = shadow_reg; - MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_AUXILIARY_CONTROL, write_data.r16); + return false; } -static void MII_writeShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data) +static bool MII_writeShadowRegister1C(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg, uint16_t data) { // -------------------------------------------- // PHY 0x1C Shadow 0x2 register write Procedure @@ -225,51 +256,58 @@ static void MII_writeShadowRegister1C(volatile DEVICE_t* device, uint8_t phy, mi RegMIICabletronLed_t shadow_select; shadow_select.r16 = 0; shadow_select.bits.ShadowRegisterSelector = shadow_reg; - MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, shadow_select.r16); + if(MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, shadow_select.r16)) + { + RegMIICabletronLed_t write_data; + write_data.r16 = data; + write_data.bits.ShadowRegisterSelector = shadow_reg; + write_data.bits.WriteEnable = 1; - RegMIICabletronLed_t write_data; - write_data.r16 = data; - write_data.bits.ShadowRegisterSelector = shadow_reg; - write_data.bits.WriteEnable = 1; + return MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, write_data.r16); + } - MII_writeRegisterInternal(device, phy, (mii_reg_t)REG_MII_CABLETRON_LED, write_data.r16); + return false; } -void MII_writeRegister(volatile DEVICE_t* device, uint8_t phy, mii_reg_t reg, uint16_t data) +bool MII_writeRegister(volatile DEVICE_t *device, uint8_t phy, mii_reg_t reg, uint16_t data) { if ((reg & 0xFF) == 0x1C) { - MII_writeShadowRegister1C(device, phy, reg, data); + return MII_writeShadowRegister1C(device, phy, reg, data); } else if ((reg & 0xFF) == 0x18) { - MII_writeShadowRegister18(device, phy, reg, data); + return MII_writeShadowRegister18(device, phy, reg, data); } else { - MII_writeRegisterInternal(device, phy, reg, data); + return MII_writeRegisterInternal(device, phy, reg, data); } } -void MII_selectBlock(volatile DEVICE_t* device, uint8_t phy, uint16_t block) +bool MII_selectBlock(volatile DEVICE_t *device, uint8_t phy, uint16_t block) { // Write register 0x1f with the block. - MII_writeRegister(device, phy, (mii_reg_t)REG_MII_BLOCK_SELECT, block); + return MII_writeRegister(device, phy, (mii_reg_t)REG_MII_BLOCK_SELECT, block); } -uint16_t MII_getBlock(volatile DEVICE_t* device, uint8_t phy) +int32_t MII_getBlock(volatile DEVICE_t *device, uint8_t phy) { // Write register 0x1f with the block. return MII_readRegister(device, phy, (mii_reg_t)REG_MII_BLOCK_SELECT); } -void MII_reset(volatile DEVICE_t* device, uint8_t phy) +bool MII_reset(volatile DEVICE_t *device, uint8_t phy) { // Set MII_REG_CONTROL to RESET; wait until RESET bit clears. - MII_writeRegister(device, phy, (mii_reg_t)REG_MII_CONTROL, MII_CONTROL_RESET_MASK); - - do + if(MII_writeRegister(device, phy, (mii_reg_t)REG_MII_CONTROL, MII_CONTROL_RESET_MASK)) { - // Spin - } while ((MII_readRegister(device, phy, (mii_reg_t)REG_MII_CONTROL) & MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK); + do + { + // Spin + } while ((MII_readRegister(device, phy, (mii_reg_t)REG_MII_CONTROL) & MII_CONTROL_RESET_MASK) == MII_CONTROL_RESET_MASK); + + return true; + } + return false; } diff --git a/libs/NCSI/ncsi.c b/libs/NCSI/ncsi.c index 2b5e2e8..e0f2113 100644 --- a/libs/NCSI/ncsi.c +++ b/libs/NCSI/ncsi.c @@ -287,7 +287,7 @@ static void clearInitialStateHandler(NetworkFrame_t *frame) { int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; - gPackageState.port[ch]->shm->NcsiChannelInfo.bits.Ready = true; + gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.Ready = true; debug("Clear initial state: channel %x\n", ch); sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, @@ -315,7 +315,7 @@ static void enableChannelHandler(NetworkFrame_t *frame) int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; debug("Enable Channel: %x\n", ch); - gPackageState.port[ch]->shm->NcsiChannelInfo.bits.Enabled = true; + gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.Enabled = true; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -326,7 +326,7 @@ static void disableChannelHandler(NetworkFrame_t *frame) int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; debug("Disable Channel: %x\n", ch); - gPackageState.port[ch]->shm->NcsiChannelInfo.bits.Enabled = false; + gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.Enabled = false; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -348,7 +348,7 @@ static void enableChannelNetworkTXHandler(NetworkFrame_t *frame) int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; debug("Enable Channel Network TX: channel %x\n", ch); - gPackageState.port[ch]->shm->NcsiChannelInfo.bits.TXPassthrough = true; + gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.TXPassthrough = true; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -359,7 +359,7 @@ static void disableChannelNetworkTXHandler(NetworkFrame_t *frame) int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; debug("Disable Channel Network TX: %x\n", ch); - gPackageState.port[ch]->shm->NcsiChannelInfo.bits.TXPassthrough = false; + gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.TXPassthrough = false; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -372,8 +372,8 @@ static void AENEnableHandler(NetworkFrame_t *frame) debug("AEN Enable: AEN_MC_ID %x\n", frame->AENEnable.AEN_MC_ID); debug("AEN Enable: AENControl %x\n", AENControl); - gPackageState.port[ch]->shm->NcsiChannelMcid.r32 = frame->AENEnable.AEN_MC_ID; - gPackageState.port[ch]->shm->NcsiChannelMcid.r32 = AENControl; + gPackageState.port[ch]->shm_channel->NcsiChannelMcid.r32 = frame->AENEnable.AEN_MC_ID; + gPackageState.port[ch]->shm_channel->NcsiChannelMcid.r32 = AENControl; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -388,8 +388,8 @@ static void setLinkHandler(NetworkFrame_t *frame) int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; NetworkPort_t *port = gPackageState.port[ch]; - port->shm->NcsiChannelSetting1.r32 = LinkSettings; - port->shm->NcsiChannelSetting2.r32 = OEMLinkSettings; + port->shm_channel->NcsiChannelSetting1.r32 = LinkSettings; + port->shm_channel->NcsiChannelSetting2.r32 = OEMLinkSettings; sendNCSIResponse(frame->controlPacket.InstanceID, frame->controlPacket.ChannelID, frame->controlPacket.ControlPacketType, NCSI_RESPONSE_CODE_COMMAND_COMPLETE, NCSI_REASON_CODE_NONE); @@ -432,7 +432,7 @@ static void getLinkStatusHandler(NetworkFrame_t *frame) linkStatus.bits.LinkSpeed10M_TFullDuplexCapable = stat.bits._10BASE_TFullDuplexCapable; linkStatus.bits.LinkSpeed10M_THalfDuplexCapable = stat.bits._10BASE_THalfDuplexCapable; - port->shm->NcsiChannelStatus = linkStatus; + port->shm_channel->NcsiChannelStatus = linkStatus; uint32_t LinkStatus = linkStatus.r32; uint32_t OEMLinkStatus = 0; @@ -447,7 +447,7 @@ static void disableVLANHandler(NetworkFrame_t *frame) // TODO int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; NetworkPort_t *port = gPackageState.port[ch]; - port->shm->NcsiChannelInfo.bits.VLAN = false; + port->shm_channel->NcsiChannelInfo.bits.VLAN = false; debug("Disable VLAN: channel %x\n", ch); @@ -497,7 +497,7 @@ static void enableVLANHandler(NetworkFrame_t *frame) // TODO int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; NetworkPort_t *port = gPackageState.port[ch]; - port->shm->NcsiChannelInfo.bits.VLAN = false; + port->shm_channel->NcsiChannelInfo.bits.VLAN = false; debug("Enable VLAN: channel %x\n", ch); @@ -510,7 +510,7 @@ static void setVLANFilter(NetworkFrame_t *frame) // TODO int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; NetworkPort_t *port = gPackageState.port[ch]; - port->shm->NcsiChannelInfo.bits.VLAN = false; + port->shm_channel->NcsiChannelInfo.bits.VLAN = false; debug("Set VLAN Filter: channel %x\n", ch); @@ -523,7 +523,7 @@ static void setMACAddressHandler(NetworkFrame_t *frame) { int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; NetworkPort_t *port = gPackageState.port[ch]; - // port->shm->NcsiChannelInfo.bits.Enabled = false; + // port->shm_channel->NcsiChannelInfo.bits.Enabled = false; debug("Set MAC: channel %x\n", ch); debug(" MAC: 0x%04x%04x%04x\n", frame->setMACAddr.MAC54, frame->setMACAddr.MAC32, frame->setMACAddr.MAC10); @@ -544,7 +544,7 @@ static void enableBroadcastFilteringHandler(NetworkFrame_t *frame) { // TODO // channel_state_t* channel = gPackageState.port[ch]; - // port->shm->NcsiChannelInfo.bits.Enabled = false; + // port->shm_channel->NcsiChannelInfo.bits.Enabled = false; int ch = frame->controlPacket.ChannelID & CHANNEL_ID_MASK; debug("Enable Broadcast Filtering: channel %x\n", ch); @@ -593,7 +593,7 @@ void handleNCSIFrame(NetworkFrame_t *frame) uint8_t package = frame->controlPacket.ChannelID >> PACKAGE_ID_SHIFT; if(package != 0) { - debug("Ignoring command to package %d\n", package); + // debug("Ignoring command to package %d\n", package); // Ignore - not us. return; @@ -623,7 +623,7 @@ void handleNCSIFrame(NetworkFrame_t *frame) if (port) { - ++port->shm->NcsiChannelCtrlstatRx.r32; + ++port->shm_channel->NcsiChannelCtrlstatRx.r32; } gPackageState.selected = true; SHM.SegSig.r32 |= (1 << command); @@ -642,7 +642,7 @@ void handleNCSIFrame(NetworkFrame_t *frame) else { gPackageState.selected = true; - if (false == gPackageState.port[ch]->shm->NcsiChannelInfo.bits.Ready) + if (false == gPackageState.port[ch]->shm_channel->NcsiChannelInfo.bits.Ready) { debug("[%x] Channel not initialized: %d\n", command, ch); // Initialization required for the channel @@ -653,7 +653,7 @@ void handleNCSIFrame(NetworkFrame_t *frame) { if (port) { - ++port->shm->NcsiChannelCtrlstatRx.r32; + ++port->shm_channel->NcsiChannelCtrlstatRx.r32; } SHM.SegSig.r32 |= (1 << command); handler->fn(frame); @@ -675,15 +675,14 @@ void resetChannel(int ch) { NetworkPort_t *port = gPackageState.port[ch]; - port->shm->NcsiChannelInfo.r32 = 0; - port->shm->NcsiChannelCtrlstatRx.r32 = 0; - port->shm->NcsiChannelInfo.bits.Ready = false; + port->shm_channel->NcsiChannelInfo.r32 = 0; + port->shm_channel->NcsiChannelCtrlstatRx.r32 = 0; + port->shm_channel->NcsiChannelCtrlstatAllTx.r32 = 0; + port->shm_channel->NcsiChannelInfo.bits.Ready = false; + uint8_t phy = MII_getPhy(port->device); APE_aquireLock(); - uint8_t phy = DEVICE_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 + ch; - MII_writeRegister(port->device, phy, (mii_reg_t)0, 0x8000); - - + MII_writeRegister(port->device, phy, (mii_reg_t)REG_MII_CONTROL, MII_CONTROL_RESET_MASK); APE_releaseLock(); } @@ -765,10 +764,10 @@ void NCSI_handlePassthrough(void) for (int ch = 0; ch < ARRAY_ELEMENTS(gPackageState.port); ch++) { NetworkPort_t *port = gPackageState.port[ch]; - if (port->shm->NcsiChannelInfo.bits.Ready) + if (port->shm_channel->NcsiChannelInfo.bits.Ready) { Network_PassthroughRxPatcket(port); - ++port->shm->NcsiChannelCtrlstatAllTx.r32; + ++port->shm_channel->NcsiChannelCtrlstatAllTx.r32; } } } diff --git a/libs/Network/include/Network.h b/libs/Network/include/Network.h index b806c30..ac26f05 100644 --- a/libs/Network/include/Network.h +++ b/libs/Network/include/Network.h @@ -77,7 +77,7 @@ typedef struct /* Port Registers */ VOLATILE DEVICE_t *device; VOLATILE FILTERS_t *filters; - VOLATILE SHM_CHANNEL_t* shm; + VOLATILE SHM_CHANNEL_t* shm_channel; } NetworkPort_t; typedef union diff --git a/libs/Network/ports.c b/libs/Network/ports.c index a90f779..1711c55 100644 --- a/libs/Network/ports.c +++ b/libs/Network/ports.c @@ -51,6 +51,10 @@ #include <APE_RX_PORT1.h> #include <APE_RX_PORT2.h> #include <APE_RX_PORT3.h> +#include <APE_SHM_CHANNEL0.h> +#include <APE_SHM_CHANNEL1.h> +#include <APE_SHM_CHANNEL2.h> +#include <APE_SHM_CHANNEL3.h> #include <APE_TX_PORT1.h> #include <APE_TX_PORT2.h> #include <APE_TX_PORT3.h> @@ -59,6 +63,7 @@ NetworkPort_t gPort0 = { .device = &DEVICE, .filters = &FILTERS0, + .shm_channel = &SHM_CHANNEL0, .tx_port = &TX_PORT0, .tx_allocator = &APE.TxToNetBufferAllocator0, @@ -74,6 +79,7 @@ NetworkPort_t gPort0 = { NetworkPort_t gPort1 = { .device = &DEVICE1, .filters = &FILTERS1, + .shm_channel = &SHM_CHANNEL1, .tx_port = &TX_PORT1, .tx_allocator = &APE.TxToNetBufferAllocator1, @@ -89,6 +95,7 @@ NetworkPort_t gPort1 = { NetworkPort_t gPort2 = { .device = &DEVICE2, .filters = &FILTERS2, + .shm_channel = &SHM_CHANNEL2, .tx_port = &TX_PORT2, .tx_allocator = &APE.TxToNetBufferAllocator2, @@ -104,6 +111,7 @@ NetworkPort_t gPort2 = { NetworkPort_t gPort3 = { .device = &DEVICE3, .filters = &FILTERS3, + .shm_channel = &SHM_CHANNEL3, .tx_port = &TX_PORT3, .tx_allocator = &APE.TxToNetBufferAllocator3, diff --git a/libs/bcm5719/APE_sym.s b/libs/bcm5719/APE_sym.s index 37e1116..a7bdf87 100644 --- a/libs/bcm5719/APE_sym.s +++ b/libs/bcm5719/APE_sym.s @@ -146,6 +146,10 @@ .equ DEBUG, 0x60221000 .size DEBUG, 0x1000 +.global SHM1 +.equ SHM1, 0x60221000 +.size SHM1, 0x894 + .global SHM2 .equ SHM2, 0x60222000 .size SHM2, 0x894 diff --git a/libs/printf/ape_putchar.c b/libs/printf/ape_putchar.c index 5aaac54..550222e 100644 --- a/libs/printf/ape_putchar.c +++ b/libs/printf/ape_putchar.c @@ -45,7 +45,6 @@ #include <printf.h> #include <em100_putchar.h> #include <APE_DEBUG.h> -#include <APE_SHM.h> void _putchar(char character) { |