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| author | Evan Lojewski <github@meklort.com> | 2019-03-23 12:57:47 -0600 |
|---|---|---|
| committer | Evan Lojewski <github@meklort.com> | 2019-03-23 12:57:47 -0600 |
| commit | e78e8436e5fa637b02735e60aaf5b93d3f7bb9ba (patch) | |
| tree | 3ac24a545b42caadb4c06cfbab391d27267a2ccf /ipxact | |
| parent | a54811c57833655e1bd74370501669d1454c8cc6 (diff) | |
| download | bcm5719-ortega-e78e8436e5fa637b02735e60aaf5b93d3f7bb9ba.tar.gz bcm5719-ortega-e78e8436e5fa637b02735e60aaf5b93d3f7bb9ba.zip | |
Start adding in APE register generation.
Diffstat (limited to 'ipxact')
| -rw-r--r-- | ipxact/APE.xml | 943 | ||||
| -rw-r--r-- | ipxact/NVIC.xml | 949 | ||||
| -rw-r--r-- | ipxact/bcm5719.xml | 4 | ||||
| -rwxr-xr-x | ipxact/regen.sh | 15 |
4 files changed, 982 insertions, 929 deletions
diff --git a/ipxact/APE.xml b/ipxact/APE.xml index 90b12fe..5129f61 100644 --- a/ipxact/APE.xml +++ b/ipxact/APE.xml @@ -5,7 +5,7 @@ <ipxact:name>Register Definitions</ipxact:name> <ipxact:version>1.0</ipxact:version> <ipxact:memoryMaps> - <!-- General Communication: 0xB50 to 0xFFF --> + <!-- Nested Vectored Interrupt Controller: 0xE000_E000 --> <ipxact:memoryMap> <ipxact:name>NVIC</ipxact:name> <ipxact:description>Nested Vectored Interrupt Controller</ipxact:description> @@ -17,933 +17,24 @@ <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> <ipxact:usage>register</ipxact:usage> <ipxact:volatile>false</ipxact:volatile> - <ipxact:register> - <ipxact:name>Interrupt Control Type</ipxact:name> - <ipxact:description>Read the Interrupt Controller Type Register to see the number of interrupt lines that the NVIC supports.</ipxact:description> - <ipxact:addressOffset>0x4</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>INTLINESNUM</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>0 to 32</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>33 to 64</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>65 to 96</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>SysTick Control and Status</ipxact:name> - <ipxact:description>Use the SysTick Control and Status Register to enable the SysTick features.</ipxact:description> - <ipxact:addressOffset>0x10</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>ENABLE</ipxact:name> - <ipxact:description>It set, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TICKINT</ipxact:name> - <ipxact:description>If set, counting down to 0 pends the SysTick handler.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>CLKSOURCE</ipxact:name> - <ipxact:description>If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>COUNTFLAG</ipxact:name> - <ipxact:description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>SysTick Reload Value</ipxact:name> - <ipxact:description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0.</ipxact:description> - <ipxact:addressOffset>0x14</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>RELOAD</ipxact:name> - <ipxact:description>Value to load into the SysTick Current Value Register when the counter reaches 0.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>24</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>SysTick Current Value</ipxact:name> - <ipxact:description>Use the SysTick Current Value Register to find the current value in the register.</ipxact:description> - <ipxact:addressOffset>0x18</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>CURRENT</ipxact:name> - <ipxact:description>Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>24</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>SysTick Calibration Value</ipxact:name> - <ipxact:description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</ipxact:description> - <ipxact:addressOffset>0x1c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>TENMS</ipxact:name> - <ipxact:description>This value is the Reload value to use for 10ms timing. Depending on the value of SKEW, this might be exactly 10ms or might be the closest value. If this reads as 0, then the calibration value is not known. This is probably because the reference clock is an unknown input from the system or scalable dynamically.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>24</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SKEW</ipxact:name> - <ipxact:description>1 = the calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.</ipxact:description> - <ipxact:bitOffset>30</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>NOREF</ipxact:name> - <ipxact:description>1 = the reference clock is not provided.</ipxact:description> - <ipxact:bitOffset>31</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Set-Enable</ipxact:name> - <ipxact:description>Each bit in the register corresponds to one of 32 interrupts. Setting a bit in the Interrupt Set-Enable Register enables the corresponding interrupt. When the enable bit of a pending interrupt is set, the processor activates the interrupt based on its priority. When the enable bit is clear, asserting its interrupt signal pends the interrupt, but it is not possible to activate the interrupt, regardless of its priority. Therefore, a disabled interrupt can serve as a latched general-purpose I/O bit. You can read it and clear it without invoking an interrupt.</ipxact:description> - <ipxact:addressOffset>0x100</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>SETENA</ipxact:name> - <ipxact:description>Writing 0 to a SETENA bit has no effect. Reading the bit returns its current enable state. Reset clears the SETENA fields.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Clear-Enable</ipxact:name> - <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Enable Register bit disables the corresponding interrupt.</ipxact:description> - <ipxact:addressOffset>0x180</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>CLRENA</ipxact:name> - <ipxact:description>Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Set-Pending</ipxact:name> - <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Set-Pending Register bit pends the corresponding interrupt.</ipxact:description> - <ipxact:addressOffset>0x200</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>SETPEND</ipxact:name> - <ipxact:description>Writing 0 to a SETPEND bit has no effect. Reading the bit returns its current state.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Clear-Pending</ipxact:name> - <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state.</ipxact:description> - <ipxact:addressOffset>0x280</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>CLRPEND</ipxact:name> - <ipxact:description>Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Active Bit</ipxact:name> - <ipxact:description>Read the Active Bit Register to determine which interrupts are active. Each flag in the register corresponds to one of the 32 interrupts.</ipxact:description> - <ipxact:addressOffset>0x300</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>ACTIVE</ipxact:name> - <ipxact:description>Interrupt active flags.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Priority 0</ipxact:name> - <ipxact:description>Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest.</ipxact:description> - <ipxact:addressOffset>0x400</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>PRI_0</ipxact:name> - <ipxact:description>Priority of Interrupt 0.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_1</ipxact:name> - <ipxact:description>Priority of Interrupt 1.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_2</ipxact:name> - <ipxact:description>Priority of Interrupt 2.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_3</ipxact:name> - <ipxact:description>Priority of Interrupt 3.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Priority 1</ipxact:name> - <ipxact:description>Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest.</ipxact:description> - <ipxact:addressOffset>0x404</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>PRI_4</ipxact:name> - <ipxact:description>Priority of Interrupt 4.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_5</ipxact:name> - <ipxact:description>Priority of Interrupt 5.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_6</ipxact:name> - <ipxact:description>Priority of Interrupt 6.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_7</ipxact:name> - <ipxact:description>Priority of Interrupt 7.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>CPU ID</ipxact:name> - <ipxact:description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</ipxact:description> - <ipxact:addressOffset>0xd00</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>REVISION</ipxact:name> - <ipxact:description>Implementation defined revision number.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PARTNO</ipxact:name> - <ipxact:description>Reads as 0xF</ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Constant</ipxact:name> - <ipxact:description>Priority of Interrupt 6.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VARIANT</ipxact:name> - <ipxact:description>Implementation defined variant number.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>IMPLEMENTER</ipxact:name> - <ipxact:description>Implementer code. ARM is 0x41.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Interrupt Control State</ipxact:name> - <ipxact:description>Use the Interrupt Control State Register to: set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</ipxact:description> - <ipxact:addressOffset>0xd04</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>VECTACTIVE</ipxact:name> - <ipxact:description>Active ISR number field. VECTACTIVE contains the interrupt number of the currently running ISR, including NMI and Hard Fault. A shared handler can use VECTACTIVE to determine which interrupt invoked it. You can subtract 16 from the VECTACTIVE field to index into the Interrupt Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority Registers. INTISR[0] has vector number 16.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>9</ipxact:bitWidth> - <ipxact:access>read-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>RETTOBASE</ipxact:name> - <ipxact:description>This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.</ipxact:description> - <ipxact:bitOffset>11</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VECTPENDING</ipxact:name> - <ipxact:description>Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.</ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>10</ipxact:bitWidth> - <ipxact:access>read-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>ISRPENDING</ipxact:name> - <ipxact:description>Interrupt pending flag. Excludes NMI and Faults.</ipxact:description> - <ipxact:bitOffset>22</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>ISRPREEMPT</ipxact:name> - <ipxact:description>You must only use this at debug time. It indicates that a pending interrupt becomes active in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</ipxact:description> - <ipxact:bitOffset>22</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PENDSTCLR</ipxact:name> - <ipxact:description>Clear pending SysTick bit.</ipxact:description> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>write-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PENDSTSET</ipxact:name> - <ipxact:description>Set a pending SysTick bit.</ipxact:description> - <ipxact:bitOffset>26</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PENDSVCLR</ipxact:name> - <ipxact:description>Clear pending pendSV bit.</ipxact:description> - <ipxact:bitOffset>27</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>write-Only</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PENDSVSET</ipxact:name> - <ipxact:description>Set pending pendSV bit.</ipxact:description> - <ipxact:bitOffset>28</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>NMIPENDSET</ipxact:name> - <ipxact:description>NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.</ipxact:description> - <ipxact:bitOffset>31</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Vector Table Offset</ipxact:name> - <ipxact:description>Use the Vector Table Offset Register to determine: if the vector table is in RAM or code memory, the vector table offset.</ipxact:description> - <ipxact:addressOffset>0xd08</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>TBLOFF</ipxact:name> - <ipxact:description>Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.</ipxact:description> - <ipxact:bitOffset>7</ipxact:bitOffset> - <ipxact:bitWidth>22</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TBLBASE</ipxact:name> - <ipxact:description>Table base is in Code (0) or RAM (1).</ipxact:description> - <ipxact:bitOffset>29</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Application Interrupt and Reset Control</ipxact:name> - <ipxact:description>the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).</ipxact:description> - <ipxact:addressOffset>0xd0c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>VECTRESET</ipxact:name> - <ipxact:description>System Reset bit. Resets the system, with the exception of debug components.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VECTCLRACTIVE</ipxact:name> - <ipxact:description>Clear active vector bit.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SYSRESETREQ</ipxact:name> - <ipxact:description>Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRIGROUP</ipxact:name> - <ipxact:description>PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>3</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>ENDIANESS</ipxact:name> - <ipxact:description>Data endianness bit: 1 = big endian.</ipxact:description> - <ipxact:bitOffset>15</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VECTKEY</ipxact:name> - <ipxact:description>Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored. Reads as 0xFA05.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>System Control</ipxact:name> - <ipxact:description>Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</ipxact:description> - <ipxact:addressOffset>0xd10</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>SLEEPONEXIT</ipxact:name> - <ipxact:description>Sleep on exit when returning from Handler mode to Thread mode: 1 = sleep on ISR exit.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SLEEPDEEP</ipxact:name> - <ipxact:description>1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SEVONPEND</ipxact:name> - <ipxact:description>When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.</ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Configuration Control</ipxact:name> - <ipxact:description>Use the Configuration Control Register to: enable NMI, Hard Fault and FAULTMASK to ignore bus fault, trap divide by zero, and unaligned accesses, enable user access to the Software Trigger Exception Register, control entry to Thread Mode.</ipxact:description> - <ipxact:addressOffset>0xd14</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>NONEBASETHRDENA</ipxact:name> - <ipxact:description>When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>USERSETMPEND</ipxact:name> - <ipxact:description>If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>UNALIGN_TRP</ipxact:name> - <ipxact:description>Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED, see Usage Fault Status Register.</ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DIV_0_TRP</ipxact:name> - <ipxact:description>Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register.</ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BFHFNMIGN</ipxact:name> - <ipxact:description>When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored – you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>STKALIGN</ipxact:name> - <ipxact:description>1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.</ipxact:description> - <ipxact:bitOffset>9</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>System Handler Priority 4</ipxact:name> - <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> - <ipxact:addressOffset>0xd18</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>PRI_4</ipxact:name> - <ipxact:description>Priority of Mem Manage.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_5</ipxact:name> - <ipxact:description>Priority of Bus Fault.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_6</ipxact:name> - <ipxact:description>Priority of Usage Fault.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_7</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>System Handler Priority 8</ipxact:name> - <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> - <ipxact:addressOffset>0xd1c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>PRI_8</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_9</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_10</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_11</ipxact:name> - <ipxact:description>Priority of SVCall.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>System Handler Priority 12</ipxact:name> - <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> - <ipxact:addressOffset>0xd20</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>PRI_12</ipxact:name> - <ipxact:description>Priority of Debug Monitor.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_13</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_14</ipxact:name> - <ipxact:description>Priority of PendSV.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PRI_15</ipxact:name> - <ipxact:description>Priority of SysTick.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>System Handler Control and State</ipxact:name> - <ipxact:description>Use the System Handler Control and State Register to: enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers.</ipxact:description> - <ipxact:addressOffset>0xd24</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>MEMFAULTACT</ipxact:name> - <ipxact:description>Reads as 1 if MemManage is active.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BUSFAULTACT</ipxact:name> - <ipxact:description>Reads as 1 if BusFault is active.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>USGFAULTACT</ipxact:name> - <ipxact:description>Reads as 1 if UsageFault is active.</ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SVCALLACT</ipxact:name> - <ipxact:description>Reads as 1 if SVCall is active.</ipxact:description> - <ipxact:bitOffset>7</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>MONITORACT</ipxact:name> - <ipxact:description>Reads as 1 if the Monitor is active.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PENDSVACT</ipxact:name> - <ipxact:description>Reads as 1 if PendSV is active.</ipxact:description> - <ipxact:bitOffset>10</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SYSTICKACT</ipxact:name> - <ipxact:description>Reads as 1 if SysTick is active.</ipxact:description> - <ipxact:bitOffset>11</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>USGFAULTPENDED</ipxact:name> - <ipxact:description>Read as 1 if usage fault is pended.</ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>MEMFAULTPENDED</ipxact:name> - <ipxact:description>Reads as 1 if MemManage is pended.</ipxact:description> - <ipxact:bitOffset>13</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BUSFAULTPENDED</ipxact:name> - <ipxact:description>Reads as 1 if BusFault is pended.</ipxact:description> - <ipxact:bitOffset>14</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SVCALLPENDED</ipxact:name> - <ipxact:description>Reads as 1 if SVCall is pended.</ipxact:description> - <ipxact:bitOffset>15</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>MEMFAULTENA</ipxact:name> - <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BUSFAULTENA</ipxact:name> - <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> - <ipxact:bitOffset>17</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>USGFAULTENA</ipxact:name> - <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> - <ipxact:bitOffset>18</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Fault Status</ipxact:name> - <ipxact:description>The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.</ipxact:description> - <ipxact:addressOffset>0xd28</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Memory Manage Fault Status</ipxact:name> - <ipxact:description>The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Bus Fault Status</ipxact:name> - <ipxact:description>The flags in the Bus Fault Status Register indicate the cause of bus access faults.</ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Usage Fault Status</ipxact:name> - <ipxact:description>The flags in the Bus Fault Status Register indicate the cause of usage faults.</ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reserved</ipxact:name> - <ipxact:description>Reserved.</ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Hard Fault Status</ipxact:name> - <ipxact:description>Use the Hard Fault Status Register (HFSR) to obtain information about events that activate the Hard Fault handler.</ipxact:description> - <ipxact:addressOffset>0xd2c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>VECTTBL</ipxact:name> - <ipxact:description>This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>FORCED</ipxact:name> - <ipxact:description>Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.</ipxact:description> - <ipxact:bitOffset>30</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DEBUGEVT</ipxact:name> - <ipxact:description>This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.</ipxact:description> - <ipxact:bitOffset>31</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Debug Fault Status</ipxact:name> - <ipxact:description>Use the Debug Fault Status Register to monitor: external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests.</ipxact:description> - <ipxact:addressOffset>0xd30</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>HALTED</ipxact:name> - <ipxact:description>1 = halt requested by NVIC, including step. The processor is halted on the next instruction.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BKPT</ipxact:name> - <ipxact:description>The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DWTTRAP</ipxact:name> - <ipxact:description>Data Watchpoint and Trace (DWT) flag.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VCATCH</ipxact:name> - <ipxact:description>Vector catch flag.</ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>EXTERNAL</ipxact:name> - <ipxact:description>External debug request flag.</ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Memory Manage Fault Address</ipxact:name> - <ipxact:description>Use the Memory Manage Fault Address Register to read the address of the location that caused a Memory Manage Fault.</ipxact:description> - <ipxact:addressOffset>0xd34</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>ADDRESS</ipxact:name> - <ipxact:description>Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Bus Fault Address</ipxact:name> - <ipxact:description>Use the Bus Fault Address Register to read the address of the location that generated a Bus Fault.</ipxact:description> - <ipxact:addressOffset>0xd38</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>ADDRESS</ipxact:name> - <ipxact:description>Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Auxiliary Fault Address</ipxact:name> - <ipxact:description>Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault information to software. The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a single-cycle high level on an external pin causes the corresponding AFSR bit to become latched as one. The bit can only be cleared by writing a one to the corresponding AFSR bit. When an AFSR bit is written or latched as one, an exception does not occur. If you require an exception, you must use an interrupt.</ipxact:description> - <ipxact:addressOffset>0xd3c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>IMPDEF</ipxact:name> - <ipxact:description>Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>Software Trigger Interrupt</ipxact:name> - <ipxact:description>Use the Software Trigger Interrupt Register to pend an interrupt to trigger.</ipxact:description> - <ipxact:addressOffset>0xf00</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>INTID</ipxact:name> - <ipxact:description>Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> </ipxact:addressBlock> <ipxact:addressUnitBits>32</ipxact:addressUnitBits> </ipxact:memoryMap> + + <!-- Device NVM Registers: 0x6024_0000 to 6024_0080 (APE) --> + <ipxact:memoryMap> + <ipxact:name>NVM</ipxact:name> + <ipxact:description>Non-Volatile Memory Registers</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>NVM</ipxact:name> + <ipxact:description>Non-Volatile Memory Registers</ipxact:description> + <ipxact:baseAddress>0x60240000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + </ipxact:memoryMap> + </ipxact:memoryMaps> </ipxact:component> diff --git a/ipxact/NVIC.xml b/ipxact/NVIC.xml new file mode 100644 index 0000000..3cad47a --- /dev/null +++ b/ipxact/NVIC.xml @@ -0,0 +1,949 @@ +<?xml version="1.0" encoding="UTF-8"?> +<ipxact:component xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" xsi:schemaLocation="http://www.accellera.org/images/XMLSchema/IPXACT/1685-2014/index.xsd"> + <ipxact:vendor>meklort</ipxact:vendor> + <ipxact:library><PROJECT></ipxact:library> + <ipxact:name>NVIC Register Definitions</ipxact:name> + <ipxact:version>1.0</ipxact:version> + <ipxact:memoryMaps> + <!-- Nested Vectored Interrupt Controller: 0xE000_E000 --> + <ipxact:memoryMap> + <ipxact:name>NVIC</ipxact:name> + <ipxact:description>Nested Vectored Interrupt Controller</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>NVIC</ipxact:name> + <ipxact:description>Nested Vectored Interrupt Controller</ipxact:description> + <ipxact:baseAddress>0xE000E000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + <ipxact:register> + <ipxact:name>Interrupt Control Type</ipxact:name> + <ipxact:description>Read the Interrupt Controller Type Register to see the number of interrupt lines that the NVIC supports.</ipxact:description> + <ipxact:addressOffset>0x4</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>INTLINESNUM</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>0 to 32</ipxact:name> + <ipxact:value>0</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>33 to 64</ipxact:name> + <ipxact:value>1</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>65 to 96</ipxact:name> + <ipxact:value>2</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>SysTick Control and Status</ipxact:name> + <ipxact:description>Use the SysTick Control and Status Register to enable the SysTick features.</ipxact:description> + <ipxact:addressOffset>0x10</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>ENABLE</ipxact:name> + <ipxact:description>It set, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TICKINT</ipxact:name> + <ipxact:description>If set, counting down to 0 pends the SysTick handler.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>CLKSOURCE</ipxact:name> + <ipxact:description>If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable.</ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>COUNTFLAG</ipxact:name> + <ipxact:description>Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>SysTick Reload Value</ipxact:name> + <ipxact:description>Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0.</ipxact:description> + <ipxact:addressOffset>0x14</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>RELOAD</ipxact:name> + <ipxact:description>Value to load into the SysTick Current Value Register when the counter reaches 0.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>24</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>SysTick Current Value</ipxact:name> + <ipxact:description>Use the SysTick Current Value Register to find the current value in the register.</ipxact:description> + <ipxact:addressOffset>0x18</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>CURRENT</ipxact:name> + <ipxact:description>Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>24</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>SysTick Calibration Value</ipxact:name> + <ipxact:description>Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</ipxact:description> + <ipxact:addressOffset>0x1c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>TENMS</ipxact:name> + <ipxact:description>This value is the Reload value to use for 10ms timing. Depending on the value of SKEW, this might be exactly 10ms or might be the closest value. If this reads as 0, then the calibration value is not known. This is probably because the reference clock is an unknown input from the system or scalable dynamically.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>24</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SKEW</ipxact:name> + <ipxact:description>1 = the calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.</ipxact:description> + <ipxact:bitOffset>30</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>NOREF</ipxact:name> + <ipxact:description>1 = the reference clock is not provided.</ipxact:description> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Set-Enable</ipxact:name> + <ipxact:description>Each bit in the register corresponds to one of 32 interrupts. Setting a bit in the Interrupt Set-Enable Register enables the corresponding interrupt. When the enable bit of a pending interrupt is set, the processor activates the interrupt based on its priority. When the enable bit is clear, asserting its interrupt signal pends the interrupt, but it is not possible to activate the interrupt, regardless of its priority. Therefore, a disabled interrupt can serve as a latched general-purpose I/O bit. You can read it and clear it without invoking an interrupt.</ipxact:description> + <ipxact:addressOffset>0x100</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>SETENA</ipxact:name> + <ipxact:description>Writing 0 to a SETENA bit has no effect. Reading the bit returns its current enable state. Reset clears the SETENA fields.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Clear-Enable</ipxact:name> + <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Enable Register bit disables the corresponding interrupt.</ipxact:description> + <ipxact:addressOffset>0x180</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>CLRENA</ipxact:name> + <ipxact:description>Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Set-Pending</ipxact:name> + <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Set-Pending Register bit pends the corresponding interrupt.</ipxact:description> + <ipxact:addressOffset>0x200</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>SETPEND</ipxact:name> + <ipxact:description>Writing 0 to a SETPEND bit has no effect. Reading the bit returns its current state.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Clear-Pending</ipxact:name> + <ipxact:description>Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state.</ipxact:description> + <ipxact:addressOffset>0x280</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>CLRPEND</ipxact:name> + <ipxact:description>Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Active Bit</ipxact:name> + <ipxact:description>Read the Active Bit Register to determine which interrupts are active. Each flag in the register corresponds to one of the 32 interrupts.</ipxact:description> + <ipxact:addressOffset>0x300</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>ACTIVE</ipxact:name> + <ipxact:description>Interrupt active flags.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Priority 0</ipxact:name> + <ipxact:description>Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest.</ipxact:description> + <ipxact:addressOffset>0x400</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>PRI_0</ipxact:name> + <ipxact:description>Priority of Interrupt 0.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_1</ipxact:name> + <ipxact:description>Priority of Interrupt 1.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_2</ipxact:name> + <ipxact:description>Priority of Interrupt 2.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_3</ipxact:name> + <ipxact:description>Priority of Interrupt 3.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Priority 1</ipxact:name> + <ipxact:description>Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest.</ipxact:description> + <ipxact:addressOffset>0x404</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>PRI_4</ipxact:name> + <ipxact:description>Priority of Interrupt 4.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_5</ipxact:name> + <ipxact:description>Priority of Interrupt 5.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_6</ipxact:name> + <ipxact:description>Priority of Interrupt 6.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_7</ipxact:name> + <ipxact:description>Priority of Interrupt 7.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>CPU ID</ipxact:name> + <ipxact:description>Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</ipxact:description> + <ipxact:addressOffset>0xd00</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>REVISION</ipxact:name> + <ipxact:description>Implementation defined revision number.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PARTNO</ipxact:name> + <ipxact:description>Reads as 0xF</ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>12</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Constant</ipxact:name> + <ipxact:description>Priority of Interrupt 6.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VARIANT</ipxact:name> + <ipxact:description>Implementation defined variant number.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>IMPLEMENTER</ipxact:name> + <ipxact:description>Implementer code. ARM is 0x41.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Interrupt Control State</ipxact:name> + <ipxact:description>Use the Interrupt Control State Register to: set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</ipxact:description> + <ipxact:addressOffset>0xd04</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>VECTACTIVE</ipxact:name> + <ipxact:description>Active ISR number field. VECTACTIVE contains the interrupt number of the currently running ISR, including NMI and Hard Fault. A shared handler can use VECTACTIVE to determine which interrupt invoked it. You can subtract 16 from the VECTACTIVE field to index into the Interrupt Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority Registers. INTISR[0] has vector number 16.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>9</ipxact:bitWidth> + <ipxact:access>read-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>RETTOBASE</ipxact:name> + <ipxact:description>This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.</ipxact:description> + <ipxact:bitOffset>11</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VECTPENDING</ipxact:name> + <ipxact:description>Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.</ipxact:description> + <ipxact:bitOffset>12</ipxact:bitOffset> + <ipxact:bitWidth>10</ipxact:bitWidth> + <ipxact:access>read-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>ISRPENDING</ipxact:name> + <ipxact:description>Interrupt pending flag. Excludes NMI and Faults.</ipxact:description> + <ipxact:bitOffset>22</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>ISRPREEMPT</ipxact:name> + <ipxact:description>You must only use this at debug time. It indicates that a pending interrupt becomes active in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</ipxact:description> + <ipxact:bitOffset>22</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PENDSTCLR</ipxact:name> + <ipxact:description>Clear pending SysTick bit.</ipxact:description> + <ipxact:bitOffset>25</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>write-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PENDSTSET</ipxact:name> + <ipxact:description>Set a pending SysTick bit.</ipxact:description> + <ipxact:bitOffset>26</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PENDSVCLR</ipxact:name> + <ipxact:description>Clear pending pendSV bit.</ipxact:description> + <ipxact:bitOffset>27</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>write-Only</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PENDSVSET</ipxact:name> + <ipxact:description>Set pending pendSV bit.</ipxact:description> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>NMIPENDSET</ipxact:name> + <ipxact:description>NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.</ipxact:description> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Vector Table Offset</ipxact:name> + <ipxact:description>Use the Vector Table Offset Register to determine: if the vector table is in RAM or code memory, the vector table offset.</ipxact:description> + <ipxact:addressOffset>0xd08</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>TBLOFF</ipxact:name> + <ipxact:description>Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.</ipxact:description> + <ipxact:bitOffset>7</ipxact:bitOffset> + <ipxact:bitWidth>22</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TBLBASE</ipxact:name> + <ipxact:description>Table base is in Code (0) or RAM (1).</ipxact:description> + <ipxact:bitOffset>29</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Application Interrupt and Reset Control</ipxact:name> + <ipxact:description>the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).</ipxact:description> + <ipxact:addressOffset>0xd0c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>VECTRESET</ipxact:name> + <ipxact:description>System Reset bit. Resets the system, with the exception of debug components.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VECTCLRACTIVE</ipxact:name> + <ipxact:description>Clear active vector bit.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SYSRESETREQ</ipxact:name> + <ipxact:description>Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.</ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRIGROUP</ipxact:name> + <ipxact:description>PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>3</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>ENDIANESS</ipxact:name> + <ipxact:description>Data endianness bit: 1 = big endian.</ipxact:description> + <ipxact:bitOffset>15</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VECTKEY</ipxact:name> + <ipxact:description>Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored. Reads as 0xFA05.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>16</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>System Control</ipxact:name> + <ipxact:description>Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</ipxact:description> + <ipxact:addressOffset>0xd10</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>SLEEPONEXIT</ipxact:name> + <ipxact:description>Sleep on exit when returning from Handler mode to Thread mode: 1 = sleep on ISR exit.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SLEEPDEEP</ipxact:name> + <ipxact:description>1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.</ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SEVONPEND</ipxact:name> + <ipxact:description>When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.</ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Configuration Control</ipxact:name> + <ipxact:description>Use the Configuration Control Register to: enable NMI, Hard Fault and FAULTMASK to ignore bus fault, trap divide by zero, and unaligned accesses, enable user access to the Software Trigger Exception Register, control entry to Thread Mode.</ipxact:description> + <ipxact:addressOffset>0xd14</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>NONEBASETHRDENA</ipxact:name> + <ipxact:description>When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>USERSETMPEND</ipxact:name> + <ipxact:description>If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>UNALIGN_TRP</ipxact:name> + <ipxact:description>Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED, see Usage Fault Status Register.</ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DIV_0_TRP</ipxact:name> + <ipxact:description>Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register.</ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BFHFNMIGN</ipxact:name> + <ipxact:description>When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored – you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>STKALIGN</ipxact:name> + <ipxact:description>1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.</ipxact:description> + <ipxact:bitOffset>9</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>System Handler Priority 4</ipxact:name> + <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> + <ipxact:addressOffset>0xd18</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>PRI_4</ipxact:name> + <ipxact:description>Priority of Mem Manage.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_5</ipxact:name> + <ipxact:description>Priority of Bus Fault.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_6</ipxact:name> + <ipxact:description>Priority of Usage Fault.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_7</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>System Handler Priority 8</ipxact:name> + <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> + <ipxact:addressOffset>0xd1c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>PRI_8</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_9</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_10</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_11</ipxact:name> + <ipxact:description>Priority of SVCall.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>System Handler Priority 12</ipxact:name> + <ipxact:description>System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.</ipxact:description> + <ipxact:addressOffset>0xd20</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>PRI_12</ipxact:name> + <ipxact:description>Priority of Debug Monitor.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_13</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_14</ipxact:name> + <ipxact:description>Priority of PendSV.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PRI_15</ipxact:name> + <ipxact:description>Priority of SysTick.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>System Handler Control and State</ipxact:name> + <ipxact:description>Use the System Handler Control and State Register to: enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers.</ipxact:description> + <ipxact:addressOffset>0xd24</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>MEMFAULTACT</ipxact:name> + <ipxact:description>Reads as 1 if MemManage is active.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BUSFAULTACT</ipxact:name> + <ipxact:description>Reads as 1 if BusFault is active.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>USGFAULTACT</ipxact:name> + <ipxact:description>Reads as 1 if UsageFault is active.</ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SVCALLACT</ipxact:name> + <ipxact:description>Reads as 1 if SVCall is active.</ipxact:description> + <ipxact:bitOffset>7</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>MONITORACT</ipxact:name> + <ipxact:description>Reads as 1 if the Monitor is active.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PENDSVACT</ipxact:name> + <ipxact:description>Reads as 1 if PendSV is active.</ipxact:description> + <ipxact:bitOffset>10</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SYSTICKACT</ipxact:name> + <ipxact:description>Reads as 1 if SysTick is active.</ipxact:description> + <ipxact:bitOffset>11</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>USGFAULTPENDED</ipxact:name> + <ipxact:description>Read as 1 if usage fault is pended.</ipxact:description> + <ipxact:bitOffset>12</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>MEMFAULTPENDED</ipxact:name> + <ipxact:description>Reads as 1 if MemManage is pended.</ipxact:description> + <ipxact:bitOffset>13</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BUSFAULTPENDED</ipxact:name> + <ipxact:description>Reads as 1 if BusFault is pended.</ipxact:description> + <ipxact:bitOffset>14</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SVCALLPENDED</ipxact:name> + <ipxact:description>Reads as 1 if SVCall is pended.</ipxact:description> + <ipxact:bitOffset>15</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>MEMFAULTENA</ipxact:name> + <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BUSFAULTENA</ipxact:name> + <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> + <ipxact:bitOffset>17</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>USGFAULTENA</ipxact:name> + <ipxact:description>Set to 0 to disable, else 1 for enabled.</ipxact:description> + <ipxact:bitOffset>18</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Fault Status</ipxact:name> + <ipxact:description>The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.</ipxact:description> + <ipxact:addressOffset>0xd28</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Memory Manage Fault Status</ipxact:name> + <ipxact:description>The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Bus Fault Status</ipxact:name> + <ipxact:description>The flags in the Bus Fault Status Register indicate the cause of bus access faults.</ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Usage Fault Status</ipxact:name> + <ipxact:description>The flags in the Bus Fault Status Register indicate the cause of usage faults.</ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Reserved</ipxact:name> + <ipxact:description>Reserved.</ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Hard Fault Status</ipxact:name> + <ipxact:description>Use the Hard Fault Status Register (HFSR) to obtain information about events that activate the Hard Fault handler.</ipxact:description> + <ipxact:addressOffset>0xd2c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>VECTTBL</ipxact:name> + <ipxact:description>This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>FORCED</ipxact:name> + <ipxact:description>Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.</ipxact:description> + <ipxact:bitOffset>30</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DEBUGEVT</ipxact:name> + <ipxact:description>This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.</ipxact:description> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Debug Fault Status</ipxact:name> + <ipxact:description>Use the Debug Fault Status Register to monitor: external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests.</ipxact:description> + <ipxact:addressOffset>0xd30</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>HALTED</ipxact:name> + <ipxact:description>1 = halt requested by NVIC, including step. The processor is halted on the next instruction.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BKPT</ipxact:name> + <ipxact:description>The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DWTTRAP</ipxact:name> + <ipxact:description>Data Watchpoint and Trace (DWT) flag.</ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VCATCH</ipxact:name> + <ipxact:description>Vector catch flag.</ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>EXTERNAL</ipxact:name> + <ipxact:description>External debug request flag.</ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Memory Manage Fault Address</ipxact:name> + <ipxact:description>Use the Memory Manage Fault Address Register to read the address of the location that caused a Memory Manage Fault.</ipxact:description> + <ipxact:addressOffset>0xd34</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>ADDRESS</ipxact:name> + <ipxact:description>Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Bus Fault Address</ipxact:name> + <ipxact:description>Use the Bus Fault Address Register to read the address of the location that generated a Bus Fault.</ipxact:description> + <ipxact:addressOffset>0xd38</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>ADDRESS</ipxact:name> + <ipxact:description>Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Auxiliary Fault Address</ipxact:name> + <ipxact:description>Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault information to software. The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a single-cycle high level on an external pin causes the corresponding AFSR bit to become latched as one. The bit can only be cleared by writing a one to the corresponding AFSR bit. When an AFSR bit is written or latched as one, an exception does not occur. If you require an exception, you must use an interrupt.</ipxact:description> + <ipxact:addressOffset>0xd3c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>IMPDEF</ipxact:name> + <ipxact:description>Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>Software Trigger Interrupt</ipxact:name> + <ipxact:description>Use the Software Trigger Interrupt Register to pend an interrupt to trigger.</ipxact:description> + <ipxact:addressOffset>0xf00</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>INTID</ipxact:name> + <ipxact:description>Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + </ipxact:addressBlock> + <ipxact:addressUnitBits>32</ipxact:addressUnitBits> + </ipxact:memoryMap> + </ipxact:memoryMaps> +</ipxact:component> diff --git a/ipxact/bcm5719.xml b/ipxact/bcm5719.xml index 35d0e59..1725378 100644 --- a/ipxact/bcm5719.xml +++ b/ipxact/bcm5719.xml @@ -3230,10 +3230,10 @@ <!-- Device NVM Registers: 0xC000_7000 to C000_7080 --> <ipxact:memoryMap> <ipxact:name>NVM</ipxact:name> - <ipxact:description>Device Registers</ipxact:description> + <ipxact:description>Non-Volatile Memory Registers</ipxact:description> <ipxact:addressBlock> <ipxact:name>NVM</ipxact:name> - <ipxact:description>Device Registers</ipxact:description> + <ipxact:description>Non-Volatile Memory Registers</ipxact:description> <ipxact:baseAddress>0xC0007000</ipxact:baseAddress> <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> diff --git a/ipxact/regen.sh b/ipxact/regen.sh index 2b22544..3e7c1db 100755 --- a/ipxact/regen.sh +++ b/ipxact/regen.sh @@ -23,6 +23,19 @@ mv bcm5719_BOOTCODE.h ../include ${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.cpp mv *.cpp ../simulator/ -${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.s +# ${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.s ${IPXACT} -p ${PROJECT} bcm5719_full.xml -t asym bcm5719_sym.s mv *.s ../libs/bcm5719/ + + +PROJECT=ape + +echo "Regenerating APE header" + + +${IPXACT} -p ${PROJECT} NVIC.xml APE.xml APE.h +mv APE_NVIC.h ../include/ + +# ${IPXACT} -p ${PROJECT} NVIC.xml APE.xml APE.s +${IPXACT} -p ${PROJECT} NVIC.xml APE.xml -t asym APE_sym.s +mv *.s ../libs/bcm5719/ |
