Rename FILTERS to FILTERS0 to match the rest of the APE network peripherals.

4 files changed, 153 insertions, 153 deletions

diff --git a/include/APE_FILTERS.h b/include/APE_FILTERS0.h
index e83b039..c848abd 100644
--- a/include/APE_FILTERS.h
+++ b/include/APE_FILTERS0.h
@@ -1,10 +1,10 @@
 ////////////////////////////////////////////////////////////////////////////////
 ///
-/// @file       APE_FILTERS.h
+/// @file       APE_FILTERS0.h
 ///
 /// @project    ape
 ///
-/// @brief      APE_FILTERS
+/// @brief      APE_FILTERS0
 ///
 ////////////////////////////////////////////////////////////////////////////////
 ///
@@ -42,26 +42,26 @@
 /// @endcond
 ////////////////////////////////////////////////////////////////////////////////
 
-/** @defgroup APE_FILTERS_H    APE_FILTERS */
-/** @addtogroup APE_FILTERS_H
+/** @defgroup APE_FILTERS0_H    APE_FILTERS0 */
+/** @addtogroup APE_FILTERS0_H
  * @{
  */
-#ifndef APE_FILTERS_H
-#define APE_FILTERS_H
+#ifndef APE_FILTERS0_H
+#define APE_FILTERS0_H
 
 #include <types.h>
 
 #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */
-void init_APE_FILTERS_sim(void* base);
-void init_APE_FILTERS(void);
+void init_APE_FILTERS0_sim(void* base);
+void init_APE_FILTERS0(void);
 
 #include <CXXRegister.h>
-typedef CXXRegister<uint8_t,  0,  8> APE_FILTERS_H_uint8_t;
-typedef CXXRegister<uint16_t, 0, 16> APE_FILTERS_H_uint16_t;
-typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS_H_uint32_t;
-#define APE_FILTERS_H_uint8_t_bitfield(__pos__, __width__)  CXXRegister<uint8_t,  __pos__, __width__>
-#define APE_FILTERS_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__>
-#define APE_FILTERS_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__>
+typedef CXXRegister<uint8_t,  0,  8> APE_FILTERS0_H_uint8_t;
+typedef CXXRegister<uint16_t, 0, 16> APE_FILTERS0_H_uint16_t;
+typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS0_H_uint32_t;
+#define APE_FILTERS0_H_uint8_t_bitfield(__pos__, __width__)  CXXRegister<uint8_t,  __pos__, __width__>
+#define APE_FILTERS0_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__>
+#define APE_FILTERS0_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__>
 #define register_container struct
 #define volatile
 #define BITFIELD_BEGIN(__type__, __name__) struct {
@@ -69,31 +69,31 @@ typedef CXXRegister<uint32_t, 0, 32> APE_FILTERS_H_uint32_t;
 #define BITFIELD_END(__type__, __name__) } __name__;
 
 #else /* Firmware Data types */
-typedef uint8_t  APE_FILTERS_H_uint8_t;
-typedef uint16_t APE_FILTERS_H_uint16_t;
-typedef uint32_t APE_FILTERS_H_uint32_t;
+typedef uint8_t  APE_FILTERS0_H_uint8_t;
+typedef uint16_t APE_FILTERS0_H_uint16_t;
+typedef uint32_t APE_FILTERS0_H_uint32_t;
 #define register_container union
 #define BITFIELD_BEGIN(__type__, __name__) struct {
 #define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__;
 #define BITFIELD_END(__type__, __name__) } __name__;
 #endif /* !CXX_SIMULATOR */
 
-#define REG_FILTERS_BASE ((volatile void*)0xa0048000) /* Management Filter Registers, function 0 */
-#define REG_FILTERS_SIZE (sizeof(FILTERS_t))
-
-#define REG_FILTERS_ELEMENT_CONFIG ((volatile APE_FILTERS_H_uint32_t*)0xa0048000) /* Element Configuration Register. */
-#define     FILTERS_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u
-#define     FILTERS_ELEMENT_CONFIG_RULE_OFFSET_MASK  0xffu
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_OFFSET(__reg__)  (((__reg__) & 0xff) >> 0u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_OFFSET(__val__)  (((__val__) << 0u) & 0xffu)
-#define     FILTERS_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u
-#define     FILTERS_ELEMENT_CONFIG_RULE_CLASS_MASK  0x1f00u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_CLASS(__reg__)  (((__reg__) & 0x1f00) >> 8u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_CLASS(__val__)  (((__val__) << 8u) & 0x1f00u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u
-#define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_MASK  0xe000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_HEADER(__reg__)  (((__reg__) & 0xe000) >> 13u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_HEADER(__val__)  (((__val__) << 13u) & 0xe000u)
+#define REG_FILTERS0_BASE ((volatile void*)0xa0048000) /* Management Filter Registers, function 0 */
+#define REG_FILTERS0_SIZE (sizeof(FILTERS_t))
+
+#define REG_FILTERS0_ELEMENT_CONFIG ((volatile APE_FILTERS0_H_uint32_t*)0xa0048000) /* Element Configuration Register. */
+#define     FILTERS0_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_OFFSET_MASK  0xffu
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_OFFSET(__reg__)  (((__reg__) & 0xff) >> 0u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_OFFSET(__val__)  (((__val__) << 0u) & 0xffu)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_CLASS_MASK  0x1f00u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_CLASS(__reg__)  (((__reg__) & 0x1f00) >> 8u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_CLASS(__val__)  (((__val__) << 8u) & 0x1f00u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_HEADER_MASK  0xe000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_HEADER(__reg__)  (((__reg__) & 0xe000) >> 13u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_HEADER(__val__)  (((__val__) << 13u) & 0xe000u)
 #define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u
 #define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u
 #define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u
@@ -103,112 +103,112 @@ typedef uint32_t APE_FILTERS_H_uint32_t;
 #define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u
 #define     FILTERS_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u
 
-#define     FILTERS_ELEMENT_CONFIG_RULE_OP_SHIFT 16u
-#define     FILTERS_ELEMENT_CONFIG_RULE_OP_MASK  0x30000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_OP(__reg__)  (((__reg__) & 0x30000) >> 16u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_OP(__val__)  (((__val__) << 16u) & 0x30000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_OP_SHIFT 16u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_OP_MASK  0x30000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_OP(__reg__)  (((__reg__) & 0x30000) >> 16u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_OP(__val__)  (((__val__) << 16u) & 0x30000u)
 #define     FILTERS_ELEMENT_CONFIG_RULE_OP_EQ 0x0u
 #define     FILTERS_ELEMENT_CONFIG_RULE_OP_NE 0x1u
 #define     FILTERS_ELEMENT_CONFIG_RULE_OP_GT 0x2u
 #define     FILTERS_ELEMENT_CONFIG_RULE_OP_LT 0x3u
 
-#define     FILTERS_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u
-#define     FILTERS_ELEMENT_CONFIG_RULE_MAP_MASK  0x1000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_MAP(__reg__)  (((__reg__) & 0x1000000) >> 24u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_MAP(__val__)  (((__val__) << 24u) & 0x1000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u
-#define     FILTERS_ELEMENT_CONFIG_RULE_DISCARD_MASK  0x2000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_DISCARD(__reg__)  (((__reg__) & 0x2000000) >> 25u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_DISCARD(__val__)  (((__val__) << 25u) & 0x2000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u
-#define     FILTERS_ELEMENT_CONFIG_RULE_MASK_MASK  0x4000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_MASK(__reg__)  (((__reg__) & 0x4000000) >> 26u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_MASK(__val__)  (((__val__) << 26u) & 0x4000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_P3_SHIFT 27u
-#define     FILTERS_ELEMENT_CONFIG_RULE_P3_MASK  0x8000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_P3(__reg__)  (((__reg__) & 0x8000000) >> 27u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_P3(__val__)  (((__val__) << 27u) & 0x8000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_P2_SHIFT 28u
-#define     FILTERS_ELEMENT_CONFIG_RULE_P2_MASK  0x10000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_P2(__reg__)  (((__reg__) & 0x10000000) >> 28u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_P2(__val__)  (((__val__) << 28u) & 0x10000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_P1_SHIFT 29u
-#define     FILTERS_ELEMENT_CONFIG_RULE_P1_MASK  0x20000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_P1(__reg__)  (((__reg__) & 0x20000000) >> 29u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_P1(__val__)  (((__val__) << 29u) & 0x20000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_AND_SHIFT 30u
-#define     FILTERS_ELEMENT_CONFIG_RULE_AND_MASK  0x40000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_AND(__reg__)  (((__reg__) & 0x40000000) >> 30u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_AND(__val__)  (((__val__) << 30u) & 0x40000000u)
-#define     FILTERS_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u
-#define     FILTERS_ELEMENT_CONFIG_RULE_ENABLE_MASK  0x80000000u
-#define GET_FILTERS_ELEMENT_CONFIG_RULE_ENABLE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
-#define SET_FILTERS_ELEMENT_CONFIG_RULE_ENABLE(__val__)  (((__val__) << 31u) & 0x80000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_MAP_MASK  0x1000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_MAP(__reg__)  (((__reg__) & 0x1000000) >> 24u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_MAP(__val__)  (((__val__) << 24u) & 0x1000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_DISCARD_MASK  0x2000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_DISCARD(__reg__)  (((__reg__) & 0x2000000) >> 25u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_DISCARD(__val__)  (((__val__) << 25u) & 0x2000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_MASK_MASK  0x4000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_MASK(__reg__)  (((__reg__) & 0x4000000) >> 26u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_MASK(__val__)  (((__val__) << 26u) & 0x4000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P3_SHIFT 27u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P3_MASK  0x8000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_P3(__reg__)  (((__reg__) & 0x8000000) >> 27u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_P3(__val__)  (((__val__) << 27u) & 0x8000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P2_SHIFT 28u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P2_MASK  0x10000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_P2(__reg__)  (((__reg__) & 0x10000000) >> 28u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_P2(__val__)  (((__val__) << 28u) & 0x10000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P1_SHIFT 29u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_P1_MASK  0x20000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_P1(__reg__)  (((__reg__) & 0x20000000) >> 29u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_P1(__val__)  (((__val__) << 29u) & 0x20000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_AND_SHIFT 30u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_AND_MASK  0x40000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_AND(__reg__)  (((__reg__) & 0x40000000) >> 30u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_AND(__val__)  (((__val__) << 30u) & 0x40000000u)
+#define     FILTERS0_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u
+#define     FILTERS0_ELEMENT_CONFIG_RULE_ENABLE_MASK  0x80000000u
+#define GET_FILTERS0_ELEMENT_CONFIG_RULE_ENABLE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
+#define SET_FILTERS0_ELEMENT_CONFIG_RULE_ENABLE(__val__)  (((__val__) << 31u) & 0x80000000u)
 
 /** @brief Register definition for @ref FILTERS_t.ElementConfig. */
 typedef register_container RegFILTERSElementConfig_t {
     /** @brief 32bit direct register access. */
-    APE_FILTERS_H_uint32_t r32;
+    APE_FILTERS0_H_uint32_t r32;
 
-    BITFIELD_BEGIN(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_BEGIN(APE_FILTERS0_H_uint32_t, bits)
 #if defined(__LITTLE_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleOffset, 0, 8)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleOffset, 0, 8)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleClass, 8, 5)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleClass, 8, 5)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleHeader, 13, 3)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleHeader, 13, 3)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleOp, 16, 2)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleOp, 16, 2)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_23_18, 18, 6)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_23_18, 18, 6)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleMap, 24, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleMap, 24, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleDiscard, 25, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleDiscard, 25, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleMask, 26, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleMask, 26, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP3, 27, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP3, 27, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP2, 28, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP2, 28, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP1, 29, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP1, 29, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleAnd, 30, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleAnd, 30, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleEnable, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleEnable, 31, 1)
 #elif defined(__BIG_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleEnable, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleEnable, 31, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleAnd, 30, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleAnd, 30, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP1, 29, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP1, 29, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP2, 28, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP2, 28, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleP3, 27, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleP3, 27, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleMask, 26, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleMask, 26, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleDiscard, 25, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleDiscard, 25, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleMap, 24, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleMap, 24, 1)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_23_18, 18, 6)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_23_18, 18, 6)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleOp, 16, 2)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleOp, 16, 2)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleHeader, 13, 3)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleHeader, 13, 3)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleClass, 8, 5)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleClass, 8, 5)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, RuleOffset, 0, 8)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, RuleOffset, 0, 8)
 #else
 #error Unknown Endian
 #endif
-    BITFIELD_END(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_END(APE_FILTERS0_H_uint32_t, bits)
 #ifdef CXX_SIMULATOR
     /** @brief Register name for use with the simulator. */
     const char* getName(void) { return "ElementConfig"; }
@@ -253,11 +253,11 @@ typedef register_container RegFILTERSElementConfig_t {
 #endif /* CXX_SIMULATOR */
 } RegFILTERSElementConfig_t;
 
-#define REG_FILTERS_ELEMENT_PATTERN ((volatile APE_FILTERS_H_uint32_t*)0xa0048080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */
+#define REG_FILTERS0_ELEMENT_PATTERN ((volatile APE_FILTERS0_H_uint32_t*)0xa0048080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */
 /** @brief Register definition for @ref FILTERS_t.ElementPattern. */
 typedef register_container RegFILTERSElementPattern_t {
     /** @brief 32bit direct register access. */
-    APE_FILTERS_H_uint32_t r32;
+    APE_FILTERS0_H_uint32_t r32;
 #ifdef CXX_SIMULATOR
     /** @brief Register name for use with the simulator. */
     const char* getName(void) { return "ElementPattern"; }
@@ -278,40 +278,40 @@ typedef register_container RegFILTERSElementPattern_t {
 #endif /* CXX_SIMULATOR */
 } RegFILTERSElementPattern_t;
 
-#define REG_FILTERS_RULE_CONFIGURATION ((volatile APE_FILTERS_H_uint32_t*)0xa0048100) /*  */
-#define     FILTERS_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u
-#define     FILTERS_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK  0x1u
-#define GET_FILTERS_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__)  (((__reg__) & 0x1) >> 0u)
-#define SET_FILTERS_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__)  (((__val__) << 0u) & 0x1u)
-#define     FILTERS_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u
-#define     FILTERS_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK  0x80000000u
-#define GET_FILTERS_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
-#define SET_FILTERS_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__)  (((__val__) << 31u) & 0x80000000u)
+#define REG_FILTERS0_RULE_CONFIGURATION ((volatile APE_FILTERS0_H_uint32_t*)0xa0048100) /*  */
+#define     FILTERS0_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u
+#define     FILTERS0_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK  0x1u
+#define GET_FILTERS0_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_FILTERS0_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     FILTERS0_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u
+#define     FILTERS0_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK  0x80000000u
+#define GET_FILTERS0_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
+#define SET_FILTERS0_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__)  (((__val__) << 31u) & 0x80000000u)
 
 /** @brief Register definition for @ref FILTERS_t.RuleConfiguration. */
 typedef register_container RegFILTERSRuleConfiguration_t {
     /** @brief 32bit direct register access. */
-    APE_FILTERS_H_uint32_t r32;
+    APE_FILTERS0_H_uint32_t r32;
 
-    BITFIELD_BEGIN(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_BEGIN(APE_FILTERS0_H_uint32_t, bits)
 #if defined(__LITTLE_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, FilterSetDisable, 0, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, FilterSetDisable, 0, 1)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_30_1, 1, 30)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_30_1, 1, 30)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, DirectIPFragmenttoAPE, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, DirectIPFragmenttoAPE, 31, 1)
 #elif defined(__BIG_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, DirectIPFragmenttoAPE, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, DirectIPFragmenttoAPE, 31, 1)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_30_1, 1, 30)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_30_1, 1, 30)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, FilterSetDisable, 0, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, FilterSetDisable, 0, 1)
 #else
 #error Unknown Endian
 #endif
-    BITFIELD_END(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_END(APE_FILTERS0_H_uint32_t, bits)
 #ifdef CXX_SIMULATOR
     /** @brief Register name for use with the simulator. */
     const char* getName(void) { return "RuleConfiguration"; }
@@ -336,56 +336,56 @@ typedef register_container RegFILTERSRuleConfiguration_t {
 #endif /* CXX_SIMULATOR */
 } RegFILTERSRuleConfiguration_t;
 
-#define REG_FILTERS_RULE_SET ((volatile APE_FILTERS_H_uint32_t*)0xa0048104) /*  */
-#define     FILTERS_RULE_SET_ACTION_SHIFT 0u
-#define     FILTERS_RULE_SET_ACTION_MASK  0x3u
-#define GET_FILTERS_RULE_SET_ACTION(__reg__)  (((__reg__) & 0x3) >> 0u)
-#define SET_FILTERS_RULE_SET_ACTION(__val__)  (((__val__) << 0u) & 0x3u)
+#define REG_FILTERS0_RULE_SET ((volatile APE_FILTERS0_H_uint32_t*)0xa0048104) /*  */
+#define     FILTERS0_RULE_SET_ACTION_SHIFT 0u
+#define     FILTERS0_RULE_SET_ACTION_MASK  0x3u
+#define GET_FILTERS0_RULE_SET_ACTION(__reg__)  (((__reg__) & 0x3) >> 0u)
+#define SET_FILTERS0_RULE_SET_ACTION(__val__)  (((__val__) << 0u) & 0x3u)
 #define     FILTERS_RULE_SET_ACTION_TO_APE_ONLY 0x0u
 #define     FILTERS_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u
 #define     FILTERS_RULE_SET_ACTION_DISCARD 0x2u
 
-#define     FILTERS_RULE_SET_COUNT_SHIFT 3u
-#define     FILTERS_RULE_SET_COUNT_MASK  0x7fff8u
-#define GET_FILTERS_RULE_SET_COUNT(__reg__)  (((__reg__) & 0x7fff8) >> 3u)
-#define SET_FILTERS_RULE_SET_COUNT(__val__)  (((__val__) << 3u) & 0x7fff8u)
-#define     FILTERS_RULE_SET_ENABLE_SHIFT 31u
-#define     FILTERS_RULE_SET_ENABLE_MASK  0x80000000u
-#define GET_FILTERS_RULE_SET_ENABLE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
-#define SET_FILTERS_RULE_SET_ENABLE(__val__)  (((__val__) << 31u) & 0x80000000u)
+#define     FILTERS0_RULE_SET_COUNT_SHIFT 3u
+#define     FILTERS0_RULE_SET_COUNT_MASK  0x7fff8u
+#define GET_FILTERS0_RULE_SET_COUNT(__reg__)  (((__reg__) & 0x7fff8) >> 3u)
+#define SET_FILTERS0_RULE_SET_COUNT(__val__)  (((__val__) << 3u) & 0x7fff8u)
+#define     FILTERS0_RULE_SET_ENABLE_SHIFT 31u
+#define     FILTERS0_RULE_SET_ENABLE_MASK  0x80000000u
+#define GET_FILTERS0_RULE_SET_ENABLE(__reg__)  (((__reg__) & 0x80000000) >> 31u)
+#define SET_FILTERS0_RULE_SET_ENABLE(__val__)  (((__val__) << 31u) & 0x80000000u)
 
 /** @brief Register definition for @ref FILTERS_t.RuleSet. */
 typedef register_container RegFILTERSRuleSet_t {
     /** @brief 32bit direct register access. */
-    APE_FILTERS_H_uint32_t r32;
+    APE_FILTERS0_H_uint32_t r32;
 
-    BITFIELD_BEGIN(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_BEGIN(APE_FILTERS0_H_uint32_t, bits)
 #if defined(__LITTLE_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Action, 0, 2)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Action, 0, 2)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_2_2, 2, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_2_2, 2, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Count, 3, 16)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Count, 3, 16)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_30_19, 19, 12)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_30_19, 19, 12)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Enable, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Enable, 31, 1)
 #elif defined(__BIG_ENDIAN__)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Enable, 31, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Enable, 31, 1)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_30_19, 19, 12)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_30_19, 19, 12)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Count, 3, 16)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Count, 3, 16)
         /** @brief Padding */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, reserved_2_2, 2, 1)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, reserved_2_2, 2, 1)
         /** @brief  */
-        BITFIELD_MEMBER(APE_FILTERS_H_uint32_t, Action, 0, 2)
+        BITFIELD_MEMBER(APE_FILTERS0_H_uint32_t, Action, 0, 2)
 #else
 #error Unknown Endian
 #endif
-    BITFIELD_END(APE_FILTERS_H_uint32_t, bits)
+    BITFIELD_END(APE_FILTERS0_H_uint32_t, bits)
 #ifdef CXX_SIMULATOR
     /** @brief Register name for use with the simulator. */
     const char* getName(void) { return "RuleSet"; }
@@ -412,11 +412,11 @@ typedef register_container RegFILTERSRuleSet_t {
 #endif /* CXX_SIMULATOR */
 } RegFILTERSRuleSet_t;
 
-#define REG_FILTERS_RULE_MASK ((volatile APE_FILTERS_H_uint32_t*)0xa0048184) /*  */
+#define REG_FILTERS0_RULE_MASK ((volatile APE_FILTERS0_H_uint32_t*)0xa0048184) /*  */
 /** @brief Register definition for @ref FILTERS_t.RuleMask. */
 typedef register_container RegFILTERSRuleMask_t {
     /** @brief 32bit direct register access. */
-    APE_FILTERS_H_uint32_t r32;
+    APE_FILTERS0_H_uint32_t r32;
 #ifdef CXX_SIMULATOR
     /** @brief Register name for use with the simulator. */
     const char* getName(void) { return "RuleMask"; }
@@ -437,7 +437,7 @@ typedef register_container RegFILTERSRuleMask_t {
 #endif /* CXX_SIMULATOR */
 } RegFILTERSRuleMask_t;
 
-/** @brief Component definition for @ref FILTERS. */
+/** @brief Component definition for @ref FILTERS0. */
 typedef struct FILTERS_t {
     /** @brief Element Configuration Register. */
     RegFILTERSElementConfig_t ElementConfig[32];
@@ -452,7 +452,7 @@ typedef struct FILTERS_t {
     RegFILTERSRuleSet_t RuleSet[31];
 
     /** @brief Reserved bytes to pad out data structure. */
-    APE_FILTERS_H_uint32_t reserved_384[1];
+    APE_FILTERS0_H_uint32_t reserved_384[1];
 
     /** @brief  */
     RegFILTERSRuleMask_t RuleMask[31];
@@ -491,7 +491,7 @@ typedef struct FILTERS_t {
 } FILTERS_t;
 
 /** @brief Management Filter Registers, function 0 */
-extern volatile FILTERS_t FILTERS;
+extern volatile FILTERS_t FILTERS0;
 
 
 
@@ -504,6 +504,6 @@ extern volatile FILTERS_t FILTERS;
 #undef BITFIELD_MEMBER
 #undef BITFIELD_END
 
-#endif /* !APE_FILTERS_H */
+#endif /* !APE_FILTERS0_H */
 
 /** @} */
diff --git a/include/APE_FILTERS1.h b/include/APE_FILTERS1.h
index 42e264f..6b0ded5 100644
--- a/include/APE_FILTERS1.h
+++ b/include/APE_FILTERS1.h
@@ -50,7 +50,7 @@
 #define APE_FILTERS1_H
 
 #include <types.h>
-#include "APE_FILTERS.h"
+#include "APE_FILTERS0.h"
 
 #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */
 void init_APE_FILTERS1_sim(void* base);
diff --git a/include/APE_FILTERS2.h b/include/APE_FILTERS2.h
index e48d71b..2c7559c 100644
--- a/include/APE_FILTERS2.h
+++ b/include/APE_FILTERS2.h
@@ -50,7 +50,7 @@
 #define APE_FILTERS2_H
 
 #include <types.h>
-#include "APE_FILTERS.h"
+#include "APE_FILTERS0.h"
 
 #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */
 void init_APE_FILTERS2_sim(void* base);
diff --git a/include/APE_FILTERS3.h b/include/APE_FILTERS3.h
index 3f4b5e1..fd4db08 100644
--- a/include/APE_FILTERS3.h
+++ b/include/APE_FILTERS3.h
@@ -50,7 +50,7 @@
 #define APE_FILTERS3_H
 
 #include <types.h>
-#include "APE_FILTERS.h"
+#include "APE_FILTERS0.h"
 
 #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */
 void init_APE_FILTERS3_sim(void* base);