Update ipxact to include addtional APE registers.

5 files changed, 3973 insertions, 41 deletions

diff --git a/include/bcm5719_APE.h b/include/bcm5719_APE.h
index b40bb19..e23e76a 100644
--- a/include/bcm5719_APE.h
+++ b/include/bcm5719_APE.h
@@ -1233,10 +1233,49 @@ typedef register_container RegAPE4028_t {
 } RegAPE4028_t;
 
 #define REG_APE_RCPU_SEG_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */
+#define     APE_RCPU_SEG_SIG_SIG_SHIFT 0u
+#define     APE_RCPU_SEG_SIG_SIG_MASK  0xffffffffu
+#define GET_APE_RCPU_SEG_SIG_SIG(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
+#define SET_APE_RCPU_SEG_SIG_SIG(__val__)  (((__val__) << 0u) & 0xffffffffu)
+#define     APE_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u
+
+
 /** @brief Register definition for @ref APE_t.RcpuSegSig. */
 typedef register_container RegAPERcpuSegSig_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Sig, 0, 32)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Sig, 0, 32)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "RcpuSegSig"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPERcpuSegSig_t()
+    {
+        /** @brief constructor for @ref APE_t.RcpuSegSig. */
+        r32.setName("RcpuSegSig");
+        bits.Sig.setBaseRegister(&r32);
+        bits.Sig.setName("Sig");
+    }
+    RegAPERcpuSegSig_t& operator=(const RegAPERcpuSegSig_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPERcpuSegSig_t;
 
 #define REG_APE_RCPU_SEG_LENGTH ((volatile BCM5719_APE_H_uint32_t*)0xc0014104) /* Set to 0x34. */
@@ -1281,26 +1320,26 @@ typedef register_container RegAPERcpuPciSubsystemId_t {
     BCM5719_APE_H_uint32_t r32;
 } RegAPERcpuPciSubsystemId_t;
 
-#define REG_APE_411C ((volatile BCM5719_APE_H_uint32_t*)0xc001411c) /* Unknown. Incremented by frobnicating routine. */
-/** @brief Register definition for @ref APE_t.411c. */
-typedef register_container RegAPE411c_t {
+#define REG_APE_RCPU_APE_RESET_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc001411c) /* Unknown. Incremented by frobnicating routine. */
+/** @brief Register definition for @ref APE_t.RcpuApeResetCount. */
+typedef register_container RegAPERcpuApeResetCount_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
-} RegAPE411c_t;
+} RegAPERcpuApeResetCount_t;
 
-#define REG_APE_4120 ((volatile BCM5719_APE_H_uint32_t*)0xc0014120) /* Unknown. Written by frobnicating routine. */
-/** @brief Register definition for @ref APE_t.4120. */
-typedef register_container RegAPE4120_t {
+#define REG_APE_RCPU_LAST_APE_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014120) /* Unknown. Written by frobnicating routine. */
+/** @brief Register definition for @ref APE_t.RcpuLastApeStatus. */
+typedef register_container RegAPERcpuLastApeStatus_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
-} RegAPE4120_t;
+} RegAPERcpuLastApeStatus_t;
 
-#define REG_APE_4124 ((volatile BCM5719_APE_H_uint32_t*)0xc0014124) /* Unknown.  */
-/** @brief Register definition for @ref APE_t.4124. */
-typedef register_container RegAPE4124_t {
+#define REG_APE_RCPU_LAST_APE_FW_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014124) /* Unknown.  */
+/** @brief Register definition for @ref APE_t.RcpuLastApeFwStatus. */
+typedef register_container RegAPERcpuLastApeFwStatus_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
-} RegAPE4124_t;
+} RegAPERcpuLastApeFwStatus_t;
 
 #define REG_APE_RCPU_CFG_HW ((volatile BCM5719_APE_H_uint32_t*)0xc0014128) /* Set from  */
 /** @brief Register definition for @ref APE_t.RcpuCfgHw. */
@@ -1317,10 +1356,59 @@ typedef register_container RegAPERcpuCfgHw2_t {
 } RegAPERcpuCfgHw2_t;
 
 #define REG_APE_RCPU_CPMU_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014130) /* Set from  */
+#define     APE_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u
+#define     APE_RCPU_CPMU_STATUS_ADDRESS_MASK  0xffffu
+#define GET_APE_RCPU_CPMU_STATUS_ADDRESS(__reg__)  (((__reg__) & 0xffff) >> 0u)
+#define SET_APE_RCPU_CPMU_STATUS_ADDRESS(__val__)  (((__val__) << 0u) & 0xffffu)
+#define     APE_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu
+
+#define     APE_RCPU_CPMU_STATUS_STATUS_SHIFT 16u
+#define     APE_RCPU_CPMU_STATUS_STATUS_MASK  0xffff0000u
+#define GET_APE_RCPU_CPMU_STATUS_STATUS(__reg__)  (((__reg__) & 0xffff0000) >> 16u)
+#define SET_APE_RCPU_CPMU_STATUS_STATUS(__val__)  (((__val__) << 16u) & 0xffff0000u)
+
 /** @brief Register definition for @ref APE_t.RcpuCpmuStatus. */
 typedef register_container RegAPERcpuCpmuStatus_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Address, 0, 16)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Status, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Status, 16, 16)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Address, 0, 16)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "RcpuCpmuStatus"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPERcpuCpmuStatus_t()
+    {
+        /** @brief constructor for @ref APE_t.RcpuCpmuStatus. */
+        r32.setName("RcpuCpmuStatus");
+        bits.Address.setBaseRegister(&r32);
+        bits.Address.setName("Address");
+        bits.Status.setBaseRegister(&r32);
+        bits.Status.setName("Status");
+    }
+    RegAPERcpuCpmuStatus_t& operator=(const RegAPERcpuCpmuStatus_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPERcpuCpmuStatus_t;
 
 #define REG_APE_HOST_SEG_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */
@@ -1599,81 +1687,1960 @@ typedef register_container RegAPEChipId_t {
     BCM5719_APE_H_uint32_t r32;
 } RegAPEChipId_t;
 
+#define REG_APE_NCSI_CHANNEL0_INFO ((volatile BCM5719_APE_H_uint32_t*)0xc0014900) /*  */
+#define     APE_NCSI_CHANNEL0_INFO_ENABLED_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_INFO_ENABLED_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_INFO_ENABLED(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_INFO_ENABLED(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH_MASK  0x2u
+#define GET_APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_NCSI_CHANNEL0_INFO_READY_SHIFT 2u
+#define     APE_NCSI_CHANNEL0_INFO_READY_MASK  0x4u
+#define GET_APE_NCSI_CHANNEL0_INFO_READY(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_NCSI_CHANNEL0_INFO_READY(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_NCSI_CHANNEL0_INFO_INIT_SHIFT 3u
+#define     APE_NCSI_CHANNEL0_INFO_INIT_MASK  0x8u
+#define GET_APE_NCSI_CHANNEL0_INFO_INIT(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_NCSI_CHANNEL0_INFO_INIT(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_NCSI_CHANNEL0_INFO_MFILT_SHIFT 4u
+#define     APE_NCSI_CHANNEL0_INFO_MFILT_MASK  0x10u
+#define GET_APE_NCSI_CHANNEL0_INFO_MFILT(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_NCSI_CHANNEL0_INFO_MFILT(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_NCSI_CHANNEL0_INFO_BFILT_SHIFT 5u
+#define     APE_NCSI_CHANNEL0_INFO_BFILT_MASK  0x20u
+#define GET_APE_NCSI_CHANNEL0_INFO_BFILT(__reg__)  (((__reg__) & 0x20) >> 5u)
+#define SET_APE_NCSI_CHANNEL0_INFO_BFILT(__val__)  (((__val__) << 5u) & 0x20u)
+#define     APE_NCSI_CHANNEL0_INFO_SERDES_SHIFT 6u
+#define     APE_NCSI_CHANNEL0_INFO_SERDES_MASK  0x40u
+#define GET_APE_NCSI_CHANNEL0_INFO_SERDES(__reg__)  (((__reg__) & 0x40) >> 6u)
+#define SET_APE_NCSI_CHANNEL0_INFO_SERDES(__val__)  (((__val__) << 6u) & 0x40u)
+#define     APE_NCSI_CHANNEL0_INFO_VLAN_SHIFT 8u
+#define     APE_NCSI_CHANNEL0_INFO_VLAN_MASK  0x100u
+#define GET_APE_NCSI_CHANNEL0_INFO_VLAN(__reg__)  (((__reg__) & 0x100) >> 8u)
+#define SET_APE_NCSI_CHANNEL0_INFO_VLAN(__val__)  (((__val__) << 8u) & 0x100u)
+#define     APE_NCSI_CHANNEL0_INFO_B2H_SHIFT 10u
+#define     APE_NCSI_CHANNEL0_INFO_B2H_MASK  0x400u
+#define GET_APE_NCSI_CHANNEL0_INFO_B2H(__reg__)  (((__reg__) & 0x400) >> 10u)
+#define SET_APE_NCSI_CHANNEL0_INFO_B2H(__val__)  (((__val__) << 10u) & 0x400u)
+#define     APE_NCSI_CHANNEL0_INFO_B2N_SHIFT 11u
+#define     APE_NCSI_CHANNEL0_INFO_B2N_MASK  0x800u
+#define GET_APE_NCSI_CHANNEL0_INFO_B2N(__reg__)  (((__reg__) & 0x800) >> 11u)
+#define SET_APE_NCSI_CHANNEL0_INFO_B2N(__val__)  (((__val__) << 11u) & 0x800u)
+#define     APE_NCSI_CHANNEL0_INFO_EEE_SHIFT 12u
+#define     APE_NCSI_CHANNEL0_INFO_EEE_MASK  0x1000u
+#define GET_APE_NCSI_CHANNEL0_INFO_EEE(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_NCSI_CHANNEL0_INFO_EEE(__val__)  (((__val__) << 12u) & 0x1000u)
+#define     APE_NCSI_CHANNEL0_INFO_PDEAD_SHIFT 14u
+#define     APE_NCSI_CHANNEL0_INFO_PDEAD_MASK  0x4000u
+#define GET_APE_NCSI_CHANNEL0_INFO_PDEAD(__reg__)  (((__reg__) & 0x4000) >> 14u)
+#define SET_APE_NCSI_CHANNEL0_INFO_PDEAD(__val__)  (((__val__) << 14u) & 0x4000u)
+#define     APE_NCSI_CHANNEL0_INFO_DRIVER_SHIFT 14u
+#define     APE_NCSI_CHANNEL0_INFO_DRIVER_MASK  0x4000u
+#define GET_APE_NCSI_CHANNEL0_INFO_DRIVER(__reg__)  (((__reg__) & 0x4000) >> 14u)
+#define SET_APE_NCSI_CHANNEL0_INFO_DRIVER(__val__)  (((__val__) << 14u) & 0x4000u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Info. */
+typedef register_container RegAPENcsiChannel0Info_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enabled, 0, 1)
+        /** @brief TX passthrough has been enabled by BMC NCSI command. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXPassthrough, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Init, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MFILT, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, BFILT, 5, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 6, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, VLAN, 8, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_9_9, 9, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2H, 10, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2N, 11, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EEE, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_13, 13, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, PDead, 14, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 14, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 14, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, PDead, 14, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_13, 13, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EEE, 12, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2N, 11, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2H, 10, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_9_9, 9, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, VLAN, 8, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 6, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, BFILT, 5, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MFILT, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Init, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 2, 1)
+        /** @brief TX passthrough has been enabled by BMC NCSI command. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXPassthrough, 1, 1)
+        /** @brief This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enabled, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Info"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Info_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Info. */
+        r32.setName("NcsiChannel0Info");
+        bits.Enabled.setBaseRegister(&r32);
+        bits.Enabled.setName("Enabled");
+        bits.TXPassthrough.setBaseRegister(&r32);
+        bits.TXPassthrough.setName("TXPassthrough");
+        bits.Ready.setBaseRegister(&r32);
+        bits.Ready.setName("Ready");
+        bits.Init.setBaseRegister(&r32);
+        bits.Init.setName("Init");
+        bits.MFILT.setBaseRegister(&r32);
+        bits.MFILT.setName("MFILT");
+        bits.BFILT.setBaseRegister(&r32);
+        bits.BFILT.setName("BFILT");
+        bits.SERDES.setBaseRegister(&r32);
+        bits.SERDES.setName("SERDES");
+        bits.VLAN.setBaseRegister(&r32);
+        bits.VLAN.setName("VLAN");
+        bits.B2H.setBaseRegister(&r32);
+        bits.B2H.setName("B2H");
+        bits.B2N.setBaseRegister(&r32);
+        bits.B2N.setName("B2N");
+        bits.EEE.setBaseRegister(&r32);
+        bits.EEE.setName("EEE");
+        bits.PDead.setBaseRegister(&r32);
+        bits.PDead.setName("PDead");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPENcsiChannel0Info_t& operator=(const RegAPENcsiChannel0Info_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Info_t;
+
+#define REG_APE_NCSI_CHANNEL0_MCID ((volatile BCM5719_APE_H_uint32_t*)0xc0014904) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mcid. */
+typedef register_container RegAPENcsiChannel0Mcid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mcid_t;
+
+#define REG_APE_NCSI_CHANNEL0_AEN ((volatile BCM5719_APE_H_uint32_t*)0xc0014908) /* Set via NCSI ENABLE AEN. */
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK  0x2u
+#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u
+#define     APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK  0x4u
+#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__)  (((__val__) << 2u) & 0x4u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Aen. */
+typedef register_container RegAPENcsiChannel0Aen_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableLinkStatusChangeAEN, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableConfigurationRequiredAEN, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableHostNCDriverStatusChangeAEN, 2, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableHostNCDriverStatusChangeAEN, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableConfigurationRequiredAEN, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableLinkStatusChangeAEN, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Aen"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Aen_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Aen. */
+        r32.setName("NcsiChannel0Aen");
+        bits.EnableLinkStatusChangeAEN.setBaseRegister(&r32);
+        bits.EnableLinkStatusChangeAEN.setName("EnableLinkStatusChangeAEN");
+        bits.EnableConfigurationRequiredAEN.setBaseRegister(&r32);
+        bits.EnableConfigurationRequiredAEN.setName("EnableConfigurationRequiredAEN");
+        bits.EnableHostNCDriverStatusChangeAEN.setBaseRegister(&r32);
+        bits.EnableHostNCDriverStatusChangeAEN.setName("EnableHostNCDriverStatusChangeAEN");
+    }
+    RegAPENcsiChannel0Aen_t& operator=(const RegAPENcsiChannel0Aen_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Aen_t;
+
+#define REG_APE_NCSI_CHANNEL0_BFILT ((volatile BCM5719_APE_H_uint32_t*)0xc001490c) /*  */
+#define     APE_NCSI_CHANNEL0_BFILT_ARP_PACKET_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_BFILT_ARP_PACKET_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_BFILT_ARP_PACKET(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_BFILT_ARP_PACKET(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET_MASK  0x2u
+#define GET_APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET_SHIFT 2u
+#define     APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET_MASK  0x4u
+#define GET_APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET_SHIFT 3u
+#define     APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET_MASK  0x8u
+#define GET_APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET(__val__)  (((__val__) << 3u) & 0x8u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Bfilt. */
+typedef register_container RegAPENcsiChannel0Bfilt_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ARPPacket, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPClientPacket, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPServerPacket, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NetBIOSPacket, 3, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_4, 4, 28)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_4, 4, 28)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NetBIOSPacket, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPServerPacket, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPClientPacket, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ARPPacket, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Bfilt"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Bfilt_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Bfilt. */
+        r32.setName("NcsiChannel0Bfilt");
+        bits.ARPPacket.setBaseRegister(&r32);
+        bits.ARPPacket.setName("ARPPacket");
+        bits.DHCPClientPacket.setBaseRegister(&r32);
+        bits.DHCPClientPacket.setName("DHCPClientPacket");
+        bits.DHCPServerPacket.setBaseRegister(&r32);
+        bits.DHCPServerPacket.setName("DHCPServerPacket");
+        bits.NetBIOSPacket.setBaseRegister(&r32);
+        bits.NetBIOSPacket.setName("NetBIOSPacket");
+    }
+    RegAPENcsiChannel0Bfilt_t& operator=(const RegAPENcsiChannel0Bfilt_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Bfilt_t;
+
+#define REG_APE_NCSI_CHANNEL0_MFILT ((volatile BCM5719_APE_H_uint32_t*)0xc0014910) /*  */
+#define     APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK  0x2u
+#define GET_APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u
+#define     APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK  0x4u
+#define GET_APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__)  (((__val__) << 2u) & 0x4u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mfilt. */
+typedef register_container RegAPENcsiChannel0Mfilt_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6NeighbourAdvertisement, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6RouterAdvertisement, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPv6RelayandServerMulticast, 2, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPv6RelayandServerMulticast, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6RouterAdvertisement, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6NeighbourAdvertisement, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Mfilt"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Mfilt_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Mfilt. */
+        r32.setName("NcsiChannel0Mfilt");
+        bits.IPv6NeighbourAdvertisement.setBaseRegister(&r32);
+        bits.IPv6NeighbourAdvertisement.setName("IPv6NeighbourAdvertisement");
+        bits.IPv6RouterAdvertisement.setBaseRegister(&r32);
+        bits.IPv6RouterAdvertisement.setName("IPv6RouterAdvertisement");
+        bits.DHCPv6RelayandServerMulticast.setBaseRegister(&r32);
+        bits.DHCPv6RelayandServerMulticast.setName("DHCPv6RelayandServerMulticast");
+    }
+    RegAPENcsiChannel0Mfilt_t& operator=(const RegAPENcsiChannel0Mfilt_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Mfilt_t;
+
+#define REG_APE_NCSI_CHANNEL0_SETTING_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0014914) /* This is the "Link Settings" value from NCSI Set Link. */
+#define     APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE_MASK  0x2u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE_MASK  0x4u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK  0x8u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u
+#define     APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE_MASK  0x10u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u
+#define     APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE_MASK  0x100u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE(__reg__)  (((__reg__) & 0x100) >> 8u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE(__val__)  (((__val__) << 8u) & 0x100u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u
+#define     APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE_MASK  0x200u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE(__reg__)  (((__reg__) & 0x200) >> 9u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE(__val__)  (((__val__) << 9u) & 0x200u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u
+#define     APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK  0x400u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__)  (((__reg__) & 0x400) >> 10u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__)  (((__val__) << 10u) & 0x400u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u
+#define     APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK  0x800u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__)  (((__reg__) & 0x800) >> 11u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__)  (((__val__) << 11u) & 0x800u)
+#define     APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u
+#define     APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK  0x1000u
+#define GET_APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__)  (((__val__) << 12u) & 0x1000u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Setting1. */
+typedef register_container RegAPENcsiChannel0Setting1_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Autonegotiationenabled, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Menable, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed100Menable, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000Menable, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Genable, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halfduplexenable, 8, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Fullduplexenable, 9, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pausecapabilityenable, 10, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Asymmetricpausecapabilityenable, 11, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, OEMlinksettingsfieldvalid, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, OEMlinksettingsfieldvalid, 12, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Asymmetricpausecapabilityenable, 11, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pausecapabilityenable, 10, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Fullduplexenable, 9, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halfduplexenable, 8, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Genable, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000Menable, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed100Menable, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Menable, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Autonegotiationenabled, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Setting1"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Setting1_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Setting1. */
+        r32.setName("NcsiChannel0Setting1");
+        bits.Autonegotiationenabled.setBaseRegister(&r32);
+        bits.Autonegotiationenabled.setName("Autonegotiationenabled");
+        bits.LinkSpeed10Menable.setBaseRegister(&r32);
+        bits.LinkSpeed10Menable.setName("LinkSpeed10Menable");
+        bits.LinkSpeed100Menable.setBaseRegister(&r32);
+        bits.LinkSpeed100Menable.setName("LinkSpeed100Menable");
+        bits.LinkSpeed1000Menable.setBaseRegister(&r32);
+        bits.LinkSpeed1000Menable.setName("LinkSpeed1000Menable");
+        bits.LinkSpeed10Genable.setBaseRegister(&r32);
+        bits.LinkSpeed10Genable.setName("LinkSpeed10Genable");
+        bits.Halfduplexenable.setBaseRegister(&r32);
+        bits.Halfduplexenable.setName("Halfduplexenable");
+        bits.Fullduplexenable.setBaseRegister(&r32);
+        bits.Fullduplexenable.setName("Fullduplexenable");
+        bits.Pausecapabilityenable.setBaseRegister(&r32);
+        bits.Pausecapabilityenable.setName("Pausecapabilityenable");
+        bits.Asymmetricpausecapabilityenable.setBaseRegister(&r32);
+        bits.Asymmetricpausecapabilityenable.setName("Asymmetricpausecapabilityenable");
+        bits.OEMlinksettingsfieldvalid.setBaseRegister(&r32);
+        bits.OEMlinksettingsfieldvalid.setName("OEMlinksettingsfieldvalid");
+    }
+    RegAPENcsiChannel0Setting1_t& operator=(const RegAPENcsiChannel0Setting1_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Setting1_t;
+
+#define REG_APE_NCSI_CHANNEL0_SETTING_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0014918) /* This is the "OEM Settings" value from NCSI Set Link. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Setting2. */
+typedef register_container RegAPENcsiChannel0Setting2_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Setting2_t;
+
+#define REG_APE_NCSI_CHANNEL0_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc001491c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Vlan. */
+typedef register_container RegAPENcsiChannel0Vlan_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Vlan_t;
+
+#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014924) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacHigh. */
+typedef register_container RegAPENcsiChannel0AltHostMacHigh_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0AltHostMacHigh_t;
+
+#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014928) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacMid. */
+typedef register_container RegAPENcsiChannel0AltHostMacMid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0AltHostMacMid_t;
+
+#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001492c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacLow. */
+typedef register_container RegAPENcsiChannel0AltHostMacLow_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0AltHostMacLow_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC0_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014934) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0High. */
+typedef register_container RegAPENcsiChannel0Mac0High_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac0High_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC0_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014938) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Mid. */
+typedef register_container RegAPENcsiChannel0Mac0Mid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac0Mid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC0_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001493c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Low. */
+typedef register_container RegAPENcsiChannel0Mac0Low_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac0Low_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC1_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014944) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1High. */
+typedef register_container RegAPENcsiChannel0Mac1High_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac1High_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC1_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014948) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Mid. */
+typedef register_container RegAPENcsiChannel0Mac1Mid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac1Mid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC1_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001494c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Low. */
+typedef register_container RegAPENcsiChannel0Mac1Low_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac1Low_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC2_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014954) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2High. */
+typedef register_container RegAPENcsiChannel0Mac2High_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac2High_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC2_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014958) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2Mid. */
+typedef register_container RegAPENcsiChannel0Mac2Mid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac2Mid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC2_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001495c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2Low. */
+typedef register_container RegAPENcsiChannel0Mac2Low_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac2Low_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC3_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014964) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3High. */
+typedef register_container RegAPENcsiChannel0Mac3High_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac3High_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC3_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014968) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3Mid. */
+typedef register_container RegAPENcsiChannel0Mac3Mid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac3Mid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC3_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001496c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3Low. */
+typedef register_container RegAPENcsiChannel0Mac3Low_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac3Low_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC0_VLAN_VALID ((volatile BCM5719_APE_H_uint32_t*)0xc0014970) /* Nonzero indicates VLAN field is valid */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0VlanValid. */
+typedef register_container RegAPENcsiChannel0Mac0VlanValid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac0VlanValid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC0_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc0014974) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Vlan. */
+typedef register_container RegAPENcsiChannel0Mac0Vlan_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac0Vlan_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC1_VLAN_VALID ((volatile BCM5719_APE_H_uint32_t*)0xc0014978) /* Nonzero indicates VLAN field is valid */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1VlanValid. */
+typedef register_container RegAPENcsiChannel0Mac1VlanValid_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac1VlanValid_t;
+
+#define REG_APE_NCSI_CHANNEL0_MAC1_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc001497c) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Vlan. */
+typedef register_container RegAPENcsiChannel0Mac1Vlan_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Mac1Vlan_t;
+
+#define REG_APE_NCSI_CHANNEL0_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014980) /*  */
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_UP_SHIFT 0u
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_UP_MASK  0x1u
+#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_UP(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_UP(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_STATUS_SHIFT 1u
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_STATUS_MASK  0x1eu
+#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_STATUS(__reg__)  (((__reg__) & 0x1e) >> 1u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_STATUS(__val__)  (((__val__) << 1u) & 0x1eu)
+#define     APE_NCSI_CHANNEL0_STATUS_SERDES_SHIFT 5u
+#define     APE_NCSI_CHANNEL0_STATUS_SERDES_MASK  0x20u
+#define GET_APE_NCSI_CHANNEL0_STATUS_SERDES(__reg__)  (((__reg__) & 0x20) >> 5u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_SERDES(__val__)  (((__val__) << 5u) & 0x20u)
+#define     APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u
+#define     APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE_MASK  0x40u
+#define GET_APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE(__reg__)  (((__reg__) & 0x40) >> 6u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE(__val__)  (((__val__) << 6u) & 0x40u)
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK  0x200u
+#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__)  (((__reg__) & 0x200) >> 9u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__)  (((__val__) << 9u) & 0x200u)
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u
+#define     APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK  0x400u
+#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__)  (((__reg__) & 0x400) >> 10u)
+#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__)  (((__val__) << 10u) & 0x400u)
+
+/** @brief Register definition for @ref APE_t.NcsiChannel0Status. */
+typedef register_container RegAPENcsiChannel0Status_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Linkup, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkStatus, 1, 4)
+        /** @brief Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 5, 1)
+        /** @brief Set if autonegotiation is complete. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, AutonegotiationComplete, 6, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_8_7, 7, 2)
+        /** @brief Link partner 1000BASE-T full duplex capable */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MFullDuplexCapable, 9, 1)
+        /** @brief Link partner 1000BASE-T half duplex capable */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MHalsDuplexCapable, 10, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_11, 11, 21)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_11, 11, 21)
+        /** @brief Link partner 1000BASE-T half duplex capable */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MHalsDuplexCapable, 10, 1)
+        /** @brief Link partner 1000BASE-T full duplex capable */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MFullDuplexCapable, 9, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_8_7, 7, 2)
+        /** @brief Set if autonegotiation is complete. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, AutonegotiationComplete, 6, 1)
+        /** @brief Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case. */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 5, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkStatus, 1, 4)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Linkup, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NcsiChannel0Status"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPENcsiChannel0Status_t()
+    {
+        /** @brief constructor for @ref APE_t.NcsiChannel0Status. */
+        r32.setName("NcsiChannel0Status");
+        bits.Linkup.setBaseRegister(&r32);
+        bits.Linkup.setName("Linkup");
+        bits.LinkStatus.setBaseRegister(&r32);
+        bits.LinkStatus.setName("LinkStatus");
+        bits.SERDES.setBaseRegister(&r32);
+        bits.SERDES.setName("SERDES");
+        bits.AutonegotiationComplete.setBaseRegister(&r32);
+        bits.AutonegotiationComplete.setName("AutonegotiationComplete");
+        bits.LinkSpeed1000MFullDuplexCapable.setBaseRegister(&r32);
+        bits.LinkSpeed1000MFullDuplexCapable.setName("LinkSpeed1000MFullDuplexCapable");
+        bits.LinkSpeed1000MHalsDuplexCapable.setBaseRegister(&r32);
+        bits.LinkSpeed1000MHalsDuplexCapable.setName("LinkSpeed1000MHalsDuplexCapable");
+    }
+    RegAPENcsiChannel0Status_t& operator=(const RegAPENcsiChannel0Status_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegAPENcsiChannel0Status_t;
+
+#define REG_APE_NCSI_CHANNEL0_RESET_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc0014984) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0ResetCount. */
+typedef register_container RegAPENcsiChannel0ResetCount_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0ResetCount_t;
+
+#define REG_APE_NCSI_CHANNEL0_PXE ((volatile BCM5719_APE_H_uint32_t*)0xc0014988) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Pxe. */
+typedef register_container RegAPENcsiChannel0Pxe_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Pxe_t;
+
+#define REG_APE_NCSI_CHANNEL0_DROPFIL ((volatile BCM5719_APE_H_uint32_t*)0xc001498c) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Dropfil. */
+typedef register_container RegAPENcsiChannel0Dropfil_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Dropfil_t;
+
+#define REG_APE_NCSI_CHANNEL0_SLINK ((volatile BCM5719_APE_H_uint32_t*)0xc0014990) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Slink. */
+typedef register_container RegAPENcsiChannel0Slink_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Slink_t;
+
+#define REG_APE_NCSI_CHANNEL0_DBG ((volatile BCM5719_APE_H_uint32_t*)0xc00149a0) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0Dbg. */
+typedef register_container RegAPENcsiChannel0Dbg_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0Dbg_t;
+
+#define REG_APE_NCSI_CHANNEL0_CTRLSTAT_RX ((volatile BCM5719_APE_H_uint32_t*)0xc00149b0) /*  */
+/** @brief Register definition for @ref APE_t.NcsiChannel0CtrlstatRx. */
+typedef register_container RegAPENcsiChannel0CtrlstatRx_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_APE_H_uint32_t r32;
+} RegAPENcsiChannel0CtrlstatRx_t;
+
 #define REG_APE_PER_LOCK_REQUEST_PHY0 ((volatile BCM5719_APE_H_uint32_t*)0xc0018400) /* This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0). */
+#define     APE_PER_LOCK_REQUEST_PHY0_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_PHY0_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_PHY0_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_PHY0_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_PHY0_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_PHY0_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_PHY0_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_PHY0_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_PHY0_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestPhy0. */
 typedef register_container RegAPEPerLockRequestPhy0_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestPhy0"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestPhy0_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestPhy0. */
+        r32.setName("PerLockRequestPhy0");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestPhy0_t& operator=(const RegAPEPerLockRequestPhy0_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestPhy0_t;
 
 #define REG_APE_PER_LOCK_REQUEST_GRC ((volatile BCM5719_APE_H_uint32_t*)0xc0018404) /*  */
+#define     APE_PER_LOCK_REQUEST_GRC_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_GRC_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_GRC_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_GRC_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_GRC_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_GRC_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_GRC_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_GRC_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_GRC_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_GRC_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_GRC_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestGrc. */
 typedef register_container RegAPEPerLockRequestGrc_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestGrc"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestGrc_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestGrc. */
+        r32.setName("PerLockRequestGrc");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestGrc_t& operator=(const RegAPEPerLockRequestGrc_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestGrc_t;
 
 #define REG_APE_PER_LOCK_REQUEST_PHY1 ((volatile BCM5719_APE_H_uint32_t*)0xc0018408) /*  */
+#define     APE_PER_LOCK_REQUEST_PHY1_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_PHY1_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_PHY1_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_PHY1_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_PHY1_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_PHY1_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_PHY1_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_PHY1_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_PHY1_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestPhy1. */
 typedef register_container RegAPEPerLockRequestPhy1_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestPhy1"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestPhy1_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestPhy1. */
+        r32.setName("PerLockRequestPhy1");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestPhy1_t& operator=(const RegAPEPerLockRequestPhy1_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestPhy1_t;
 
 #define REG_APE_PER_LOCK_REQUEST_PHY2 ((volatile BCM5719_APE_H_uint32_t*)0xc001840c) /*  */
+#define     APE_PER_LOCK_REQUEST_PHY2_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_PHY2_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_PHY2_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_PHY2_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_PHY2_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_PHY2_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_PHY2_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_PHY2_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_PHY2_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestPhy2. */
 typedef register_container RegAPEPerLockRequestPhy2_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestPhy2"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestPhy2_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestPhy2. */
+        r32.setName("PerLockRequestPhy2");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestPhy2_t& operator=(const RegAPEPerLockRequestPhy2_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestPhy2_t;
 
 #define REG_APE_PER_LOCK_REQUEST_MEM ((volatile BCM5719_APE_H_uint32_t*)0xc0018410) /*  */
+#define     APE_PER_LOCK_REQUEST_MEM_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_MEM_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_MEM_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_MEM_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_MEM_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_MEM_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_MEM_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_MEM_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_MEM_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_MEM_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_MEM_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestMem. */
 typedef register_container RegAPEPerLockRequestMem_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestMem"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestMem_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestMem. */
+        r32.setName("PerLockRequestMem");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestMem_t& operator=(const RegAPEPerLockRequestMem_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestMem_t;
 
 #define REG_APE_PER_LOCK_REQUEST_PHY3 ((volatile BCM5719_APE_H_uint32_t*)0xc0018414) /*  */
+#define     APE_PER_LOCK_REQUEST_PHY3_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_PHY3_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_PHY3_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_PHY3_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_PHY3_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_PHY3_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_PHY3_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_PHY3_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_PHY3_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestPhy3. */
 typedef register_container RegAPEPerLockRequestPhy3_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestPhy3"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestPhy3_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestPhy3. */
+        r32.setName("PerLockRequestPhy3");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestPhy3_t& operator=(const RegAPEPerLockRequestPhy3_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestPhy3_t;
 
 #define REG_APE_PER_LOCK_REQUEST_PORT6 ((volatile BCM5719_APE_H_uint32_t*)0xc0018418) /*  */
+#define     APE_PER_LOCK_REQUEST_PORT6_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_PORT6_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_PORT6_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_PORT6_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_PORT6_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_PORT6_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_PORT6_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_PORT6_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_PORT6_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestPort6. */
 typedef register_container RegAPEPerLockRequestPort6_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestPort6"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestPort6_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestPort6. */
+        r32.setName("PerLockRequestPort6");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestPort6_t& operator=(const RegAPEPerLockRequestPort6_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestPort6_t;
 
 #define REG_APE_PER_LOCK_REQUEST_GPIO ((volatile BCM5719_APE_H_uint32_t*)0xc001841c) /*  */
+#define     APE_PER_LOCK_REQUEST_GPIO_APE_SHIFT 0u
+#define     APE_PER_LOCK_REQUEST_GPIO_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_REQUEST_GPIO_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_REQUEST_GPIO_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_REQUEST_GPIO_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_REQUEST_GPIO_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_REQUEST_GPIO_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_REQUEST_GPIO_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_REQUEST_GPIO_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockRequestGpio. */
 typedef register_container RegAPEPerLockRequestGpio_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockRequestGpio"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockRequestGpio_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockRequestGpio. */
+        r32.setName("PerLockRequestGpio");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockRequestGpio_t& operator=(const RegAPEPerLockRequestGpio_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockRequestGpio_t;
 
 #define REG_APE_PER_LOCK_GRANT_PHY0 ((volatile BCM5719_APE_H_uint32_t*)0xc0018420) /*  */
+#define     APE_PER_LOCK_GRANT_PHY0_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_PHY0_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_PHY0_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_PHY0_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_PHY0_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_PHY0_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_PHY0_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_PHY0_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_PHY0_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_PHY0_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_PHY0_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantPhy0. */
 typedef register_container RegAPEPerLockGrantPhy0_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantPhy0"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantPhy0_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantPhy0. */
+        r32.setName("PerLockGrantPhy0");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantPhy0_t& operator=(const RegAPEPerLockGrantPhy0_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantPhy0_t;
 
 #define REG_APE_PER_LOCK_GRANT_GRC ((volatile BCM5719_APE_H_uint32_t*)0xc0018424) /*  */
+#define     APE_PER_LOCK_GRANT_GRC_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_GRC_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_GRC_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_GRC_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_GRC_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_GRC_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_GRC_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_GRC_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_GRC_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_GRC_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_GRC_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_GRC_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_GRC_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_GRC_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_GRC_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_GRC_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_GRC_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_GRC_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_GRC_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantGrc. */
 typedef register_container RegAPEPerLockGrantGrc_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantGrc"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantGrc_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantGrc. */
+        r32.setName("PerLockGrantGrc");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantGrc_t& operator=(const RegAPEPerLockGrantGrc_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantGrc_t;
 
 #define REG_APE_PER_LOCK_GRANT_PHY1 ((volatile BCM5719_APE_H_uint32_t*)0xc0018428) /*  */
+#define     APE_PER_LOCK_GRANT_PHY1_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_PHY1_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_PHY1_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_PHY1_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_PHY1_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_PHY1_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_PHY1_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_PHY1_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_PHY1_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_PHY1_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_PHY1_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantPhy1. */
 typedef register_container RegAPEPerLockGrantPhy1_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantPhy1"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantPhy1_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantPhy1. */
+        r32.setName("PerLockGrantPhy1");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantPhy1_t& operator=(const RegAPEPerLockGrantPhy1_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantPhy1_t;
 
 #define REG_APE_PER_LOCK_GRANT_PHY2 ((volatile BCM5719_APE_H_uint32_t*)0xc001842c) /*  */
@@ -1684,31 +3651,411 @@ typedef register_container RegAPEPerLockGrantPhy2_t {
 } RegAPEPerLockGrantPhy2_t;
 
 #define REG_APE_PER_LOCK_GRANT_MEM ((volatile BCM5719_APE_H_uint32_t*)0xc0018430) /*  */
+#define     APE_PER_LOCK_GRANT_MEM_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_MEM_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_MEM_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_MEM_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_MEM_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_MEM_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_MEM_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_MEM_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_MEM_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_MEM_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_MEM_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_MEM_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_MEM_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_MEM_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_MEM_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_MEM_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_MEM_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_MEM_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_MEM_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantMem. */
 typedef register_container RegAPEPerLockGrantMem_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantMem"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantMem_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantMem. */
+        r32.setName("PerLockGrantMem");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantMem_t& operator=(const RegAPEPerLockGrantMem_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantMem_t;
 
 #define REG_APE_PER_LOCK_GRANT_PHY3 ((volatile BCM5719_APE_H_uint32_t*)0xc0018434) /*  */
+#define     APE_PER_LOCK_GRANT_PHY3_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_PHY3_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_PHY3_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_PHY3_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_PHY3_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_PHY3_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_PHY3_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_PHY3_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_PHY3_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_PHY3_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_PHY3_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantPhy3. */
 typedef register_container RegAPEPerLockGrantPhy3_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantPhy3"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantPhy3_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantPhy3. */
+        r32.setName("PerLockGrantPhy3");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantPhy3_t& operator=(const RegAPEPerLockGrantPhy3_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantPhy3_t;
 
 #define REG_APE_PER_LOCK_GRANT_PORT6 ((volatile BCM5719_APE_H_uint32_t*)0xc0018438) /*  */
+#define     APE_PER_LOCK_GRANT_PORT6_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_PORT6_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_PORT6_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_PORT6_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_PORT6_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_PORT6_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_PORT6_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_PORT6_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_PORT6_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_PORT6_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_PORT6_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantPort6. */
 typedef register_container RegAPEPerLockGrantPort6_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantPort6"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantPort6_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantPort6. */
+        r32.setName("PerLockGrantPort6");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantPort6_t& operator=(const RegAPEPerLockGrantPort6_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantPort6_t;
 
 #define REG_APE_PER_LOCK_GRANT_GPIO ((volatile BCM5719_APE_H_uint32_t*)0xc001843c) /*  */
+#define     APE_PER_LOCK_GRANT_GPIO_APE_SHIFT 0u
+#define     APE_PER_LOCK_GRANT_GPIO_APE_MASK  0x1u
+#define GET_APE_PER_LOCK_GRANT_GPIO_APE(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_APE(__val__)  (((__val__) << 0u) & 0x1u)
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_1_SHIFT 1u
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_1_MASK  0x2u
+#define GET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_1(__reg__)  (((__reg__) & 0x2) >> 1u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_1(__val__)  (((__val__) << 1u) & 0x2u)
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_2_SHIFT 2u
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_2_MASK  0x4u
+#define GET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_2(__reg__)  (((__reg__) & 0x4) >> 2u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_2(__val__)  (((__val__) << 2u) & 0x4u)
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_3_SHIFT 3u
+#define     APE_PER_LOCK_GRANT_GPIO_FUNCTION_3_MASK  0x8u
+#define GET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_3(__reg__)  (((__reg__) & 0x8) >> 3u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_FUNCTION_3(__val__)  (((__val__) << 3u) & 0x8u)
+#define     APE_PER_LOCK_GRANT_GPIO_BOOTCODE_SHIFT 4u
+#define     APE_PER_LOCK_GRANT_GPIO_BOOTCODE_MASK  0x10u
+#define GET_APE_PER_LOCK_GRANT_GPIO_BOOTCODE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_BOOTCODE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     APE_PER_LOCK_GRANT_GPIO_DRIVER_SHIFT 12u
+#define     APE_PER_LOCK_GRANT_GPIO_DRIVER_MASK  0x1000u
+#define GET_APE_PER_LOCK_GRANT_GPIO_DRIVER(__reg__)  (((__reg__) & 0x1000) >> 12u)
+#define SET_APE_PER_LOCK_GRANT_GPIO_DRIVER(__val__)  (((__val__) << 12u) & 0x1000u)
+
 /** @brief Register definition for @ref APE_t.PerLockGrantGpio. */
 typedef register_container RegAPEPerLockGrantGpio_t {
     /** @brief 32bit direct register access. */
     BCM5719_APE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 12, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_11_5, 5, 7)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Bootcode, 4, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function3, 3, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function2, 2, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Function1, 1, 1)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, APE, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "PerLockGrantGpio"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegAPEPerLockGrantGpio_t()
+    {
+        /** @brief constructor for @ref APE_t.PerLockGrantGpio. */
+        r32.setName("PerLockGrantGpio");
+        bits.APE.setBaseRegister(&r32);
+        bits.APE.setName("APE");
+        bits.Function1.setBaseRegister(&r32);
+        bits.Function1.setName("Function1");
+        bits.Function2.setBaseRegister(&r32);
+        bits.Function2.setName("Function2");
+        bits.Function3.setBaseRegister(&r32);
+        bits.Function3.setName("Function3");
+        bits.Bootcode.setBaseRegister(&r32);
+        bits.Bootcode.setName("Bootcode");
+        bits.Driver.setBaseRegister(&r32);
+        bits.Driver.setName("Driver");
+    }
+    RegAPEPerLockGrantGpio_t& operator=(const RegAPEPerLockGrantGpio_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
 } RegAPEPerLockGrantGpio_t;
 
 /** @brief Component definition for @ref APE. */
@@ -1846,13 +4193,13 @@ typedef struct {
     RegAPERcpuPciSubsystemId_t RcpuPciSubsystemId;
 
     /** @brief Unknown. Incremented by frobnicating routine. */
-    RegAPE411c_t _411c;
+    RegAPERcpuApeResetCount_t RcpuApeResetCount;
 
     /** @brief Unknown. Written by frobnicating routine. */
-    RegAPE4120_t _4120;
+    RegAPERcpuLastApeStatus_t RcpuLastApeStatus;
 
     /** @brief Unknown.  */
-    RegAPE4124_t _4124;
+    RegAPERcpuLastApeFwStatus_t RcpuLastApeFwStatus;
 
     /** @brief Set from  */
     RegAPERcpuCfgHw_t RcpuCfgHw;
@@ -1951,7 +4298,133 @@ typedef struct {
     RegAPEChipId_t ChipId;
 
     /** @brief Reserved bytes to pad out data structure. */
-    BCM5719_APE_H_uint32_t reserved_18580[3803];
+    BCM5719_APE_H_uint32_t reserved_18580[27];
+
+    /** @brief  */
+    RegAPENcsiChannel0Info_t NcsiChannel0Info;
+
+    /** @brief AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */
+    RegAPENcsiChannel0Mcid_t NcsiChannel0Mcid;
+
+    /** @brief Set via NCSI ENABLE AEN. */
+    RegAPENcsiChannel0Aen_t NcsiChannel0Aen;
+
+    /** @brief  */
+    RegAPENcsiChannel0Bfilt_t NcsiChannel0Bfilt;
+
+    /** @brief  */
+    RegAPENcsiChannel0Mfilt_t NcsiChannel0Mfilt;
+
+    /** @brief This is the "Link Settings" value from NCSI Set Link. */
+    RegAPENcsiChannel0Setting1_t NcsiChannel0Setting1;
+
+    /** @brief This is the "OEM Settings" value from NCSI Set Link. */
+    RegAPENcsiChannel0Setting2_t NcsiChannel0Setting2;
+
+    /** @brief Receives VLAN mode from NCSI specification "Enable VLAN" command. */
+    RegAPENcsiChannel0Vlan_t NcsiChannel0Vlan;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18720[1];
+
+    /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */
+    RegAPENcsiChannel0AltHostMacHigh_t NcsiChannel0AltHostMacHigh;
+
+    /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */
+    RegAPENcsiChannel0AltHostMacMid_t NcsiChannel0AltHostMacMid;
+
+    /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */
+    RegAPENcsiChannel0AltHostMacLow_t NcsiChannel0AltHostMacLow;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18736[1];
+
+    /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac0High_t NcsiChannel0Mac0High;
+
+    /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac0Mid_t NcsiChannel0Mac0Mid;
+
+    /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac0Low_t NcsiChannel0Mac0Low;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18752[1];
+
+    /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac1High_t NcsiChannel0Mac1High;
+
+    /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac1Mid_t NcsiChannel0Mac1Mid;
+
+    /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac1Low_t NcsiChannel0Mac1Low;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18768[1];
+
+    /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac2High_t NcsiChannel0Mac2High;
+
+    /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac2Mid_t NcsiChannel0Mac2Mid;
+
+    /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac2Low_t NcsiChannel0Mac2Low;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18784[1];
+
+    /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac3High_t NcsiChannel0Mac3High;
+
+    /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac3Mid_t NcsiChannel0Mac3Mid;
+
+    /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */
+    RegAPENcsiChannel0Mac3Low_t NcsiChannel0Mac3Low;
+
+    /** @brief Nonzero indicates VLAN field is valid */
+    RegAPENcsiChannel0Mac0VlanValid_t NcsiChannel0Mac0VlanValid;
+
+    /** @brief  */
+    RegAPENcsiChannel0Mac0Vlan_t NcsiChannel0Mac0Vlan;
+
+    /** @brief Nonzero indicates VLAN field is valid */
+    RegAPENcsiChannel0Mac1VlanValid_t NcsiChannel0Mac1VlanValid;
+
+    /** @brief  */
+    RegAPENcsiChannel0Mac1Vlan_t NcsiChannel0Mac1Vlan;
+
+    /** @brief  */
+    RegAPENcsiChannel0Status_t NcsiChannel0Status;
+
+    /** @brief  */
+    RegAPENcsiChannel0ResetCount_t NcsiChannel0ResetCount;
+
+    /** @brief  */
+    RegAPENcsiChannel0Pxe_t NcsiChannel0Pxe;
+
+    /** @brief  */
+    RegAPENcsiChannel0Dropfil_t NcsiChannel0Dropfil;
+
+    /** @brief  */
+    RegAPENcsiChannel0Slink_t NcsiChannel0Slink;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18836[3];
+
+    /** @brief  */
+    RegAPENcsiChannel0Dbg_t NcsiChannel0Dbg;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18852[3];
+
+    /** @brief  */
+    RegAPENcsiChannel0CtrlstatRx_t NcsiChannel0CtrlstatRx;
+
+    /** @brief Reserved bytes to pad out data structure. */
+    BCM5719_APE_H_uint32_t reserved_18868[3731];
 
     /** @brief This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0). */
     RegAPEPerLockRequestPhy0_t PerLockRequestPhy0;
diff --git a/include/bcm5719_GEN.h b/include/bcm5719_GEN.h
index 2a4494c..58b382f 100644
--- a/include/bcm5719_GEN.h
+++ b/include/bcm5719_GEN.h
@@ -86,7 +86,7 @@ typedef uint32_t BCM5719_GEN_H_uint32_t;
 #define     GEN_GEN_FW_MBOX_MBOX_MASK  0xffffffffu
 #define GET_GEN_GEN_FW_MBOX_MBOX(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
 #define SET_GEN_GEN_FW_MBOX_MBOX(__val__)  (((__val__) << 0u) & 0xffffffffu)
-#define     GEN_GEN_FW_MBOX_MBOX_DRIVER_READY 0x4b657654u
+#define     GEN_GEN_FW_MBOX_MBOX_BOOTCODE_READY 0xb49a89abu
 
 
 /** @brief Register definition for @ref GEN_t.GenFwMbox. */
@@ -132,9 +132,9 @@ typedef register_container RegGENGenFwMbox_t {
 #define     GEN_GEN_DATA_SIG_SIG_MASK  0xffffffffu
 #define GET_GEN_GEN_DATA_SIG_SIG(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
 #define SET_GEN_GEN_DATA_SIG_SIG(__val__)  (((__val__) << 0u) & 0xffffffffu)
-#define     GEN_GEN_DATA_SIG_SIG_BOOTCODE_READY 0xb49a89abu
 #define     GEN_GEN_DATA_SIG_SIG_STAGE2_MAGIC_INVALID 0xbad0000u
 #define     GEN_GEN_DATA_SIG_SIG_STAGE2_CRC_INVALID 0xbad0001u
+#define     GEN_GEN_DATA_SIG_SIG_DRIVER_READY 0x4b657654u
 
 
 /** @brief Register definition for @ref GEN_t.GenDataSig. */
diff --git a/ipxact/bcm5719.xml b/ipxact/bcm5719.xml
index d90d0c2..71da3c8 100644
--- a/ipxact/bcm5719.xml
+++ b/ipxact/bcm5719.xml
@@ -32,8 +32,8 @@
                         <ipxact:enumeratedValues>
                             <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values -->
                             <ipxact:enumeratedValue>
-                                <ipxact:name>Driver Ready</ipxact:name>
-                                <ipxact:value>0x4B657654</ipxact:value>
+                                <ipxact:name>Bootcode Ready</ipxact:name>
+                                <ipxact:value>0xB49A89AB</ipxact:value>
                             </ipxact:enumeratedValue>
                         </ipxact:enumeratedValues>
                     </ipxact:field>
@@ -53,8 +53,8 @@
                         <ipxact:enumeratedValues>
                             <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values -->
                             <ipxact:enumeratedValue>
-                                <ipxact:name>Bootcode Ready</ipxact:name>
-                                <ipxact:value>0xB49A89AB</ipxact:value>
+                                <ipxact:name>Driver Ready</ipxact:name>
+                                <ipxact:value>0x4B657654</ipxact:value>
                             </ipxact:enumeratedValue>
                             <ipxact:enumeratedValue>
                                 <ipxact:name>Stage2 Magic Invalid</ipxact:name>
@@ -1498,6 +1498,20 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Sig</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>32</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                        <ipxact:enumeratedValues>
+                            <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values -->
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>RCPU_MAGIC</ipxact:name>
+                                <ipxact:value>0x52435055</ipxact:value>
+                            </ipxact:enumeratedValue>
+                        </ipxact:enumeratedValues>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>RCPU_SEG_LENGTH</ipxact:name>
@@ -1548,7 +1562,7 @@
                     <ipxact:volatile>true</ipxact:volatile>
                 </ipxact:register>
                 <ipxact:register>
-                    <ipxact:name>411C</ipxact:name>
+                    <ipxact:name>RCPU_APE_RESET_COUNT</ipxact:name>
                     <ipxact:description>Unknown. Incremented by frobnicating routine.</ipxact:description>
                     <ipxact:addressOffset>0x411c</ipxact:addressOffset>
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
@@ -1556,7 +1570,7 @@
                     <ipxact:volatile>true</ipxact:volatile>
                 </ipxact:register>
                 <ipxact:register>
-                    <ipxact:name>4120</ipxact:name>
+                    <ipxact:name>RCPU_LAST_APE_STATUS</ipxact:name>
                     <ipxact:description>Unknown. Written by frobnicating routine.</ipxact:description>
                     <ipxact:addressOffset>0x4120</ipxact:addressOffset>
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
@@ -1564,7 +1578,7 @@
                     <ipxact:volatile>true</ipxact:volatile>
                 </ipxact:register>
                 <ipxact:register>
-                    <ipxact:name>4124</ipxact:name>
+                    <ipxact:name>RCPU_LAST_APE_FW_STATUS</ipxact:name>
                     <ipxact:description>Unknown. </ipxact:description>
                     <ipxact:addressOffset>0x4124</ipxact:addressOffset>
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
@@ -1594,6 +1608,27 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Address</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>16</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                        <ipxact:enumeratedValues>
+                            <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values -->
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>ADDRESS</ipxact:name>
+                                <ipxact:value>0x362C</ipxact:value>
+                            </ipxact:enumeratedValue>
+                        </ipxact:enumeratedValues>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Status</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>16</ipxact:bitOffset>
+                        <ipxact:bitWidth>16</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>HOST_SEG_SIG</ipxact:name>
@@ -1832,6 +1867,562 @@
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
                 </ipxact:register>
+
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_INFO</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4900</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Enabled</ipxact:name>
+                        <ipxact:description>This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE.</ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>TX Passthrough</ipxact:name>
+                        <ipxact:description>TX passthrough has been enabled by BMC NCSI command.</ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Ready</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Init</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>MFILT</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>BFILT</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>5</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>SERDES</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>6</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>VLAN</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>8</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>B2H</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>10</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>B2N</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>11</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>EEE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>14</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>PDead</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>14</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MCID</ipxact:name>
+                    <ipxact:description>AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs.</ipxact:description>
+                    <ipxact:addressOffset>0x4904</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_AEN</ipxact:name>
+                    <ipxact:description>Set via NCSI ENABLE AEN.</ipxact:description>
+                    <ipxact:addressOffset>0x4908</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Enable Link Status Change AEN</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Enable Configuration Required AEN</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Enable Host NC Driver Status Change AEN</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_BFILT</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x490c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>ARP Packet</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>DHCP Client Packet</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>DHCP Server Packet</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>NetBIOS Packet</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MFILT</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4910</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>IPv6 Neighbour Advertisement</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>IPv6 Router Advertisement</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>DHCPv6 Relay and Server Multicast</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_SETTING_1</ipxact:name>
+                    <ipxact:description>This is the "Link Settings" value from NCSI Set Link.</ipxact:description>
+                    <ipxact:addressOffset>0x4914</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Autonegotiation enabled</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 10M enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 100M enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 100M enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 1000M enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 10G enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Half duplex enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>8</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Full duplex enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>9</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Pause capability enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>10</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Asymmetric pause capability enable</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>11</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>OEM link settings field valid</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_SETTING_2</ipxact:name>
+                    <ipxact:description>This is the "OEM Settings" value from NCSI Set Link.</ipxact:description>
+                    <ipxact:addressOffset>0x4918</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_VLAN</ipxact:name>
+                    <ipxact:description>Receives VLAN mode from NCSI specification "Enable VLAN" command.</ipxact:description>
+                    <ipxact:addressOffset>0x491c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_HIGH</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4924</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_MID</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4928</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_LOW</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x492c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC0_HIGH</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4934</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC0_MID</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4938</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC0_LOW</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x493c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC1_HIGH</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4944</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC1_MID</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4948</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC1_LOW</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x494c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC2_HIGH</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4954</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC2_MID</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4958</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC2_LOW</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x495c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC3_HIGH</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4964</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC3_MID</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x4968</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC3_LOW</ipxact:name>
+                    <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description>
+                    <ipxact:addressOffset>0x496c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN_VALID</ipxact:name>
+                    <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description>
+                    <ipxact:addressOffset>0x4970</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4974</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN_VALID</ipxact:name>
+                    <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description>
+                    <ipxact:addressOffset>0x4978</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x497c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_STATUS</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4980</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Link up</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Status</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>4</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>SERDES</ipxact:name>
+                        <ipxact:description>Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case.</ipxact:description>
+                        <ipxact:bitOffset>5</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Autonegotiation Complete</ipxact:name>
+                        <ipxact:description>Set if autonegotiation is complete.</ipxact:description>
+                        <ipxact:bitOffset>6</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 1000M Full Duplex Capable</ipxact:name>
+                        <ipxact:description>Link partner 1000BASE-T full duplex capable</ipxact:description>
+                        <ipxact:bitOffset>9</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Link Speed 1000M Hals Duplex Capable</ipxact:name>
+                        <ipxact:description>Link partner 1000BASE-T half duplex capable</ipxact:description>
+                        <ipxact:bitOffset>10</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_RESET_COUNT</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4984</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_PXE</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4988</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_DROPFIL</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x498c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_SLINK</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x4990</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_DBG</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x49a0</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NCSI_CHANNEL0_CTRLSTAT_RX</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x49b0</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                </ipxact:register>
+
+
+
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_PHY0</ipxact:name>
                     <ipxact:description>This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0).</ipxact:description>
@@ -1839,6 +2430,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_GRC</ipxact:name>
@@ -1847,7 +2480,49 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
-                </ipxact:register>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_PHY1</ipxact:name>
                     <ipxact:description></ipxact:description>
@@ -1855,6 +2530,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_PHY2</ipxact:name>
@@ -1863,6 +2580,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_MEM</ipxact:name>
@@ -1871,6 +2630,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_PHY3</ipxact:name>
@@ -1879,6 +2680,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_PORT6</ipxact:name>
@@ -1887,6 +2730,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_REQUEST_GPIO</ipxact:name>
@@ -1895,6 +2780,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_PHY0</ipxact:name>
@@ -1903,6 +2830,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_GRC</ipxact:name>
@@ -1911,6 +2880,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_PHY1</ipxact:name>
@@ -1919,6 +2930,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_PHY2</ipxact:name>
@@ -1935,6 +2988,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_PHY3</ipxact:name>
@@ -1943,6 +3038,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_PORT6</ipxact:name>
@@ -1951,6 +3088,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
                     <ipxact:name>PER_LOCK_GRANT_GPIO</ipxact:name>
@@ -1959,6 +3138,48 @@
                     <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
                     <ipxact:size>32</ipxact:size>
                     <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>APE</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 1</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>1</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 2</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>2</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Function 3</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>3</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Bootcode</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Driver</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>12</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
                 </ipxact:register>
             </ipxact:addressBlock>
             <ipxact:addressUnitBits>8</ipxact:addressUnitBits>
diff --git a/simulator/bcm5719_APE.cpp b/simulator/bcm5719_APE.cpp
index 55f5bcb..f1533cb 100644
--- a/simulator/bcm5719_APE.cpp
+++ b/simulator/bcm5719_APE.cpp
@@ -115,11 +115,11 @@ void init_bcm5719_APE(void)
 
     /** @brief Bitmap for @ref APE_t.RcpuPciSubsystemId. */
 
-    /** @brief Bitmap for @ref APE_t.411c. */
+    /** @brief Bitmap for @ref APE_t.RcpuApeResetCount. */
 
-    /** @brief Bitmap for @ref APE_t.4120. */
+    /** @brief Bitmap for @ref APE_t.RcpuLastApeStatus. */
 
-    /** @brief Bitmap for @ref APE_t.4124. */
+    /** @brief Bitmap for @ref APE_t.RcpuLastApeFwStatus. */
 
     /** @brief Bitmap for @ref APE_t.RcpuCfgHw. */
 
@@ -169,6 +169,74 @@ void init_bcm5719_APE(void)
 
     /** @brief Bitmap for @ref APE_t.ChipId. */
 
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Info. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mcid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Aen. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Bfilt. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mfilt. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting1. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting2. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Vlan. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacHigh. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacMid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacLow. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0High. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Mid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Low. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1High. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Mid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Low. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2High. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Mid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Low. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3High. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Mid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Low. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0VlanValid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Vlan. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1VlanValid. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Vlan. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Status. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0ResetCount. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Pxe. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Dropfil. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Slink. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Dbg. */
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0CtrlstatRx. */
+
     /** @brief Bitmap for @ref APE_t.PerLockRequestPhy0. */
 
     /** @brief Bitmap for @ref APE_t.PerLockRequestGrc. */
diff --git a/simulator/bcm5719_APE_mmap.cpp b/simulator/bcm5719_APE_mmap.cpp
index 2eebdf4..60aad9e 100644
--- a/simulator/bcm5719_APE_mmap.cpp
+++ b/simulator/bcm5719_APE_mmap.cpp
@@ -246,20 +246,20 @@ void init_bcm5719_APE_mmap(void *base)
     APE.RcpuPciSubsystemId.r32.installReadCallback(read_from_ram, &APE_RcpuPciSubsystemId_r32);
     APE.RcpuPciSubsystemId.r32.installWriteCallback(write_to_ram, &APE_RcpuPciSubsystemId_r32);
 
-    /** @brief Bitmap for @ref APE_t.411c. */
-    static ram_offset_t APE__411c_r32((uint8_t *)base, (uint32_t)16668);
-    APE._411c.r32.installReadCallback(read_from_ram, &APE__411c_r32);
-    APE._411c.r32.installWriteCallback(write_to_ram, &APE__411c_r32);
+    /** @brief Bitmap for @ref APE_t.RcpuApeResetCount. */
+    static ram_offset_t APE_RcpuApeResetCount_r32((uint8_t *)base, (uint32_t)16668);
+    APE.RcpuApeResetCount.r32.installReadCallback(read_from_ram, &APE_RcpuApeResetCount_r32);
+    APE.RcpuApeResetCount.r32.installWriteCallback(write_to_ram, &APE_RcpuApeResetCount_r32);
 
-    /** @brief Bitmap for @ref APE_t.4120. */
-    static ram_offset_t APE__4120_r32((uint8_t *)base, (uint32_t)16672);
-    APE._4120.r32.installReadCallback(read_from_ram, &APE__4120_r32);
-    APE._4120.r32.installWriteCallback(write_to_ram, &APE__4120_r32);
+    /** @brief Bitmap for @ref APE_t.RcpuLastApeStatus. */
+    static ram_offset_t APE_RcpuLastApeStatus_r32((uint8_t *)base, (uint32_t)16672);
+    APE.RcpuLastApeStatus.r32.installReadCallback(read_from_ram, &APE_RcpuLastApeStatus_r32);
+    APE.RcpuLastApeStatus.r32.installWriteCallback(write_to_ram, &APE_RcpuLastApeStatus_r32);
 
-    /** @brief Bitmap for @ref APE_t.4124. */
-    static ram_offset_t APE__4124_r32((uint8_t *)base, (uint32_t)16676);
-    APE._4124.r32.installReadCallback(read_from_ram, &APE__4124_r32);
-    APE._4124.r32.installWriteCallback(write_to_ram, &APE__4124_r32);
+    /** @brief Bitmap for @ref APE_t.RcpuLastApeFwStatus. */
+    static ram_offset_t APE_RcpuLastApeFwStatus_r32((uint8_t *)base, (uint32_t)16676);
+    APE.RcpuLastApeFwStatus.r32.installReadCallback(read_from_ram, &APE_RcpuLastApeFwStatus_r32);
+    APE.RcpuLastApeFwStatus.r32.installWriteCallback(write_to_ram, &APE_RcpuLastApeFwStatus_r32);
 
     /** @brief Bitmap for @ref APE_t.RcpuCfgHw. */
     static ram_offset_t APE_RcpuCfgHw_r32((uint8_t *)base, (uint32_t)16680);
@@ -381,6 +381,176 @@ void init_bcm5719_APE_mmap(void *base)
     APE.ChipId.r32.installReadCallback(read_from_ram, &APE_ChipId_r32);
     APE.ChipId.r32.installWriteCallback(write_to_ram, &APE_ChipId_r32);
 
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Info. */
+    static ram_offset_t APE_NcsiChannel0Info_r32((uint8_t *)base, (uint32_t)18688);
+    APE.NcsiChannel0Info.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Info_r32);
+    APE.NcsiChannel0Info.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Info_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mcid. */
+    static ram_offset_t APE_NcsiChannel0Mcid_r32((uint8_t *)base, (uint32_t)18692);
+    APE.NcsiChannel0Mcid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mcid_r32);
+    APE.NcsiChannel0Mcid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mcid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Aen. */
+    static ram_offset_t APE_NcsiChannel0Aen_r32((uint8_t *)base, (uint32_t)18696);
+    APE.NcsiChannel0Aen.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Aen_r32);
+    APE.NcsiChannel0Aen.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Aen_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Bfilt. */
+    static ram_offset_t APE_NcsiChannel0Bfilt_r32((uint8_t *)base, (uint32_t)18700);
+    APE.NcsiChannel0Bfilt.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Bfilt_r32);
+    APE.NcsiChannel0Bfilt.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Bfilt_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mfilt. */
+    static ram_offset_t APE_NcsiChannel0Mfilt_r32((uint8_t *)base, (uint32_t)18704);
+    APE.NcsiChannel0Mfilt.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mfilt_r32);
+    APE.NcsiChannel0Mfilt.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mfilt_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting1. */
+    static ram_offset_t APE_NcsiChannel0Setting1_r32((uint8_t *)base, (uint32_t)18708);
+    APE.NcsiChannel0Setting1.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Setting1_r32);
+    APE.NcsiChannel0Setting1.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Setting1_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting2. */
+    static ram_offset_t APE_NcsiChannel0Setting2_r32((uint8_t *)base, (uint32_t)18712);
+    APE.NcsiChannel0Setting2.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Setting2_r32);
+    APE.NcsiChannel0Setting2.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Setting2_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Vlan. */
+    static ram_offset_t APE_NcsiChannel0Vlan_r32((uint8_t *)base, (uint32_t)18716);
+    APE.NcsiChannel0Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Vlan_r32);
+    APE.NcsiChannel0Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Vlan_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacHigh. */
+    static ram_offset_t APE_NcsiChannel0AltHostMacHigh_r32((uint8_t *)base, (uint32_t)18724);
+    APE.NcsiChannel0AltHostMacHigh.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacHigh_r32);
+    APE.NcsiChannel0AltHostMacHigh.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacHigh_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacMid. */
+    static ram_offset_t APE_NcsiChannel0AltHostMacMid_r32((uint8_t *)base, (uint32_t)18728);
+    APE.NcsiChannel0AltHostMacMid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacMid_r32);
+    APE.NcsiChannel0AltHostMacMid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacMid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacLow. */
+    static ram_offset_t APE_NcsiChannel0AltHostMacLow_r32((uint8_t *)base, (uint32_t)18732);
+    APE.NcsiChannel0AltHostMacLow.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacLow_r32);
+    APE.NcsiChannel0AltHostMacLow.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacLow_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0High. */
+    static ram_offset_t APE_NcsiChannel0Mac0High_r32((uint8_t *)base, (uint32_t)18740);
+    APE.NcsiChannel0Mac0High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0High_r32);
+    APE.NcsiChannel0Mac0High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0High_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Mid. */
+    static ram_offset_t APE_NcsiChannel0Mac0Mid_r32((uint8_t *)base, (uint32_t)18744);
+    APE.NcsiChannel0Mac0Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Mid_r32);
+    APE.NcsiChannel0Mac0Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Mid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Low. */
+    static ram_offset_t APE_NcsiChannel0Mac0Low_r32((uint8_t *)base, (uint32_t)18748);
+    APE.NcsiChannel0Mac0Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Low_r32);
+    APE.NcsiChannel0Mac0Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Low_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1High. */
+    static ram_offset_t APE_NcsiChannel0Mac1High_r32((uint8_t *)base, (uint32_t)18756);
+    APE.NcsiChannel0Mac1High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1High_r32);
+    APE.NcsiChannel0Mac1High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1High_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Mid. */
+    static ram_offset_t APE_NcsiChannel0Mac1Mid_r32((uint8_t *)base, (uint32_t)18760);
+    APE.NcsiChannel0Mac1Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Mid_r32);
+    APE.NcsiChannel0Mac1Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Mid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Low. */
+    static ram_offset_t APE_NcsiChannel0Mac1Low_r32((uint8_t *)base, (uint32_t)18764);
+    APE.NcsiChannel0Mac1Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Low_r32);
+    APE.NcsiChannel0Mac1Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Low_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2High. */
+    static ram_offset_t APE_NcsiChannel0Mac2High_r32((uint8_t *)base, (uint32_t)18772);
+    APE.NcsiChannel0Mac2High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2High_r32);
+    APE.NcsiChannel0Mac2High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2High_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Mid. */
+    static ram_offset_t APE_NcsiChannel0Mac2Mid_r32((uint8_t *)base, (uint32_t)18776);
+    APE.NcsiChannel0Mac2Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2Mid_r32);
+    APE.NcsiChannel0Mac2Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2Mid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Low. */
+    static ram_offset_t APE_NcsiChannel0Mac2Low_r32((uint8_t *)base, (uint32_t)18780);
+    APE.NcsiChannel0Mac2Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2Low_r32);
+    APE.NcsiChannel0Mac2Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2Low_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3High. */
+    static ram_offset_t APE_NcsiChannel0Mac3High_r32((uint8_t *)base, (uint32_t)18788);
+    APE.NcsiChannel0Mac3High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3High_r32);
+    APE.NcsiChannel0Mac3High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3High_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Mid. */
+    static ram_offset_t APE_NcsiChannel0Mac3Mid_r32((uint8_t *)base, (uint32_t)18792);
+    APE.NcsiChannel0Mac3Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3Mid_r32);
+    APE.NcsiChannel0Mac3Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3Mid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Low. */
+    static ram_offset_t APE_NcsiChannel0Mac3Low_r32((uint8_t *)base, (uint32_t)18796);
+    APE.NcsiChannel0Mac3Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3Low_r32);
+    APE.NcsiChannel0Mac3Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3Low_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0VlanValid. */
+    static ram_offset_t APE_NcsiChannel0Mac0VlanValid_r32((uint8_t *)base, (uint32_t)18800);
+    APE.NcsiChannel0Mac0VlanValid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0VlanValid_r32);
+    APE.NcsiChannel0Mac0VlanValid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0VlanValid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Vlan. */
+    static ram_offset_t APE_NcsiChannel0Mac0Vlan_r32((uint8_t *)base, (uint32_t)18804);
+    APE.NcsiChannel0Mac0Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Vlan_r32);
+    APE.NcsiChannel0Mac0Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Vlan_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1VlanValid. */
+    static ram_offset_t APE_NcsiChannel0Mac1VlanValid_r32((uint8_t *)base, (uint32_t)18808);
+    APE.NcsiChannel0Mac1VlanValid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1VlanValid_r32);
+    APE.NcsiChannel0Mac1VlanValid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1VlanValid_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Vlan. */
+    static ram_offset_t APE_NcsiChannel0Mac1Vlan_r32((uint8_t *)base, (uint32_t)18812);
+    APE.NcsiChannel0Mac1Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Vlan_r32);
+    APE.NcsiChannel0Mac1Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Vlan_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Status. */
+    static ram_offset_t APE_NcsiChannel0Status_r32((uint8_t *)base, (uint32_t)18816);
+    APE.NcsiChannel0Status.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Status_r32);
+    APE.NcsiChannel0Status.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Status_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0ResetCount. */
+    static ram_offset_t APE_NcsiChannel0ResetCount_r32((uint8_t *)base, (uint32_t)18820);
+    APE.NcsiChannel0ResetCount.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0ResetCount_r32);
+    APE.NcsiChannel0ResetCount.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0ResetCount_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Pxe. */
+    static ram_offset_t APE_NcsiChannel0Pxe_r32((uint8_t *)base, (uint32_t)18824);
+    APE.NcsiChannel0Pxe.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Pxe_r32);
+    APE.NcsiChannel0Pxe.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Pxe_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Dropfil. */
+    static ram_offset_t APE_NcsiChannel0Dropfil_r32((uint8_t *)base, (uint32_t)18828);
+    APE.NcsiChannel0Dropfil.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Dropfil_r32);
+    APE.NcsiChannel0Dropfil.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Dropfil_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Slink. */
+    static ram_offset_t APE_NcsiChannel0Slink_r32((uint8_t *)base, (uint32_t)18832);
+    APE.NcsiChannel0Slink.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Slink_r32);
+    APE.NcsiChannel0Slink.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Slink_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0Dbg. */
+    static ram_offset_t APE_NcsiChannel0Dbg_r32((uint8_t *)base, (uint32_t)18848);
+    APE.NcsiChannel0Dbg.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Dbg_r32);
+    APE.NcsiChannel0Dbg.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Dbg_r32);
+
+    /** @brief Bitmap for @ref APE_t.NcsiChannel0CtrlstatRx. */
+    static ram_offset_t APE_NcsiChannel0CtrlstatRx_r32((uint8_t *)base, (uint32_t)18864);
+    APE.NcsiChannel0CtrlstatRx.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0CtrlstatRx_r32);
+    APE.NcsiChannel0CtrlstatRx.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0CtrlstatRx_r32);
+
     /** @brief Bitmap for @ref APE_t.PerLockRequestPhy0. */
     static ram_offset_t APE_PerLockRequestPhy0_r32((uint8_t *)base, (uint32_t)33792);
     APE.PerLockRequestPhy0.r32.installReadCallback(read_from_ram, &APE_PerLockRequestPhy0_r32);