1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
{
"context" : "{ [] }",
"name" : "%1 => %17",
"statements" : [
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_4[i0, i1] -> MemRef_C[1536i0 + i1] }"
}
],
"domain" : "{ Stmt_4[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 }",
"name" : "Stmt_4",
"schedule" : "{ Stmt_4[i0, i1] -> schedule[0, i0, 0, i1, 0, 0, 0] }"
},
{
"accesses" : [
{
"kind" : "read",
"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_C[1536i0 + i1] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_A[1536i0 + i2] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_B[i1 + 1536i2] }"
},
{
"kind" : "write",
"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_C[1536i0 + i1] }"
}
],
"domain" : "{ Stmt_6[i0, i1, i2] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 and i2 >= 0 and i2 <= 1023 }",
"name" : "Stmt_6",
"schedule" : "{ Stmt_6[i0, i1, i2] -> schedule[1, o0, o1, o2, i0, i2, i1]: o0 <= i0 < o0 + 64 and o1 <= i1 < o1 + 64 and o2 <= i2 < o2 + 64 and o0 % 64 = 0 and o1 % 64 = 0 and o2 % 64 = 0 }"
}
]
}
|
