1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
{
"arrays" : [
{
"name" : "MemRef_xptr",
"sizes" : [ "*" ],
"type" : "i64"
},
{
"name" : "MemRef_B",
"sizes" : [ "*" ],
"type" : "float"
}
],
"context" : "{ : }",
"name" : "%bb1---%bb14",
"statements" : [
{
"accesses" : [
{
"kind" : "read",
"relation" : "{ Stmt_bb2[i0] -> MemRef_xptr[0] }"
},
{
"kind" : "write",
"relation" : "{ Stmt_bb2[i0] -> MemRef_j_0__phi[] }"
}
],
"domain" : "{ Stmt_bb2[i0] : 0 <= i0 <= 1023 }",
"name" : "Stmt_bb2",
"schedule" : "{ Stmt_bb2[i0] -> [i0, 0] }"
},
{
"accesses" : [
{
"kind" : "read",
"relation" : "{ Stmt_bb3__TO__bb11[i0] -> MemRef_j_0__phi[] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_bb3__TO__bb11[i0] -> MemRef_B[42] }"
},
{
"kind" : "write",
"relation" : "{ Stmt_bb3__TO__bb11[i0] -> MemRef_B[42] }"
}
],
"domain" : "{ Stmt_bb3__TO__bb11[i0] : 0 <= i0 <= 1023 }",
"name" : "Stmt_bb3__TO__bb11",
"schedule" : "{ Stmt_bb3__TO__bb11[i0] -> [i0, 1] }"
}
]
}
|
