summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/pr43509.ll
blob: 4243764d08cf71fbc2fea2bd15e224402cb354a1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s

define <8 x i8> @foo(<8 x float> %arg) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %bb
; CHECK-NEXT:    vcmpgtps {{.*}}(%rip){1to8}, %ymm0, %k0
; CHECK-NEXT:    vpmovm2b %k0, %xmm1
; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT:    vcmpltps %ymm2, %ymm0, %k1
; CHECK-NEXT:    vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
; CHECK-NEXT:    vpand %xmm0, %xmm1, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
bb:
  %tmp = xor <8 x i8> zeroinitializer, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  %tmp1 = fcmp reassoc nsz contract ogt <8 x float> %arg, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
  %tmp2 = zext <8 x i1> %tmp1 to <8 x i8>
  %tmp3 = and <8 x i8> %tmp, %tmp2
  %tmp4 = fcmp reassoc nsz contract ogt <8 x float> zeroinitializer, %arg
  %tmp5 = or <8 x i1> zeroinitializer, %tmp4
  %tmp6 = zext <8 x i1> %tmp5 to <8 x i8>
  %tmp7 = and <8 x i8> %tmp3, %tmp6
  ret <8 x i8> %tmp7
}
OpenPOWER on IntegriCloud