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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) {
; CHECK-LABEL: abs_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s8 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <16 x i8> %s1, zeroinitializer
%1 = sub nsw <16 x i8> zeroinitializer, %s1
%2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %s1
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @abs_v8i16(<8 x i16> %s1) {
; CHECK-LABEL: abs_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <8 x i16> %s1, zeroinitializer
%1 = sub nsw <8 x i16> zeroinitializer, %s1
%2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %s1
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @abs_v4i32(<4 x i32> %s1) {
; CHECK-LABEL: abs_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabs.s32 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = icmp slt <4 x i32> %s1, zeroinitializer
%1 = sub nsw <4 x i32> zeroinitializer, %s1
%2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
; CHECK-LABEL: abs_v2i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vmov r12, s2
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: rsbs.w r3, r12, #0
; CHECK-NEXT: sbc.w lr, r2, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it mi
; CHECK-NEXT: movmi r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq lr, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: rsbs r5, r4, #0
; CHECK-NEXT: sbc.w r6, r2, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it mi
; CHECK-NEXT: movmi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r6, r0
; CHECK-NEXT: moveq r5, r4
; CHECK-NEXT: vmov.32 q0[0], r5
; CHECK-NEXT: vmov.32 q0[1], r6
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r3, r12
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: pop {r4, r5, r6, pc}
entry:
%0 = icmp slt <2 x i64> %s1, zeroinitializer
%1 = sub nsw <2 x i64> zeroinitializer, %s1
%2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1
ret <2 x i64> %2
}
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