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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
--- |
; Function Attrs: nofree norecurse nounwind
define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 {
bb:
%tmp = icmp eq i32 %arg2, 0
%tmp1 = add i32 %arg2, 3
%tmp2 = lshr i32 %tmp1, 2
%tmp3 = shl nuw i32 %tmp2, 2
%tmp4 = add i32 %tmp3, -4
%tmp5 = lshr i32 %tmp4, 2
%tmp6 = add nuw nsw i32 %tmp5, 1
%conv.mask = zext i16 %mask to i32
%invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
br i1 %tmp, label %bb27, label %bb3
bb3: ; preds = %bb
call void @llvm.set.loop.iterations.i32(i32 %tmp6)
br label %bb9
bb9: ; preds = %bb9, %bb3
%lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
%lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ]
%tmp7 = phi i32 [ %tmp6, %bb3 ], [ %tmp12, %bb9 ]
%tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
%lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>*
%lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
%vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
%and = and <4 x i1> %vctp, %invariant.mask
%tmp11 = sub i32 %tmp8, 4
%tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef), !tbaa !3
%tmp18 = icmp ne <4 x i32> %tmp17, zeroinitializer
%tmp20 = and <4 x i1> %tmp18, %vctp
%tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %tmp20, <4 x i32> undef), !tbaa !3
%tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %tmp20), !tbaa !3
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
%tmp13 = icmp ne i32 %tmp12, 0
%scevgep = getelementptr i32, i32* %lsr.iv, i32 4
%scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4
br i1 %tmp13, label %bb9, label %bb27, !llvm.loop !7
bb27: ; preds = %bb9, %bb
ret void
}
; Function Attrs: argmemonly nounwind readonly willreturn
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1
; Function Attrs: argmemonly nounwind willreturn
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2
; Function Attrs: noduplicate nounwind
declare void @llvm.set.loop.iterations.i32(i32) #3
; Function Attrs: noduplicate nounwind
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
; Function Attrs: nounwind readnone
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
; Function Attrs: nounwind readnone
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #4
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #5
attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+mve" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind readonly willreturn "target-features"="+mve" }
attributes #2 = { argmemonly nounwind willreturn "target-features"="+mve" }
attributes #3 = { noduplicate nounwind "target-features"="+mve" }
attributes #4 = { nounwind readnone "target-features"="+mve" }
attributes #5 = { nounwind }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"min_enum_size", i32 4}
!2 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 8f92f97150cbdd3b9f569570b8377db78ed61a9e)"}
!3 = !{!4, !4, i64 0}
!4 = !{!"int", !5, i64 0}
!5 = !{!"omnipotent char", !6, i64 0}
!6 = !{!"Simple C/C++ TBAA"}
!7 = distinct !{!7, !8}
!8 = !{!"llvm.loop.isvectorized", i32 1}
...
---
name: test
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 12
offsetAdjustment: -4
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.bb:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $lr
; CHECK: frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr $sp, 14, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.bb3:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
; CHECK: $lr = t2DLS renamable $lr
; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4, !tbaa !3)
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4, !tbaa !3)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3)
; CHECK: $r0 = tMOVr $r3, 14, $noreg
; CHECK: $lr = t2LEUpdate renamable $lr, %bb.2
; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14, $noreg
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr
frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7
$sp = frame-setup tSUBspi $sp, 1, 14, $noreg
tCBZ $r2, %bb.3
bb.1.bb3:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3
renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg
renamable $lr = t2MOVi 1, 14, $noreg, $noreg
renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
$vpr = VMSR_P0 killed $r3, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
$r3 = tMOVr $r0, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
t2DoLoopStart renamable $lr
bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4, !tbaa !3)
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4, !tbaa !3)
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3)
renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg
bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc
...
|
