1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; These tests are each targeted at a particular RISC-V ALU instruction. Other
; files in this folder exercise LLVM IR instructions that don't directly match a
; RISC-V instruction
; Register-immediate instructions
define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
}
define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, 2
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, 3
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, 3
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 4
; RV32I-NEXT: ret
%1 = xor i32 %a, 4
ret i32 %1
}
define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 5
; RV32I-NEXT: ret
%1 = or i32 %a, 5
ret i32 %1
}
define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 6
; RV32I-NEXT: ret
%1 = and i32 %a, 6
ret i32 %1
}
define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
}
define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: ret
%1 = lshr i32 %a, 8
ret i32 %1
}
define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a0, a0, 9
; RV32I-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
}
; Register-register instructions
define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: ret
%1 = xor i32 %a, %b
ret i32 %1
}
define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
; RV32I-NEXT: sra a0, a0, a1
; RV32I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
; RV32I: # %bb.0:
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
%1 = or i32 %a, %b
ret i32 %1
}
define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
%1 = and i32 %a, %b
ret i32 %1
}
|
