1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
declare i32 @llvm.bitreverse.i32(i32)
define i32 @testBitReverseIntrinsicI32(i32 %arg) {
; CHECK-LABEL: testBitReverseIntrinsicI32:
; CHECK: # BB#0:
; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1
; CHECK-NEXT: lis 7, -13108
; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: lis 10, -3856
; CHECK-NEXT: lis 11, 3855
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: ori 5, 8, 13107
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: ori 4, 7, 52428
; CHECK-NEXT: slwi 9, 3, 2
; CHECK-NEXT: srwi 3, 3, 2
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: and 4, 9, 4
; CHECK-NEXT: ori 5, 11, 3855
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: ori 4, 10, 61680
; CHECK-NEXT: slwi 12, 3, 4
; CHECK-NEXT: srwi 3, 3, 4
; CHECK-NEXT: and 4, 12, 4
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24
; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
; CHECK-NEXT: rldicl 3, 4, 0, 32
; CHECK-NEXT: blr
%res = call i32 @llvm.bitreverse.i32(i32 %arg)
ret i32 %res
}
|
