llvm/test/CodeGen/MIR/X86/named-registers.mir


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
# This test ensures that the MIR parser parses X86 registers correctly.

--- |

  define i32 @foo() {
  entry:
    ret i32 0
  }

...
---
# CHECK: name: foo
name:            foo
body:
 - name:         entry
   instructions:
     # CHECK:      - '%eax = MOV32r0
     # CHECK-NEXT: - 'RETQ %eax
     - '%eax = MOV32r0'
     - 'RETQ %eax'
...