llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir


1
2
3
4
5
6
7
8
9
10
11
12

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :7:27: expected a named register
# CHECK: scratchWaveOffsetReg:  ''
---
name: empty_scratch_wave_offset_reg
machineFunctionInfo:
  scratchWaveOffsetReg:  ''
body:             |
  bb.0:

    S_ENDPGM
...