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path: root/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s

---
name: test_fptosi_s32_to_s32
body: |
  bb.0:
    liveins: $vgpr0

    ; SI-LABEL: name: test_fptosi_s32_to_s32
    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
    ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
    ; VI-LABEL: name: test_fptosi_s32_to_s32
    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
    ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_FPTOSI %0
    $vgpr0 = COPY %1
...

---
name: test_fptosi_s64_to_s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_fptosi_s64_to_s32
    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
    ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
    ; VI-LABEL: name: test_fptosi_s64_to_s32
    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
    ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_FPTOSI %0
    $vgpr0 = COPY %1
...

---
name: test_fptosi_v2s32_to_v2s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_fptosi_v2s32_to_v2s32
    ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s32)
    ; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s32)
    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
    ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    ; VI-LABEL: name: test_fptosi_v2s32_to_v2s32
    ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s32)
    ; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s32)
    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
    ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s32>) = G_FPTOSI %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_fptosi_v2s64_to_v2s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; SI-LABEL: name: test_fptosi_v2s64_to_v2s32
    ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
    ; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
    ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    ; VI-LABEL: name: test_fptosi_v2s64_to_v2s32
    ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
    ; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
    ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(<2 x s32>) = G_FPTOSI %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_fptosi_s16_to_s16
body: |
  bb.0:
    liveins: $vgpr0

    ; SI-LABEL: name: test_fptosi_s16_to_s16
    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
    ; SI: $vgpr0 = COPY [[COPY1]](s32)
    ; VI-LABEL: name: test_fptosi_s16_to_s16
    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; VI: [[FPTOSI:%[0-9]+]]:_(s16) = G_FPTOSI [[TRUNC]](s16)
    ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTOSI]](s16)
    ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0
    %2:_(s16) = G_FPTOSI %1
    %3:_(s32) = G_ANYEXT %2
    $vgpr0 = COPY %3
...

---
name: test_fptosi_s32_to_s16
body: |
  bb.0:
    liveins: $vgpr0

    ; SI-LABEL: name: test_fptosi_s32_to_s16
    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
    ; SI: $vgpr0 = COPY [[COPY1]](s32)
    ; VI-LABEL: name: test_fptosi_s32_to_s16
    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
    ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
    ; VI: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_FPTOSI %0
    %2:_(s32) = G_ANYEXT %1
    $vgpr0 = COPY %2
...

---
name: test_fptosi_s64_to_s16
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; SI-LABEL: name: test_fptosi_s64_to_s16
    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
    ; SI: $vgpr0 = COPY [[COPY1]](s32)
    ; VI-LABEL: name: test_fptosi_s64_to_s16
    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
    ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
    ; VI: $vgpr0 = COPY [[COPY1]](s32)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s16) = G_FPTOSI %0
    %2:_(s32) = G_ANYEXT %1
    $vgpr0 = COPY %2
...
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