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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
---
name: ffbh_u32_s32_s_s
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ffbh_u32_s32_s_s
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_FLBIT_I32_B32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B32 [[COPY]]
; CHECK: S_ENDPGM 0, implicit [[S_FLBIT_I32_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_AMDGPU_FFBH_U32 %0
S_ENDPGM 0, implicit %1
...
---
name: ffbh_u32_s32_v_v
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: ffbh_u32_s32_v_v
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
S_ENDPGM 0, implicit %1
...
---
name: ffbh_u32_v_s
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ffbh_u32_v_s
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
S_ENDPGM 0, implicit %1
...
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