summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
blob: 38e770eeb404d65f3041af81430807df6c6e7b9f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
# RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mattr=+reserve-x10 \
# RUN:     -mattr=+reserve-x11 -mattr=+reserve-x15 -mtriple=arm64-apple-iphoneos -verify-machineinstrs \
# RUN:     -o - %s | FileCheck --check-prefix=CHECK --check-prefix=PRESERVED %s

# RUN: llc -run-pass=aarch64-ldst-opt -aarch64-load-store-renaming=true -mtriple=arm64-apple-iphoneos \
# RUN:     -verify-machineinstrs -o - %s | FileCheck --check-prefix=CHECK --check-prefix=NOPRES %s


# Make sure we do not pick reserved registers. For test1, we would pick x10,
# and for test2 we would pick x15, both of which are reserved.
#
---
# CHECK-LABEL: name: test1
# CHECK:       bb.0:
# CHECK-NEXT:     liveins: $x0, $x1
# PRESERVED:      $x12, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
# NOPRES:         $x10, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
# CHECK-NEXT:     renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
# CHECK-NEXT:     STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
# CHECK-NEXT:     renamable $x8 = ADDXrr $x8, $x8
# PRESERVED-NEXT: STPXi renamable $x8, killed $x12, renamable $x0, 10 :: (store 8, align 4)
# NOPRES-NEXT:    STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store 8, align 4)
# CHECK-NEXT:     RET undef $lr

name:            test1
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
  - { reg: '$x1' }
  - { reg: '$x8' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1
    renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
    STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
    renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
    STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
    renamable $x8 = ADDXrr $x8, $x8
    STRXui renamable $x8, renamable $x0, 10 :: (store 8, align 4)
    RET undef $lr

...
# CHECK-LABEL: name: test2
# CHECK:       bb.0:
# CHECK-NEXT:     liveins: $x0, $x1, $x10, $x11, $x12, $x13
# CHECK:          renamable $w19 = LDRWui renamable $x0, 0 :: (load 8)
# PRESERVED-NEXT: $x18, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
# NOPRES-NEXT:    $x15, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
# CHECK-NEXT:     renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
# CHECK-NEXT:     renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
# PRESERVED-NEXT: STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store 8, align 4)
# NOPRES-NEXT:    STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store 8, align 4)
# CHECK-NEXT:     STRXui killed renamable $x14, renamable $x0, 200 :: (store 8, align 4)
# CHECK-NEXT:     renamable $w8 = ADDWrr $w19, $w19
# CHECK-NEXT:     STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
# CHECK-NEXT:     RET undef $lr
#
name:            test2
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
  - { reg: '$x1' }
  - { reg: '$x8' }
frameInfo:
  maxAlignment:    1
  maxCallFrameSize: 0
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1, $x10, $x11, $x12, $x13
    renamable $w19 = LDRWui renamable $x0, 0 :: (load 8)
    renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
    STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
    renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
    renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
    STRXui renamable $x9, renamable $x0, 10 :: (store 8, align 4)
    STRXui renamable killed $x14, renamable $x0, 200 :: (store 8, align 4)
    renamable $w8 = ADDWrr $w19, $w19
    STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
    RET undef $lr

...
---
OpenPOWER on IntegriCloud