1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
//===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements the targeting of the Machinelegalizer class for Mips.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#include "MipsLegalizerInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
using namespace llvm;
MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
using namespace TargetOpcode;
const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64);
const LLT p0 = LLT::pointer(0, 32);
getActionDefinitionsBuilder(G_ADD)
.legalFor({s32})
.minScalar(0, s32)
.customFor({s64});
getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForCartesianProduct({p0, s32}, {p0});
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR})
.legalFor({s32});
getActionDefinitionsBuilder(G_ICMP)
.legalFor({{s32, s32}})
.minScalar(0, s32);
getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({s32})
.minScalar(0, s32)
.customFor({s64});
getActionDefinitionsBuilder(G_GEP)
.legalFor({{p0, s32}});
getActionDefinitionsBuilder(G_FRAME_INDEX)
.legalFor({p0});
getActionDefinitionsBuilder(G_GLOBAL_VALUE)
.legalFor({p0});
computeTables();
verify(*ST.getInstrInfo());
}
bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const {
using namespace TargetOpcode;
MIRBuilder.setInstr(MI);
switch (MI.getOpcode()) {
case G_ADD: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
const LLT sHalf = LLT::scalar(Size / 2);
unsigned RHSLow = MRI.createGenericVirtualRegister(sHalf);
unsigned RHSHigh = MRI.createGenericVirtualRegister(sHalf);
unsigned LHSLow = MRI.createGenericVirtualRegister(sHalf);
unsigned LHSHigh = MRI.createGenericVirtualRegister(sHalf);
unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
unsigned Carry = MRI.createGenericVirtualRegister(sHalf);
unsigned TmpResHigh = MRI.createGenericVirtualRegister(sHalf);
MIRBuilder.buildUnmerge({RHSHigh, RHSLow}, MI.getOperand(2).getReg());
MIRBuilder.buildUnmerge({LHSHigh, LHSLow}, MI.getOperand(1).getReg());
MIRBuilder.buildAdd(TmpResHigh, LHSHigh, RHSHigh);
MIRBuilder.buildAdd(ResLow, LHSLow, RHSLow);
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow);
MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry);
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow});
MI.eraseFromParent();
break;
}
case G_CONSTANT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
const LLT sHalf = LLT::scalar(Size / 2);
const APInt &CImmValue = MI.getOperand(1).getCImm()->getValue();
unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
MIRBuilder.buildConstant(
ResLow, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
CImmValue.trunc(Size / 2)));
MIRBuilder.buildConstant(
ResHigh, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
CImmValue.lshr(Size / 2).trunc(Size / 2)));
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow});
MI.eraseFromParent();
break;
}
default:
return false;
}
return true;
}
|
