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//===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file defines all the static objects used by AArch64RegisterBankInfo.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#ifndef LLVM_BUILD_GLOBAL_ISEL
#error "You shouldn't build this"
#endif
namespace llvm {
namespace AArch64 {
const uint32_t GPRCoverageData[] = {
// Classes 0-31
(1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |
(1u << AArch64::GPR32spRegClassID) |
(1u << AArch64::GPR32commonRegClassID) |
(1u << AArch64::GPR32sponlyRegClassID) |
(1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |
(1u << AArch64::GPR64spRegClassID) |
(1u << AArch64::GPR64commonRegClassID) |
(1u << AArch64::tcGPR64RegClassID) |
(1u << AArch64::GPR64sponlyRegClassID),
// Classes 32-63
0,
// FIXME: The entries below this point can be safely removed once this is
// tablegenerated. It's only needed because of the hardcoded register class
// limit.
// Classes 64-96
0,
// Classes 97-128
0,
// Classes 129-160
0,
// Classes 161-192
0,
// Classes 193-224
0,
};
const uint32_t FPRCoverageData[] = {
// Classes 0-31
(1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |
(1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |
(1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |
(1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |
(1u << AArch64::DDDDRegClassID),
// Classes 32-63
(1u << (AArch64::QQRegClassID - 32)) |
(1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
(1u
<< (AArch64::
QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID -
32)) |
(1u << (AArch64::QQQQRegClassID - 32)) |
(1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID - 32)) |
(1u
<< (AArch64::
QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID -
32)) |
(1u
<< (AArch64::
QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID -
32)) |
(1u << (AArch64::QQQRegClassID - 32)) |
(1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID - 32)) |
(1u << (AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID - 32)) |
(1u
<< (AArch64::
QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID -
32)),
// FIXME: The entries below this point can be safely removed once this
// is tablegenerated. It's only needed because of the hardcoded register
// class limit.
// Classes 64-96
0,
// Classes 97-128
0,
// Classes 129-160
0,
// Classes 161-192
0,
// Classes 193-224
0,
};
const uint32_t CCRCoverageData[] = {
// Classes 0-31
1u << AArch64::CCRRegClassID,
// Classes 32-63
0,
// FIXME: The entries below this point can be safely removed once this
// is tablegenerated. It's only needed because of the hardcoded register
// class limit.
// Classes 64-96
0,
// Classes 97-128
0,
// Classes 129-160
0,
// Classes 161-192
0,
// Classes 193-224
0,
};
RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
} // end namespace AArch64
RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
&AArch64::GPRRegBank, &AArch64::FPRRegBank, &AArch64::CCRRegBank};
RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
// 0: GPR 32-bit value.
{0, 32, AArch64::GPRRegBank},
// 1: GPR 64-bit value.
{0, 64, AArch64::GPRRegBank},
// 2: FPR 32-bit value.
{0, 32, AArch64::FPRRegBank},
// 3: FPR 64-bit value.
{0, 64, AArch64::FPRRegBank},
// 4: FPR 128-bit value.
{0, 128, AArch64::FPRRegBank},
// 5: FPR 256-bit value.
{0, 256, AArch64::FPRRegBank},
// 6: FPR 512-bit value.
{0, 512, AArch64::FPRRegBank}};
// ValueMappings.
RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
/* BreakDown, NumBreakDowns */
// 3-operands instructions (all binary operations should end up with one of
// those mapping).
// 0: GPR 32-bit value. <-- This must match First3OpsIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
// 3: GPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
// 6: FPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
// 9: FPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
// 12: FPR 128-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
// 15: FPR 256-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
// 18: FPR 512-bit value. <-- This must match Last3OpsIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
// Cross register bank copies.
// 21: GPR 32-bit value to FPR 32-bit value. <-- This must match
// FirstCrossRegCpyIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
// 23: GPR 64-bit value to FPR 64-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
// 25: FPR 32-bit value to GPR 32-bit value.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
// 27: FPR 64-bit value to GPR 64-bit value. <-- This must match
// LastCrossRegCpyIdx.
{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}
};
bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
unsigned ValStartIdx,
unsigned ValLength,
const RegisterBank &RB) {
const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
Map.RegBank == &RB;
}
bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
unsigned FirstInBank,
unsigned Size,
unsigned Offset) {
unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
const ValueMapping &Map =
AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
Map.NumBreakDowns == 1;
}
bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
ArrayRef<PartialMappingIdx> Order) {
if (Order.front() != FirstAlias)
return false;
if (Order.back() != LastAlias)
return false;
if (Order.front() > Order.back())
return false;
PartialMappingIdx Previous = Order.front();
bool First = true;
for (const auto &Current : Order) {
if (First) {
First = false;
continue;
}
if (Previous + 1 != Current)
return false;
Previous = Current;
}
return true;
}
unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
unsigned Size) {
if (RBIdx == PMI_FirstGPR) {
if (Size <= 32)
return 0;
if (Size <= 64)
return 1;
llvm_unreachable("Unexpected size");
}
if (RBIdx == PMI_FirstFPR) {
if (Size <= 32)
return 0;
if (Size <= 64)
return 1;
if (Size <= 128)
return 2;
if (Size <= 256)
return 3;
if (Size <= 512)
return 4;
llvm_unreachable("Unexpected size");
}
llvm_unreachable("Unexpected bank");
}
const RegisterBankInfo::ValueMapping *
AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
unsigned Size) {
assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
unsigned ValMappingIdx = First3OpsIdx +
(RBIdx - PartialMappingIdx::PMI_Min +
getRegBankBaseIdxOffset(RBIdx, Size)) *
ValueMappingIdx::DistanceBetweenRegBanks;
assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
"Mapping out of bound");
return &ValMappings[ValMappingIdx];
}
AArch64GenRegisterBankInfo::PartialMappingIdx
AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
PMI_FirstGPR, // GPR
PMI_FirstFPR, // FPR
PMI_None, // CCR
};
const RegisterBankInfo::ValueMapping *
AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
unsigned SrcBankID, unsigned Size) {
assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
assert(DstRBIdx != PMI_None && "No such mapping");
assert(SrcRBIdx != PMI_None && "No such mapping");
if (DstRBIdx == SrcRBIdx)
return getValueMapping(DstRBIdx, Size);
assert(Size <= 64 && "GPR cannot handle that size");
unsigned ValMappingIdx =
FirstCrossRegCpyIdx +
(DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
ValueMappingIdx::DistanceBetweenCrossRegCpy;
assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
return &ValMappings[ValMappingIdx];
}
} // End llvm namespace.
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