1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
define i32 @__clc_atomic_add_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_add_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_and_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_and_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_max_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_max_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_or_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_or_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umax_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umax_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_sub_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_sub_addr3(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i32 addrspace(3)* %ptr, i32 %value seq_cst
ret i32 %0
}
|
