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* Revert "[mlir] Create a gpu.module operation for the GPU Dialect."Benjamin Kramer2020-01-163-7/+8
| | | | | | | This reverts commit 4624a1e8ac8a3f69cc887403b976f538f587744a. Causing problems downstream. (cherry picked from commit 0133cc60e4e230ee2c176c23eff5aa2f4ee17a75)
* [mlir][spirv] Properly support SPIR-V conversion targetLei Zhang2020-01-143-10/+281
| | | | | | | | | | | | | | | | This commit defines a new SPIR-V dialect attribute for specifying a SPIR-V target environment. It is a dictionary attribute containing the SPIR-V version, supported extension list, and allowed capability list. A SPIRVConversionTarget subclass is created to take in the target environment and sets proper dynmaically legal ops by querying the op availability interface of SPIR-V ops to make sure they are available in the specified target environment. All existing conversions targeting SPIR-V is changed to use this SPIRVConversionTarget. It probes whether the input IR has a `spv.target_env` attribute, otherwise, it uses the default target environment: SPIR-V 1.0 with Shader capability and no extra extensions. Differential Revision: https://reviews.llvm.org/D72256
* [mlir][Linalg] Update the semantics, verifier and test for Linalg with tensors.Nicolas Vasilache2020-01-142-59/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This diff fixes issues with the semantics of linalg.generic on tensors that appeared when converting directly from HLO to linalg.generic. The changes are self-contained within MLIR and can be captured and tested independently of XLA. The linalg.generic and indexed_generic are updated to: To allow progressive lowering from the value world (a.k.a tensor values) to the buffer world (a.k.a memref values), a linalg.generic op accepts mixing input and output ranked tensor values with input and output memrefs. ``` %1 = linalg.generic #trait_attribute %A, %B {other-attributes} : tensor<?x?xf32>, memref<?x?xf32, stride_specification> -> (tensor<?x?xf32>) ``` In this case, the number of outputs (args_out) must match the sum of (1) the number of output buffer operands and (2) the number of tensor return values. The semantics is that the linalg.indexed_generic op produces (i.e. allocates and fills) its return values. Tensor values must be legalized by a buffer allocation pass before most transformations can be applied. Such legalization moves tensor return values into output buffer operands and updates the region argument accordingly. Transformations that create control-flow around linalg.indexed_generic operations are not expected to mix with tensors because SSA values do not escape naturally. Still, transformations and rewrites that take advantage of tensor SSA values are expected to be useful and will be added in the near future. Subscribers: bmahjour, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72555
* [mlir] Create a gpu.module operation for the GPU Dialect.Tres Popp2020-01-143-8/+7
| | | | | | | | | | | | | | | | | Summary: This is based on the use of code constantly checking for an attribute on a model and instead represents the distinct operaion with a different op. Instead, this op can be used to provide better filtering. Reviewers: herhut, mravishankar, antiagainst, rriddle Reviewed By: herhut, antiagainst, rriddle Subscribers: liufengdb, aartbik, jholewinski, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, csigg, arpith-jacob, mgester, lucyrfox, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72336
* [mlir] Add loop.parallel, loop.reduce and loop.reduce.return operations.Adrian Kuegel2020-01-142-0/+225
| | | | | | | | | | Summary: These operations can be used to specify a loop nest with a body that can contain reductions. The iteration space can be iterated in any order. RFC: https://groups.google.com/a/tensorflow.org/d/topic/mlir/pwtSgiKFPis/discussion Differential Revision: https://reviews.llvm.org/D72394
* [mlir] Change the syntax of AffineMapAttr and IntegerSetAttr to avoid ↵River Riddle2020-01-1315-278/+278
| | | | | | | | | | conflicts with function types. Summary: The current syntax for AffineMapAttr and IntegerSetAttr conflict with function types, making it currently impossible to round-trip function types(and e.g. FuncOp) in the IR. This revision changes the syntax for the attributes by wrapping them in a keyword. AffineMapAttr is wrapped with `affine_map<>` and IntegerSetAttr is wrapped with `affine_set<>`. Reviewed By: nicolasvasilache, ftynse Differential Revision: https://reviews.llvm.org/D72429
* [mlir][GPU] introduce utilities for promotion to workgroup memoryAlex Zinenko2020-01-091-0/+119
| | | | | | | | | | | | | | | | | | | Introduce a set of function that promote a memref argument of a `gpu.func` to workgroup memory using memory attribution. The promotion boils down to additional loops performing the copy from the original argument to the attributed memory in the beginning of the function, and back at the end of the function using all available threads. The loop bounds are specified so as to adapt to any size of the workgroup. These utilities are intended to compose with other existing utilities (loop coalescing and tiling) in cases where the distribution of work across threads is uneven, e.g. copying a 2D memref with only the threads along the "x" dimension. Similarly, specialization of the kernel to specific launch sizes should be implemented as a separate pass combining constant propagation and canonicalization. Introduce a simple attribute-driven pass to test the promotion transformation since we don't have a heuristic at the moment. Differential revision: https://reviews.llvm.org/D71904
* [mlir][Linalg] Lower linalg.reshape to LLVM for the static caseNicolas Vasilache2020-01-081-0/+60
| | | | | | | | | | | | | | | | | | | | | | Summary: This diff adds lowering of the linalg.reshape op to LLVM. A new descriptor is created with fields initialized as follows: 1. allocatedPTr, alignedPtr and offset are copied from the source descriptor 2. sizes are copied from the static destination shape 3. strides are copied from the static strides collected with `getStridesAndOffset` Only the static case in which the target view conforms to strided memref semantics is supported. Other cases are left for future work and will be added on a per-need basis. Reviewers: ftynse, mravishankar Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72316
* [mlir][spirv] Add lowering for std cmp ops.Denis Khalikov2020-01-071-0/+27
| | | | Differential Revision: https://reviews.llvm.org/D72296
* [mlir][spirv] Add lowering for standard bit opsDenis Khalikov2020-01-071-0/+9
| | | | Differential Revision: https://reviews.llvm.org/D72205
* [mlir][Linalg] Add a linalg.reshape opNicolas Vasilache2020-01-062-1/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This diff adds a new operation to linalg to allow reshaping of an existing view into a new view in the same buffer at the same offset. More specifically: The `linalg.reshape` op produces a new view whose sizes are a reassociation of the original `view`. Depending on whether or not the reassociated MemRefType is contiguous, the resulting memref may require explicit alloc and copies. A reassociation is defined as a continous grouping of dimensions and is represented with a affine map array attribute. In the future, non-continous groupings may be allowed (i.e. permutations, reindexings etc). For now, it is assumed that either: 1. a reassociation produces and consumes contiguous MemRefType or, 2. the reshape op will be folded into its consumers (by changing the shape of the computations). All other cases are undefined behavior and a reshape op may not lower to LLVM if it cannot be proven statically that it does not require alloc+copy. A reshape may either collapse or expand dimensions, depending on the relationship between source and target memref ranks. The verification rule is that the reassociation maps are applied to the memref with the larger rank to obtain the memref with the smaller rank. In the case of a dimension expansion, the reassociation maps can be interpreted as inverse maps. Examples: ```mlir // Dimension collapse (i, j) -> i' and k -> k' %1 = linalg.reshape %0 [(i, j, k) -> (i, j), (i, j, k) -> (k)] : memref<?x?x?xf32, stride_spec> into memref<?x?xf32, stride_spec_2> ``` ```mlir // Dimension expansion i -> (i', j') and (k) -> (k') %1 = linalg.reshape %0 [(i, j, k) -> (i, j), (i, j, k) -> (k)] : memref<?x?xf32, stride_spec> into memref<?x?x?xf32, stride_spec_2> ``` The relevant invalid and roundtripping tests are added. Reviewers: AlexEichenberger, ftynse, rriddle, asaadaldien, yangjunpro Subscribers: kiszk, merge_guards_bot, mehdi_amini, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72168
* [mlir][linalg] Lower linalg to affine loopsAhmed Taei2020-01-031-0/+55
| | | | | | | | | | | | Reviewers: nicolasvasilache Reviewed By: nicolasvasilache Subscribers: mgester, lucyrfox, merge_guards_bot, AlexEichenberger, mravishankar, ftynse, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72094
* [mlir][spirv] Fix shader ABI attribute prefix and add verificationLei Zhang2020-01-033-29/+130
| | | | | | | | | | This commit fixes shader ABI attributes to use `spv.` as the prefix so that they match the dialect's namespace. This enables us to add verification hooks in the SPIR-V dialect to verify them. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D72062
* [mlir][spirv] Update SPIR-V enums and ops with availability specLei Zhang2020-01-021-1/+1
| | | | | | | | | | This commit updates gen_spirv_dialect.py to query the grammar and generate availability spec for various enum attribute definitions and all defined ops. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D72095
* [mlir][Linalg] Extend generic ops to allow tensorsNicolas Vasilache2020-01-022-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This diff adds support to allow `linalg.generic` and `linalg.indexed_generic` to take tensor input and output arguments. The subset of output tensor operand types must appear verbatim in the result types after an arrow. The parser, printer and verifier are extended to accomodate this behavior. The Linalg operations now support variadic ranked tensor return values. This extension exhibited issues with the current handling of NativeCall in RewriterGen.cpp. As a consequence, an explicit cast to `SmallVector<Value, 4>` is added in the proper place to support the new behavior (better suggestions are welcome). Relevant cleanups and name uniformization are applied. Relevant invalid and roundtrip test are added. Reviewers: mehdi_amini, rriddle, jpienaar, antiagainst, ftynse Subscribers: burmako, shauheen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72022
* [mlir][spirv] Allow specifying availability on enum attribute casesLei Zhang2020-01-022-4/+25
| | | | | | | | | | | | | | Lots of SPIR-V ops take enum attributes and certain enum cases need extra capabilities or extensions to be available. This commit extends to allow specifying availability spec on enum cases. Extra utility functions are generated for the corresponding enum classes to return the availability requirement. The availability interface implemention for a SPIR-V op now goes over all enum attributes to collect the availability requirements. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D71947
* [mlir][spirv] Add basic definitions for supporting availabilityLei Zhang2019-12-274-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | SPIR-V has a few mechanisms to control op availability: version, extension, and capabilities. These mechanisms are considered as different availability classes. This commit introduces basic definitions for modelling SPIR-V availability classes. Specifically, an `Availability` class is added to SPIRVBase.td, along with two subclasses: MinVersion and MaxVersion for versioning. SPV_Op is extended to take a list of `Availability`. Each `Availability` instance carries information for generating op interfaces for the corresponding availability class and also the concrete availability requirements. With the availability spec on ops, we can now auto-generate the op interfaces of all SPIR-V availability classes and also synthesize the op's implementations of these interfaces. The interface generation is done via new TableGen backends -gen-avail-interface-{decls|defs}. The op's implementation is done via -gen-spirv-avail-impls. Differential Revision: https://reviews.llvm.org/D71930
* [VectorOps] unify vector dialect "subscripts"Aart Bik2019-12-202-34/+34
| | | | PiperOrigin-RevId: 286650682
* [VectorOps] remove redundant returns from invalid ops testAart Bik2019-12-201-27/+0
| | | | PiperOrigin-RevId: 286640660
* Add gpu.shuffle op.Christian Sigg2019-12-202-0/+19
| | | | | | | | This will allow us to lower most of gpu.all_reduce (when all_reduce doesn't exist in the target dialect) within the GPU dialect, and only do target-specific lowering for the shuffle op. PiperOrigin-RevId: 286548256
* [VectorOps] Update vector transfer_read/write ops to operatate on memrefs ↵Andy Davis2019-12-192-4/+45
| | | | | | | | | with vector element type. Update vector transfer_read/write ops to operatate on memrefs with vector element type. This handle cases where the memref vector element type represents the minimal memory transfer unit (or multiple of the minimal memory transfer unit). PiperOrigin-RevId: 286482115
* [VectorOps] Add vector ReshapeOp to the VectorOps dialect.Andy Davis2019-12-192-0/+77
| | | | | | Adds vector ReshapeOp to the VectorOps dialect. An aggregate vector reshape operation, which aggregates multiple hardware vectors, can enable optimizations during decomposition (e.g. loading one input hardware vector and performing multiple rotate and scatter store operations to the vector output). PiperOrigin-RevId: 286440658
* [VectorOps] minor cleanup: vector dialect "subscripts" are i32Aart Bik2019-12-192-12/+12
| | | | | | | | Introduces some centralized methods to move towards consistent use of i32 as vector subscripts. Note: sizes/strides/offsets attributes are still i64 PiperOrigin-RevId: 286434133
* [VectorOps] Add vector.print definition, with lowering supportAart Bik2019-12-182-0/+15
| | | | | | | | | | | | | | | | Examples: vector.print %f : f32 vector.print %x : vector<4xf32> vector.print %y : vector<3x4xf32> vector.print %z : vector<2x3x4xf32> LLVM lowering replaces these with fully unrolled calls into a small runtime support library that provides some basic printing operations (single value, opening closing bracket, comma, newline). PiperOrigin-RevId: 286230325
* Harden the requirements to memory attribution types in gpu.funcAlex Zinenko2019-12-181-0/+33
| | | | | | | | | | When memory attributions are present in `gpu.func`, require that they are of memref type and live in memoryspaces 3 and 5 for workgroup and private memory attributions, respectively. Adapt the conversion from the GPU dialect to the NVVM dialect to drop the private memory space from attributions as NVVM is able to model them as local `llvm.alloca`s in the default memory space. PiperOrigin-RevId: 286161763
* Add pattern rewrite which splits a vector TransferWriteOp into slices ↵Andy Davis2019-12-171-10/+21
| | | | | | according to the unrolling/slicing scheme of its InsertSlicesOp operand. PiperOrigin-RevId: 286042578
* Add missing virtual inliner interface method in SPIR-V dialect.Mahesh Ravishankar2019-12-171-0/+45
| | | | | | | | | | | The inline interface uses two methods to check legality of inling: 1) Can a region be inlined into another. 2) Can an operation be inlined into another. Setting the former to true, allows the inliner to use the second for legality checks. Add this method to the SPIR-V dialect inlining interface. PiperOrigin-RevId: 286041734
* Add pattern rewrite to forward vector tuple elements to their users.Andy Davis2019-12-171-13/+4
| | | | | | User(TupleGetOp(ExtractSlicesOp(InsertSlicesOp(TupleOp(Producer))) -> User(Producer) PiperOrigin-RevId: 286020249
* Add pattern rewrite which splits a vector TransferReadOp into slices ↵Andy Davis2019-12-171-5/+12
| | | | | | according to the unrolling/slicing scheme of its ExtractSlicesOp user. PiperOrigin-RevId: 285975613
* Update vector op unrolling transformation to generate ExtractSlicesOp and ↵Andy Davis2019-12-171-151/+144
| | | | | | InsertSlicesOp (instead of less structured chain of StridedSliceOps and InsertStridedSliceOps). PiperOrigin-RevId: 285968051
* Add atomic operations to SPIR-V dialect.Mahesh Ravishankar2019-12-162-2/+155
| | | | | | | Some changes to the dialect generation script to allow specification of different base class to derive from in ODS. PiperOrigin-RevId: 285859230
* [spirv] Re-enable nested loop (de)serialization testLei Zhang2019-12-161-98/+99
| | | | PiperOrigin-RevId: 285849308
* Add InsertSlicesOp to the VectorOps dialect.Andy Davis2019-12-162-0/+43
| | | | PiperOrigin-RevId: 285830394
* Plug gpu.func into the GPU lowering pipelinesAlex Zinenko2019-12-163-15/+14
| | | | | | | | | | | | | | This updates the lowering pipelines from the GPU dialect to lower-level dialects (NVVM, SPIRV) to use the recently introduced gpu.func operation instead of a standard function annotated with an attribute. In particular, the kernel outlining is updated to produce gpu.func instead of std.func and the individual conversions are updated to consume gpu.funcs and disallow standard funcs after legalization, if necessary. The attribute "gpu.kernel" is preserved in the generic syntax, but can also be used with the custom syntax on gpu.funcs. The special kind of function for GPU allows one to use additional features such as memory attribution. PiperOrigin-RevId: 285822272
* [Linalg] Expose subview promotion as a declarative patternJose Ignacio Gomez2019-12-161-0/+50
| | | | | | | | | | | | This PR targest issue tensorflow/mlir#295. It exposes the already existing subiew promotion pass as a declarative pattern Change-Id: If901ebef9fb53fcd0b12ecc536f6b174ce320b92 Closes tensorflow/mlir#315 COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/315 from tetuante:issue295 8e5f268b6d85f31015c33505329dbd7a4db97ac5 PiperOrigin-RevId: 285801463
* [VectorOps] Add [insert/extract]element definition together with lowering to ↵Aart Bik2019-12-162-1/+43
| | | | | | | | | | | | | | LLVM Similar to insert/extract vector instructions but (1) work on 1-D vectors only (2) allow for a dynamic index %c3 = constant 3 : index %0 = vector.insertelement %arg0, %arg1[%c : index] : vector<4xf32> %1 = vector.extractelement %arg0[%c3 : index] : vector<4xf32> PiperOrigin-RevId: 285792205
* Adds ExtractSlicesOp to the VectorOps dialect.Andy Davis2019-12-162-0/+68
| | | | | | | ExtractSlicesOp extracts slices of its vector operand and with a specified tiling scheme. This operation centralizes the tiling scheme around a single op, which simplifies vector op unrolling and subsequent pattern rewrite transformations. PiperOrigin-RevId: 285761129
* [Linalg] Add test for fusion of GenericOp with IndexedGenericOp.Alexander Belyaev2019-12-121-1/+56
| | | | PiperOrigin-RevId: 285211797
* Automated rollback of commit f68ac464d818629e0fe10c23b44ac782d64a12d2Christian Sigg2019-12-122-11/+11
| | | | PiperOrigin-RevId: 285162061
* Switch from shfl.bfly to shfl.down.Christian Sigg2019-12-122-11/+11
| | | | | | | Both work for the current use case, but the latter allows implementing prefix sums and is a little easier to understand for partial warps. PiperOrigin-RevId: 285145287
* Continue refactoring StructuredOps utilitiesNicolas Vasilache2019-12-118-51/+98
| | | | | | | This CL adds more common information to StructuredOpsUtils.h The n_view attribute is retired in favor of args_in + args_out but the CL is otherwise NFC. PiperOrigin-RevId: 285000621
* [Linalg] Add tiling for IndexedGenericOp with a region.Alexander Belyaev2019-12-111-0/+102
| | | | PiperOrigin-RevId: 284949355
* Add VectorOp transform pattern which splits vector TransferReadOps to target ↵Andy Davis2019-12-101-1/+65
| | | | | | vector unroll size. PiperOrigin-RevId: 284880592
* Fold TestLinalgTilePermutePatterns into TestLinalgTransformPatterns - NFCNicolas Vasilache2019-12-102-70/+68
| | | | | | Centralize all patterns that test Linalg transforms in a single pass. PiperOrigin-RevId: 284835938
* [Linalg] Add a Linalg iterator permutation transformationJose Ignacio Gomez2019-12-101-0/+52
| | | | | | | | | | | | | | | This patch closes issue tensorflow/mlir#272 We add a standalone iterator permutation transformation to Linalg. This transformation composes a permutation map with the maps in the "indexing_maps" attribute. It also permutes "iterator_types" accordingly. Change-Id: I7c1e693b8203aeecc595a7c012e738ca1100c857 Closes tensorflow/mlir#307 COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/307 from tetuante:issue272 f7908d58792f4111119721885e247045104f1131 PiperOrigin-RevId: 284824102
* Uniformize Vector transforms as patterns on the model of Linalg - NFCNicolas Vasilache2019-12-101-0/+238
| | | | | | This reorganizes the vector transformations to be more easily testable as patterns and more easily composable into fused passes in the future. PiperOrigin-RevId: 284817474
* [VectorOps] Add a ShuffleOp to the VectorOps dialectAart Bik2019-12-092-14/+67
| | | | | | | | | | For example %0 = vector.shuffle %x, %y [3 : i32, 2 : i32, 1 : i32, 0 : i32] : vector<2xf32>, vector<2xf32> yields a vector<4xf32> result with a permutation of the elements of %x and %y PiperOrigin-RevId: 284657191
* [VectorOps] Fix off-by-one error in insert/extract validationAart Bik2019-12-091-0/+14
| | | | PiperOrigin-RevId: 284652653
* [spirv] Add CompositeConstruct operation.Denis Khalikov2019-12-092-1/+58
| | | | | | | Closes tensorflow/mlir#308 COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/308 from denis0x0D:sandbox/composite_construct 9ef7180f77f9374bcd05afc4f9e6c1d2d72d02b7 PiperOrigin-RevId: 284613617
* [spirv] Add spv.IAdd, spv.ISub, and spv.IMul foldersLei Zhang2019-12-091-0/+155
| | | | | | | The patterns to be folded away can be commonly generated during lowering to SPIR-V. PiperOrigin-RevId: 284604855
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