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* [mlir][spirv] Add lowering for std.fpext, std.fptrunc, std.sitofp.Denis Khalikov2020-01-071-0/+33
| | | | Differential Revision: https://reviews.llvm.org/D72137
* Revert "[mlir][spirv] Add lowering for std.fpext, std.fptrunc, std.sitofp."Lei Zhang2020-01-071-33/+0
| | | | | This reverts commit 7e7f849a6d94f77f1a29630419acb7226051f4b6 because it recorded the wrong commit author.
* [mlir][spirv] Add lowering for std cmp ops.Denis Khalikov2020-01-071-0/+41
| | | | Differential Revision: https://reviews.llvm.org/D72296
* [mlir][spirv] Add lowering for standard bit opsDenis Khalikov2020-01-071-18/+48
| | | | Differential Revision: https://reviews.llvm.org/D72205
* [mlir][spirv] Add lowering for std.fpext, std.fptrunc, std.sitofp.Lei Zhang2020-01-071-0/+33
| | | | Differential Revision: https://reviews.llvm.org/D72137
* [mlir] Convert std.and/std.or ops to spv.LogicalAnd/spv.LogicalOrMaheshRavishankar2019-12-271-0/+40
| | | | | | | | | The conversion from std.and/std.or to spv.LogicalAnd/spv.LogicalOr is only valid for boolean (i1) types. Modify BinaryOpPattern in StandardToSPIRV.td to allow limiting the type of the operands for which the pattern is applied. Differential Revision: https://reviews.llvm.org/D71881
* Add integer bit-shift operations to the standard dialect.Manuel Freiberger2019-12-221-2/+2
| | | | | | | | | | | | | | | | | | | Rename the 'shlis' operation in the standard dialect to 'shift_left'. Add tests for this operation (these have been missing so far) and add a lowering to the 'shl' operation in the LLVM dialect. Add also 'shift_right_signed' (lowered to LLVM's 'ashr') and 'shift_right_unsigned' (lowered to 'lshr'). The original plan was to name these operations 'shift.left', 'shift.right.signed' and 'shift.right.unsigned'. This works if the operations are prefixed with 'std.' in MLIR assembly. Unfortunately during import the short form is ambigous with operations from a hypothetical 'shift' dialect. The best solution seems to omit dots in standard operations for now. Closes tensorflow/mlir#226 PiperOrigin-RevId: 286803388
* [spirv] Add lowering for std.fdiv, std.frem, std.fsubDenis Khalikov2019-12-111-0/+28
| | | | | | | Closes tensorflow/mlir#313 COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/313 from denis0x0D:sandbox/lowering_std_farith 41715070a74d13bfa9401957478978c1bb8006c0 PiperOrigin-RevId: 285023586
* Add a pass to legalize operations before lowering to SPIR-V.Mahesh Ravishankar2019-12-032-0/+114
| | | | | | | | | | | | Not all StandardOps can be lowered to SPIR-V. For example, subview op implementation requires use of pointer bitcasts which is not valid according to SPIR-V spec (or at least is ambiguous about it). Such ops need to be removed/transformed before lowering to SPIR-V. The SPIRVLegalizationPass is added a place where such legalizations can be added. Current implementation folds the subview ops with load/stores so that the lowering itself does not have to convert a subview op. PiperOrigin-RevId: 283642981
* [spirv] NFC: rename test files and sort tests insideLei Zhang2019-11-231-33/+49
| | | | PiperOrigin-RevId: 282132339
* Add operations needed to support lowering of AffineExpr to SPIR-V.Mahesh Ravishankar2019-11-121-1/+44
| | | | | | | | Lowering of CmpIOp, DivISOp, RemISOp, SubIOp and SelectOp to SPIR-V dialect enables the lowering of operations generated by AffineExpr -> StandardOps conversion into the SPIR-V dialect. PiperOrigin-RevId: 280039204
* Add lowering of constant ops to SPIR-V.Mahesh Ravishankar2019-10-101-0/+60
The lowering is specified as a pattern and is done only if the result is a SPIR-V scalar type or vector type. Handling ConstantOp with index return type needs special handling since SPIR-V dialect does not have index types. Based on the bitwidth of the attribute value, either i32 or i64 is chosen. Other constant lowerings are left as a TODO. PiperOrigin-RevId: 274056805
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