summaryrefslogtreecommitdiffstats
path: root/mlir/lib/Analysis/Utils.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* Refactor and share common code across addAffineForOpDomain / addSliceBoundsUday Bondhugula2019-03-291-13/+1
* Convert ambiguous bool returns in /Analysis to use Status instead.River Riddle2019-03-291-39/+40
* Add FlatAffineConstraints::containsId to avoid using findId when position isn'tUday Bondhugula2019-03-291-5/+2
* Use FlatAffineConstraints::unionBoundingBox to perform slice bounds union for...MLIR Team2019-03-291-0/+49
* Adds loop attribute as a temporary work around to prevent slice fusion of loo...MLIR Team2019-03-291-13/+18
* Update addSliceBounds to deal with loops with floor's/mod's.Uday Bondhugula2019-03-291-3/+6
* NFC. Move all of the remaining operations left in BuiltinOps to StandardOps. ...River Riddle2019-03-291-1/+0
* Use consistent names for dialect op source filesLei Zhang2019-03-291-1/+1
* A simple pass to detect and mark all parallel loopsUday Bondhugula2019-03-291-22/+21
* Loop fusion for input reuse.MLIR Team2019-03-291-5/+65
* Method to align/merge dimensional/symbolic identifiers between two FlatAffine...Uday Bondhugula2019-03-291-6/+7
* Change some of the debug messages to use emitError / emitWarning / emitNote -...Uday Bondhugula2019-03-291-1/+1
* Fix bug in memref region computation with slice loop bounds. Adds loop IV val...MLIR Team2019-03-291-1/+4
* Refactor AffineExprFlattener and move FlatAffineConstraints out of IR intoUday Bondhugula2019-03-291-2/+2
* Fix for getMemRefSizeInBytes: unsigned -> uint64_tUday Bondhugula2019-03-291-1/+1
* Misc. updates/fixes to analysis utils used for DMA generation; update DMAUday Bondhugula2019-03-291-18/+38
* Fix + cleanup for getMemRefRegion()Uday Bondhugula2019-03-291-13/+16
* Automated rollback of changelist 232728977.Uday Bondhugula2019-03-291-1/+1
* Automated rollback of changelist 232717775.Uday Bondhugula2019-03-291-5/+5
* Rename the 'if' operation in the AffineOps dialect to 'affine.if' and namespaceRiver Riddle2019-03-291-1/+1
* NFC: Rename the 'for' operation in the AffineOps dialect to 'affine.for'. The...River Riddle2019-03-291-6/+6
* Address post submit review comments for removing Block::findInstPositionInBlock.River Riddle2019-03-291-1/+1
* Adds the ability to compute the MemRefRegion of a sliced loop nest. Utilizes ...MLIR Team2019-03-291-37/+77
* Remove findInstPositionInBlock from the Block api.River Riddle2019-03-291-2/+3
* Refactor the affine analysis by moving some functionality to IR and some to A...River Riddle2019-03-291-2/+2
* NFC: Move AffineApplyOp to the AffineOps dialect. This also moves the isValid...River Riddle2019-03-291-1/+1
* Refactor common code getting memref access in getMemRefRegion - NFCUday Bondhugula2019-03-291-65/+50
* Update dma-generate pass to (1) work on blocks of instructions (instead of justUday Bondhugula2019-03-291-21/+30
* Begin the process of fully removing OperationInst. This patch cleans up refer...River Riddle2019-03-291-15/+11
* Define the AffineForOp and replace ForInst with it. This patch is largely mec...River Riddle2019-03-291-34/+42
* Recommit: Define a AffineOps dialect as well as an AffineIfOp operation. Repl...River Riddle2019-03-291-15/+7
* Automated rollback of changelist 231318632.Nicolas Vasilache2019-03-291-7/+15
* Define a AffineOps dialect as well as an AffineIfOp operation. Replace all in...River Riddle2019-03-291-15/+7
* Change the ForInst induction variable to be a block argument of the body inst...River Riddle2019-03-291-3/+4
* Drop AffineMap::Null and IntegerSet::NullNicolas Vasilache2019-03-291-2/+2
* Allow operations to hold a blocklist and add support for parsing/printing a b...River Riddle2019-03-291-0/+8
* Update dma-generate: update for multiple load/store op's per memrefUday Bondhugula2019-03-291-0/+5
* Add cloning functionality to Block and Function, this also adds support for r...River Riddle2019-03-291-2/+1
* Migrate VectorOrTensorType/MemRefType shape api to use int64_t instead of int.River Riddle2019-03-291-2/+2
* Update fusion cost model + some additional infrastructure and debug informati...Uday Bondhugula2019-03-291-14/+93
* Allocate private/local buffers for slices accurately during fusionUday Bondhugula2019-03-291-4/+9
* LoopFusion improvements:MLIR Team2019-03-291-25/+31
* Minor code cleanup - NFC.Uday Bondhugula2019-03-291-6/+8
* LoopFusion: automate selection of source loop nest slice depth and destinatio...MLIR Team2019-03-291-30/+48
* Simplify compositions of AffineApplyNicolas Vasilache2019-03-291-2/+4
* Delete FuncBuilder::createChecked. It is perhaps still a good idea, but has noChris Lattner2019-03-291-2/+1
* Fix 0-d memref corner case for getMemRefRegion()Uday Bondhugula2019-03-291-0/+9
* Extend loop-fusion's slicing utility + other fixes / updatesUday Bondhugula2019-03-291-64/+57
* Misc readability and doc / code comment related improvements - NFCUday Bondhugula2019-03-291-16/+13
* Complete TODOs / cleanup for loop-fusion utilityUday Bondhugula2019-03-291-10/+1
OpenPOWER on IntegriCloud