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* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-032-0/+17
| | | | | | integer-promoted. llvm-svn: 147484
* Enhance DAGCombine for transforming 128->256 casts into a vmovaps, ratherChad Rosier2012-01-033-0/+42
| | | | | | | then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 llvm-svn: 147481
* Conform to the style guide; remove 'else' after 'return'. Also remove an extraNick Lewycky2012-01-031-56/+36
| | | | | | if-statement by turning it into an assert. No functionality change. llvm-svn: 147474
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Fix for PR11652: assertion failures when Type.cpp is compiled with -OsStepan Dyatkovskiy2012-01-031-9/+21
| | | | llvm-svn: 147470
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* Fix typo.Eric Christopher2012-01-031-1/+1
| | | | llvm-svn: 147456
* Fix typo in ruler. No functionality change.Nick Lewycky2012-01-031-1/+1
| | | | llvm-svn: 147454
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-032-28/+28
| | | | llvm-svn: 147453
* Type: replaced usage of ID with getTypeID().Stepan Dyatkovskiy2012-01-032-38/+44
| | | | llvm-svn: 147446
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-032-6/+58
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
* Fix SCEVExpander to handle loops with no preheader when LSR gives it aAndrew Trick2012-01-022-0/+56
| | | | | | | | "phony" insertion point. Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert llvm-svn: 147439
* Correct spelling.Duncan Sands2012-01-021-1/+1
| | | | llvm-svn: 147435
* Undo the hack in r147427 and move this unittest to a better home. ThisChandler Carruth2012-01-025-5/+24
| | | | | | | | | | | | | | | is testing the bitcode reader's functionality, not VMCore's. Add the what is a hope sufficient build system mojo to build and run a new unittest. Also clean up some of the test's naming. The goal for the file should be to unittest the Bitcode Reader, and this is just one particular test among potentially many in the future. Also, reverse my position and relegate the PR# to a comment, but stash the comment on the same line as the test name so it doesn't get lost. This makes the code more self-documenting hopefully w/o losing track of the PR number. llvm-svn: 147431
* Miscellaneous shuffle lowering cleanup. No functional changes. Primarily ↵Craig Topper2012-01-021-47/+43
| | | | | | converting the indexing loops to unsigned to be consistent across functions. llvm-svn: 147430
* Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. ↵Craig Topper2012-01-022-26/+22
| | | | | | Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. llvm-svn: 147428
* Fix unittest makefile after r147425. This should unbreak the makefileChandler Carruth2012-01-021-1/+1
| | | | | | | | | | | build. This didn't show up in the CMake build because the CMake build for the unittests is rather poorly factored. This probably isn't the correct fix. This should be a bitcode reader unittest not a VMCore unittest. I'll move it and clean various parts of the unittest up in a follow-up patch, but I wanted to unbreak the bots. llvm-svn: 147427
* Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend ↵Nadav Rotem2012-01-025-10/+49
| | | | | | instructions only look at the highest bit. llvm-svn: 147426
* Materialize functions whose basic blocks are used by global variables. FixesRafael Espindola2012-01-024-1/+78
| | | | | | PR11677. llvm-svn: 147425
* Allow CRC32 instructions to be selected when AVX is enabled.Craig Topper2012-01-013-2/+24
| | | | llvm-svn: 147411
* Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX ↵Craig Topper2012-01-015-22/+71
| | | | | | is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. llvm-svn: 147409
* X86Disassembler: Fix undefined behavior found by GCC 4.6Benjamin Kramer2012-01-011-3/+5
| | | | llvm-svn: 147404
* PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use ↵Benjamin Kramer2012-01-013-19/+30
| | | | | | it to simplify a few matchers. llvm-svn: 147403
* PatternMatch: Simplify code by reusing the Operator class.Benjamin Kramer2012-01-011-22/+12
| | | | llvm-svn: 147402
* Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola2012-01-012-47/+5
| | | | llvm-svn: 147400
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-012-5/+47
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
* Happy new year 2012!NAKAMURA Takumi2012-01-014-7/+7
| | | | llvm-svn: 147395
* Merge X86 SHUFPS and SHUFPD node types.Craig Topper2011-12-314-58/+35
| | | | llvm-svn: 147394
* Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load.Craig Topper2011-12-312-0/+70
| | | | llvm-svn: 147393
* Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with ↵Craig Topper2011-12-312-4/+36
| | | | | | a load from being selected. llvm-svn: 147392
* Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate theNick Lewycky2011-12-312-5/+29
| | | | | | | 'and' that would zero out the trailing bits, and to produce an exact shift ourselves. llvm-svn: 147391
* VMCore: add assert for miscompileDylan Noblesmith2011-12-311-0/+5
| | | | | | | | | | | See PR11652. Trying to add this assert to setSubclassData() itself actually prevented the miscompile entirely, so it has to be here. This makes the source of the bug more obvious than the other asserts triggering later on did. llvm-svn: 147390
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-304-171/+79
| | | | llvm-svn: 147383
* Improve Mips JIT.Bruno Cardoso Lopes2011-12-303-6/+15
| | | | | | | | | | | Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue for jmptarget and brtarget Mips tablegen operand types in the code emitter for old-style JIT. Rename the pc relative relocation for branches - new name is Mips::reloc_mips_pc16. Patch by Sasa Stankovic llvm-svn: 147382
* Remove extraneous ".get()->" which is just "->". No functionality change.Nick Lewycky2011-12-301-5/+5
| | | | llvm-svn: 147379
* Make FMA4 imply AVX so that YMM registers would be available. Necessitates ↵Craig Topper2011-12-301-6/+8
| | | | | | removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-304-11/+26
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-304-39/+69
| | | | llvm-svn: 147367
* Separate the concept of having memory access in operand 4 from the concept ↵Craig Topper2011-12-305-34/+26
| | | | | | of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. llvm-svn: 147366
* Combine FMA4 SS/SD patterns with the instruction definitions.Craig Topper2011-12-301-97/+24
| | | | llvm-svn: 147365
* Combine FMA4 PS/PD patterns with the instruction definitions.Craig Topper2011-12-301-219/+42
| | | | llvm-svn: 147364
* Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to ↵Craig Topper2011-12-302-58/+72
| | | | | | force alignment on these instructions. Add a couple testcases for memory forms. llvm-svn: 147361
* Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 ↵Craig Topper2011-12-302-60/+71
| | | | | | size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. llvm-svn: 147360
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-304-25/+31
| | | | | | | | 1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. llvm-svn: 147359
* Implement cfi_restore. Patch by Brian Anderson!Rafael Espindola2011-12-296-2/+80
| | | | llvm-svn: 147356
* Rename Remember and Restore to RememberState and RestoreState for consistency.Rafael Espindola2011-12-293-6/+6
| | | | llvm-svn: 147354
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ↵Craig Topper2011-12-293-19/+67
| | | | | | instructions. llvm-svn: 147353
* Implement .cfi_escape. Patch by Brian Anderson!Rafael Espindola2011-12-296-1/+92
| | | | llvm-svn: 147352
* Expose FMA3 instructions to the disassembler.Craig Topper2011-12-292-17/+39
| | | | llvm-svn: 147351
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