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* DebugInfo: Refactor some tests to allow DW_AT_name to not be the first ↵David Blaikie2014-06-139-18/+37
| | | | | | | | | | | | | | | | | attribute in a local variable. In an effort to fix concrete variables referencing abstract origins where the concrete variable preceeds the first inlined usage, the addition of attributes such as name, file, etc will be delayed until the end of the module (to wait to see if any inlined instances have occurred, thus necessitating an abstract definition that the concrete definition should also reference). These test cases don't actually need to care about this ordering of attributes, so update them to be more resilient to such changes coming in the near future. llvm-svn: 210940
* test/DebugInfo/X86/dbg-value-isel.s: correct lexical block descriptor to ↵David Blaikie2014-06-131-1/+1
| | | | | | | | | | match schema This silently broke a long time ago when I unified some aspects of the debug info schema. I'm just cleaning these up if/when they become a problem. llvm-svn: 210939
* Make the error-handling functions thread-safe.Zachary Turner2014-06-132-9/+19
| | | | | | | | | | | | | Prior to this change, error handling functions must be installed and removed only inside of an llvm_[start/stop]_multithreading pair. This change allows error handling functions to be installed any time, and from any thread. Reviewed by: chandlerc Differential Revision: http://reviews.llvm.org/D4140 llvm-svn: 210937
* Remove top-level Clang -fsanitize= flags for optional ASan features.Alexey Samsonov2014-06-135-41/+21
| | | | | | | | | | | | | Init-order and use-after-return modes can currently be enabled by runtime flags. use-after-scope mode is not really working at the moment. The only problem I see is that users won't be able to disable extra instrumentation for init-order and use-after-scope by a top-level Clang flag. But this instrumentation was implicitly enabled for quite a while and we didn't hear from users hurt by it. llvm-svn: 210924
* X86: lower ATOMIC_CMP_SWAP_WITH_SUCCESS directlyTim Northover2014-06-133-12/+201
| | | | | | | | | | | Lowering this new node allows us to fold the almost universal comparison for success before it's even formed. Instead we can create a copy from EFLAGS and an X86ISD::SETCC operation since all "cmpxchg" instructions set the zero-flag to the correct value. rdar://problem/13201607 llvm-svn: 210923
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-132-95/+42
| | | | | | | | | | | | Move / delete some of the more obviously wrong setOperationAction calls. Most of these are setting Expand for types that aren't legal which is the default anyway. Leave stuff that might require more thought on whether it's junk or not as it is. No functionality change. llvm-svn: 210922
* Finishing touch for the std::error_code transition.Rafael Espindola2014-06-1316-38/+134
| | | | | | | | | | | While std::error_code itself seems to work OK in all platforms, there are few annoying differences with regards to the std::errc enumeration. This patch adds a simple llvm enumeration, which will hopefully avoid build breakages in other platforms and surprises as we get more uses of std::error_code. llvm-svn: 210920
* Atomics: make use of the "cmpxchg weak" instruction.Tim Northover2014-06-136-48/+232
| | | | | | | | | This also simplifies the IR we create slightly: instead of working out where success & failure should go manually, it turns out we can just always jump to a success/failure block created for the purpose. Later phases will sort out the mess without much difficulty. llvm-svn: 210917
* Atomics: switch direction of cmpxchg comparisonTim Northover2014-06-133-18/+18
| | | | | | | | This has two benefits: it makes the result more suitable for direct insertaion into the struct to emulate the new cmpxchg, and it means the name we give the instruction matches its actual effect better. llvm-svn: 210916
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-1321-447/+104
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* opt: Initialize asm printersTobias Grosser2014-06-131-0/+1
| | | | | | | | | | | | | | Without initializing the assembly printers a shared library build of opt is linked with these libraries whereas for a static build these libraries are dead code eliminated. This is unfortunate for plugins in case they want to use them, as they neither can rely on opt to provide this functionality nor can they link the printers in themselves as this breaks with a shared object build of opt. This patch calls InitializeAllAsmPrinters() from opt, which increases the static binary size from 50MB -> 52MB on my system (all backends compiled) and causes no measurable increase in the time needed to run 'make check'. llvm-svn: 210914
* Remove unused and odd code.Rafael Espindola2014-06-134-33/+0
| | | | | | | | This code was never being used and any use of it would look fairly strange. For example, it would try to map a object_error::parse_failed to std::errc::invalid_argument. llvm-svn: 210912
* Remove broken include.Rafael Espindola2014-06-131-1/+0
| | | | | | Looks like I got some git merge wrong. llvm-svn: 210911
* Fix KillTheDoctor after r210725.Rafael Espindola2014-06-131-2/+4
| | | | | | | We don't map these windows errors to generic ones since errc::timed_out is not defined on mingw. Just use the raw windows error value. llvm-svn: 210910
* SCCP: update for cmpxchg returning { iN, i1 } now.Tim Northover2014-06-132-1/+12
| | | | | | I accidentally missed this one since its use looked OK locally. llvm-svn: 210909
* [mips][mips64r6] Relocation R_MIPS_PC18_S3Zoran Jovanovic2014-06-136-6/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D3890 llvm-svn: 210908
* Docs: remove extra {} around result types.Tim Northover2014-06-131-97/+97
| | | | | | | | It makes the types look like they're single-element structures. And when we have instructions that *do* result in a struct, that can get confusing rather quickly. llvm-svn: 210905
* Docs: fix grammar error in descriptionTim Northover2014-06-131-4/+4
| | | | llvm-svn: 210904
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-1361-295/+629
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
* Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.Cameron McInally2014-06-131-2/+2
| | | | llvm-svn: 210901
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-1315-13/+118
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
* [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-133-2/+16
| | | | | | | | | | | | | | Summary: These MIPS-3D instructions have never been implemented in LLVM so we only add testcases. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4115 llvm-svn: 210899
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-1322-13/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
* [mips][mips64r6] daddi is not available on MIPS64r6Daniel Sanders2014-06-1310-14/+67
| | | | | | | | | | | | | | | | | | Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
* [Win32] Let utils/not aware of abort(), aka llvm_unreachable(), in msvcrt.NAKAMURA Takumi2014-06-131-0/+7
| | | | | | | It has exit code as 3. abort(), aka unreachable, may be handled as crash. FIXME: Could we move this into Win32/Program.inc? llvm-svn: 210895
* llvm/test/CodeGen/X86/fast-isel-args-fail2.ll: Don't expect to fail with ↵NAKAMURA Takumi2014-06-131-0/+1
| | | | | | -Asserts. It might or might not crash. llvm-svn: 210894
* Add HasCDI predicate to AVX512 VPBROADCASTM*.Cameron McInally2014-06-131-0/+2
| | | | llvm-svn: 210892
* CPP backend: set volatile property on atomic instructions.Tim Northover2014-06-132-0/+79
| | | | llvm-svn: 210890
* ARM: Fix fastcc calling convention for Thumb1Oliver Stannard2014-06-132-3/+39
| | | | | | | | When targetting Thumb1 on a processor which has a VFP unit (which is not accessible from Thumb1), we were converting the fastcc calling convention to AAPCS-VFP, which is not possible. llvm-svn: 210889
* R600: Don't call setOperationAction with things that aren't opcodes.Matt Arsenault2014-06-131-8/+0
| | | | | | | | | CondCode actions are set with setCondCodeAction. This should have been a harmless bug since the values seem to only collide only with nodes that don't need to be handled, and these are already correctly setup elsewhere. llvm-svn: 210888
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-135-32/+136
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* Remove the last uses of 'using std::error_code'Rafael Espindola2014-06-138-79/+73
| | | | | | This finishes the transition to std::error_code. llvm-svn: 210877
* Remove 'using std::error_code' from tools.Rafael Espindola2014-06-1333-194/+167
| | | | llvm-svn: 210876
* Fix build on windows.Rafael Espindola2014-06-132-85/+90
| | | | llvm-svn: 210873
* Remove 'using std::errro_code' from lib.Rafael Espindola2014-06-1342-580/+562
| | | | llvm-svn: 210871
* [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.Juergen Ributzka2014-06-132-0/+120
| | | | | | | | This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding insertelement instructions are folded into the conversion instruction (if possible). llvm-svn: 210870
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-1323-43/+54
| | | | llvm-svn: 210869
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-131-1/+2
| | | | llvm-svn: 210868
* Remove all uses of 'using std::error_code' from headers.Rafael Espindola2014-06-1322-65/+68
| | | | llvm-svn: 210866
* R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard2014-06-131-1/+1
| | | | llvm-svn: 210865
* [FastISel][X86] - Add branch weightsJuergen Ributzka2014-06-133-5/+41
| | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). llvm-svn: 210863
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-134-7/+7
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-134-76/+87
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* [DWARF parser] Fix broken address ranges construction.Alexey Samsonov2014-06-125-60/+86
| | | | | | | | | | | | | | | | | Previous algorithm for constructing [Address ranges]->[Compile Units] mapping was wrong. It somewhat relied on the assumption that address ranges for different compile units may not overlap. It is not so. For example, two compile units may contain the definition of the same linkonce_odr function. These definitions will be merged at link-time, resulting in equivalent .debug_ranges entries for both these units Instead of sorting and merging original address ranges (from .debug_ranges and .debug_aranges), implement a different approach: save endpoints of all ranges, and then use a sweep-line approach to construct the desired mapping. If we find that certain address maps to several compilation units, we just pick any of them. llvm-svn: 210860
* Have ARMSelectionDAGInfo take a DataLayout as it's argument as theEric Christopher2014-06-123-14/+11
| | | | | | | DAG has access to the subtarget and TargetSelectionDAGInfo only needs a DataLayout. llvm-svn: 210859
* [FastISel][X86] Add MachineMemOperand to load/store instructions.Juergen Ributzka2014-06-124-39/+127
| | | | | | | | This commit adds MachineMemOperands to load and store instructions. This allows the peephole optimizer to fold load instructions. Unfortunatelly the peephole optimizer currently doesn't run at -O0. llvm-svn: 210858
* Move the PPCSelectionDAGInfo off the TargetMachine and onto theEric Christopher2014-06-124-5/+6
| | | | | | subtarget. llvm-svn: 210854
* Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachineEric Christopher2014-06-123-7/+6
| | | | | | since that's all it needs. llvm-svn: 210853
* Move PPCTargetLowering off of the TargetMachine and onto the subtarget.Eric Christopher2014-06-125-8/+11
| | | | llvm-svn: 210852
* Remove an extraneous this-> to access the subtarget.Eric Christopher2014-06-121-1/+1
| | | | llvm-svn: 210849
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