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authorOliver Stannard <oliver.stannard@arm.com>2014-06-13 08:33:03 +0000
committerOliver Stannard <oliver.stannard@arm.com>2014-06-13 08:33:03 +0000
commitb5e596f7c3cc5b1056780dc7c27932eb7d04c443 (patch)
tree2c4b53f060a00c1010ce913052c0f48da209ae50 /llvm
parentc02eea7f6485d5ee253a4b238ea8dc6761e38a62 (diff)
downloadbcm5719-llvm-b5e596f7c3cc5b1056780dc7c27932eb7d04c443.tar.gz
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ARM: Fix fastcc calling convention for Thumb1
When targetting Thumb1 on a processor which has a VFP unit (which is not accessible from Thumb1), we were converting the fastcc calling convention to AAPCS-VFP, which is not possible. llvm-svn: 210889
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp6
-rw-r--r--llvm/test/CodeGen/Thumb/fastcc.ll36
2 files changed, 39 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 64270dade26..47a48f18a3d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1205,7 +1205,7 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
case CallingConv::C:
if (!Subtarget->isAAPCS_ABI())
return CallingConv::ARM_APCS;
- else if (Subtarget->hasVFP2() &&
+ else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
!isVarArg)
return CallingConv::ARM_AAPCS_VFP;
@@ -1213,10 +1213,10 @@ ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
return CallingConv::ARM_AAPCS;
case CallingConv::Fast:
if (!Subtarget->isAAPCS_ABI()) {
- if (Subtarget->hasVFP2() && !isVarArg)
+ if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
return CallingConv::Fast;
return CallingConv::ARM_APCS;
- } else if (Subtarget->hasVFP2() && !isVarArg)
+ } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
return CallingConv::ARM_AAPCS_VFP;
else
return CallingConv::ARM_AAPCS;
diff --git a/llvm/test/CodeGen/Thumb/fastcc.ll b/llvm/test/CodeGen/Thumb/fastcc.ll
new file mode 100644
index 00000000000..98ff684d2ec
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb/fastcc.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mcpu=arm926ej-s -mattr=+vfp2
+
+; This is a regression test, to ensure that fastcc functions are correctly
+; handled when compiling for a processor which has a floating-point unit which
+; is not accessible from the selected instruction set.
+
+target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv5e-none-linux-gnueabi"
+
+; Function Attrs: optsize
+define fastcc void @_foo(float %walpha) #0 {
+entry:
+ br label %for.body13
+
+for.body13: ; preds = %for.body13, %entry
+ br i1 undef, label %for.end182.critedge, label %for.body13
+
+for.end182.critedge: ; preds = %for.body13
+ %conv183 = fpext float %walpha to double
+ %mul184 = fmul double %conv183, 8.200000e-01
+ %conv185 = fptrunc double %mul184 to float
+ %conv188 = fpext float %conv185 to double
+ %mul189 = fmul double %conv188, 6.000000e-01
+ %conv190 = fptrunc double %mul189 to float
+ br label %for.body193
+
+for.body193: ; preds = %for.body193, %for.end182.critedge
+ %mul195 = fmul float %conv190, undef
+ br label %for.body193
+}
+
+attributes #0 = { optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.ident = !{!0}
+
+!0 = metadata !{metadata !"clang version 3.5.0 "}
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