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* debuginfo-tests: Add support for an lldb wrapper scriptAdrian Prantl2013-09-061-1/+18
| | | | | | to be used on darwin in lieu of gdb. llvm-svn: 190186
* mi-sched: cleanup register pressure update, remove a FIXME.Andrew Trick2013-09-063-20/+32
| | | | llvm-svn: 190181
* mi-sched: improve regpressure tracing.Andrew Trick2013-09-061-2/+7
| | | | llvm-svn: 190180
* mi-sched: print tree size in -view-misched-dagsAndrew Trick2013-09-061-1/+5
| | | | llvm-svn: 190179
* mi-sched: register pressure update tracing.Andrew Trick2013-09-061-0/+4
| | | | llvm-svn: 190178
* mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.Andrew Trick2013-09-061-4/+4
| | | | | | The latency based scheduling could induce spills in some cases. llvm-svn: 190177
* Added MachineSchedPolicy.Andrew Trick2013-09-063-37/+88
| | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. llvm-svn: 190176
* msbuild integration: provide separate files for VS2010 and VS2012Hans Wennborg2013-09-066-35/+58
| | | | | | | | | The previous msbuild integration only worked if VS2010 was installed. This patch renames the current integration to LLVM-vs2010 and adds LLVM-vs2012. Differential Revision: http://llvm-reviews.chandlerc.com/D1614 llvm-svn: 190173
* avoid unnecessary direct access to LiveInterval::rangesMatthias Braun2013-09-064-34/+37
| | | | llvm-svn: 190170
* remove unused argument from LiveRanges::join()Matthias Braun2013-09-063-6/+3
| | | | llvm-svn: 190169
* remove pointless assertMatthias Braun2013-09-061-2/+0
| | | | | | The if above it ensures the property anyway. llvm-svn: 190168
* fix commentMatthias Braun2013-09-061-1/+1
| | | | | | There's no 'B3' in the example. llvm-svn: 190167
* fix typo in commentMatthias Braun2013-09-061-1/+1
| | | | llvm-svn: 190165
* [mips][msa] IndentationDaniel Sanders2013-09-061-34/+34
| | | | llvm-svn: 190156
* [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritanceDaniel Sanders2013-09-061-628/+628
| | | | | | | Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-065-5/+61
| | | | | | Test cases are included in patch. llvm-svn: 190154
* [mips][msa] Made the operand register sets optional for the VEC formatsDaniel Sanders2013-09-061-16/+9
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190153
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-066-8/+68
| | | | | | cases are included in patch. llvm-svn: 190152
* [mips][msa] Made the operand register sets optional for the ELM_INSVE formatsDaniel Sanders2013-09-061-14/+10
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190151
* [mips][msa] Made the operand register sets optional for the 3RF_4RF formatDaniel Sanders2013-09-061-14/+14
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190150
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-067-8/+83
| | | | | | cases are included in patch. llvm-svn: 190148
* SelectionDAG: create correct BooleanContent constantsTim Northover2013-09-063-2/+72
| | | | | | | | | | | | | | | Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. llvm-svn: 190147
* [mips][msa] Made the operand register sets optional for the 3RF formatsDaniel Sanders2013-09-061-132/+72
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190146
* [mips][msa] Made the operand register sets optional for the 3R_4R formatDaniel Sanders2013-09-061-30/+22
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190145
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-064-17/+391
| | | | | | check tests. llvm-svn: 190144
* [mips][msa] Made the operand register sets optional for the 2RF formatDaniel Sanders2013-09-061-59/+39
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190143
* [mips][msa] Made the operand register sets optional for the I8 formatDaniel Sanders2013-09-061-21/+12
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190142
* [mips][msa] Made the operand register sets optional for the I5 and SI5 formatsDaniel Sanders2013-09-061-74/+46
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190141
* [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formatsDaniel Sanders2013-09-061-104/+60
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190140
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-067-121/+223
| | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. llvm-svn: 190138
* [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element sizeDaniel Sanders2013-09-061-16/+16
| | | | | | No functional change llvm-svn: 190134
* [mips][msa] Made the operand register sets optional for the 3R formatDaniel Sanders2013-09-061-460/+280
| | | | | | | | Their default is to be the same as the result register set. No functional change llvm-svn: 190133
* [mips][msa] Made the InstrItinClass argument optional since it is always ↵Daniel Sanders2013-09-061-600/+607
| | | | | | | | NoItinerary at the moment. No functional change llvm-svn: 190131
* [SystemZ] Use XC for a memset of 0Richard Sandiford2013-09-062-50/+47
| | | | llvm-svn: 190130
* Use type helper functions.Matt Arsenault2013-09-064-6/+5
| | | | llvm-svn: 190113
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-062-4/+32
| | | | llvm-svn: 190112
* R600: Coding styleTom Stellard2013-09-051-6/+4
| | | | llvm-svn: 190110
* [X86] Perform VSELECT DAG combines also before DAG type legalization.Juergen Ributzka2013-09-052-12/+12
| | | | | | | | | | | | If the DAG already has only legal types, then the second round of DAG combines is skipped. In this case VSELECT+SETCC patterns that match a more efficient instruction (e.g. min/max) are never recognized. This fix allows VSELECT+SETCC combines if the types are already legal before DAG type legalization. Reviewer: Nadav llvm-svn: 190105
* Fixed a crash in the integrated assembler for Mach-O when a symbol differenceKevin Enderby2013-09-052-0/+42
| | | | | | | | | | | | | expression uses an assembler temporary symbol from an assignment.  In this case the symbol does not have a fragment so the use of getFragment() would be NULL and caused a crash. In the case of an assembler temporary symbol we want to use the AliasedSymbol (if any) which will create a local relocation entry, but if it is not an assembler temporary symbol then let it use that symbol with an external relocation entry. rdar://9356266 llvm-svn: 190096
* Consistently use dbgs() in debug printingMatt Arsenault2013-09-054-17/+17
| | | | llvm-svn: 190093
* Trying to un-break the bots.Manman Ren2013-09-051-1/+2
| | | | llvm-svn: 190092
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-052-0/+20
| | | | llvm-svn: 190091
* Remove unused argument.Rafael Espindola2013-09-051-3/+1
| | | | llvm-svn: 190090
* Improve handling of .file, .include and .incbin directives toYunzhong Gao2013-09-054-15/+19
| | | | | | | | | allow escaped octal character sequences. The patch was discussed in Phabricator. See: http://llvm-reviews.chandlerc.com/D1289 llvm-svn: 190089
* Debug Info: Use identifier to reference DIType in base type field ofManman Ren2013-09-057-6/+156
| | | | | | | | | | | | | | | | | | | | | | ptr_to_member. We introduce a new class DITypeRef that represents a reference to a DIType. It wraps around a Value*, which can be either an identifier in MDString or an actual MDNode. The class has a helper function "resolve" that finds the actual MDNode for a given DITypeRef. We specialize getFieldAs to return a field that is a reference to a DIType. To correctly access the base type field of ptr_to_member, getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef. Also add a typedef for DITypeIdentifierMap and a helper generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually populate the map. Verifier is updated accordingly. llvm-svn: 190081
* R600: Add support for local memory atomic addTom Stellard2013-09-058-14/+101
| | | | llvm-svn: 190080
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-053-15/+52
| | | | llvm-svn: 190079
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-053-4/+40
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. llvm-svn: 190078
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-053-1/+16
| | | | llvm-svn: 190077
* R600: Fix segfault in R600TextureIntrinsicReplacerTom Stellard2013-09-051-0/+3
| | | | | | | | | | This pass was segfaulting when it ran into a non-intrinsic function call. Function calls are not supported, so now instead of segfaulting, we will get an assertion failure with a nice error message. I'm not sure how to test this using lit. llvm-svn: 190076
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