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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-09-05 19:41:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-09-05 19:41:10 +0000 |
| commit | 6f2437997490e909546ea59cba02080f256d58cd (patch) | |
| tree | d90451e68ce3be782e1c46bc461f2dc6754c0616 /llvm | |
| parent | d21ac19bdaa686944164c6f1f298fdfcba0ef80e (diff) | |
| download | bcm5719-llvm-6f2437997490e909546ea59cba02080f256d58cd.tar.gz bcm5719-llvm-6f2437997490e909546ea59cba02080f256d58cd.zip | |
R600: Fix i64 to i32 trunc on SI
llvm-svn: 190091
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/trunc.ll | 19 |
2 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index f196059b894..05b7b5d9b74 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -90,6 +90,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(MVT::i64, MVT::i32, Expand); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); diff --git a/llvm/test/CodeGen/R600/trunc.ll b/llvm/test/CodeGen/R600/trunc.ll new file mode 100644 index 00000000000..d94d4fe7a47 --- /dev/null +++ b/llvm/test/CodeGen/R600/trunc.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s + + +define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { +; SI-LABEL: @trunc_i64_to_i32_store +; SI: S_LOAD_DWORD SGPR0, SGPR0_SGPR1, 11 +; SI: V_MOV_B32_e32 VGPR0, SGPR0 +; SI: BUFFER_STORE_DWORD VGPR0 + +; EG-LABEL: @trunc_i64_to_i32_store +; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG: LSHR +; EG-NEXT: 2( + + %result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + |
